CN116599496A - Circuit structure of half-band FIR filter - Google Patents
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- CN116599496A CN116599496A CN202310874209.XA CN202310874209A CN116599496A CN 116599496 A CN116599496 A CN 116599496A CN 202310874209 A CN202310874209 A CN 202310874209A CN 116599496 A CN116599496 A CN 116599496A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
- H03H17/0223—Computation saving measures; Accelerating measures
- H03H17/0225—Measures concerning the multipliers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
- H03H17/0219—Compensation of undesirable effects, e.g. quantisation noise, overflow
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H2017/0072—Theoretical filter design
- H03H2017/0081—Theoretical filter design of FIR filters
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The invention discloses a circuit structure of a half-band FIR filter, which belongs to the technical field of digital signal processing and is mainly divided into three parts, namely a symmetrical shift register chain, a multiplication and addition logic operation storage module and an accumulation storage module. The symmetrical shift register chain stores the data quantity required by the filter operation; the multiplication and addition logic operation storage module calculates the operation result of each step in the filter formula, groups the operation results of each step according to the bit width size similarity, adds the operation results two by two and stores the operation results in a corresponding register; the accumulation storage module adds all multiplication and addition operation results of all orders in one clock period to obtain a final output, and the final output result is obtained through n steps of accumulation, namely the final result is obtained in a plurality of clock periods through pipeline structure.
Description
Technical Field
The invention relates to the technical field of digital signal processing, in particular to a circuit structure of a half-band FIR filter.
Background
A half band filter is a special FIR filter whose order can only be even and whose length is odd (i.e., an N-order filter, n+1 taps). Except for the intermediate value of 0.5, the coefficients with the even numbers are all 0, so that multiplication and addition operations during filtering are also greatly saved. A half-band filter is a special low-pass FIR digital filter that has nearly half of the filter coefficients exactly zero, since the pass band and stop band are symmetrical about one half of the Nyquist frequency.
General frequency of half-band FIR filterThe response is shown in FIG. 1, whereRepresenting passband ripple->Representing stop band ripple->Represents passband side frequency, ">Representing the stop band side frequency. A half-band FIR filter typically has several characteristics: (1) Passband ripple->And stop band ripple->Equal, i.e.)>The method comprises the steps of carrying out a first treatment on the surface of the (2) Passband side frequency->And stop band side frequency->Relative to->Is symmetrical, i.e.)>The method comprises the steps of carrying out a first treatment on the surface of the (3) The coefficients of the filter have an even symmetry characteristic and the filter length is even (the filter order is odd). The impulse response values of all even numbered filters larger than 0 are 0, and the characteristic of the half-band filter greatly reduces the multiplication and addition times required by the operation of the filter; (4) After filtering by a half-band filter, when 2 times of extraction is performed, the signal passband has no spectrum aliasing, but the stopband has spectrum aliasing.
The passband ripple is equal to the stopband ripple and these characteristics are reflected in the impulse response of the filter. For example, for a filter with an odd number of tap coefficients, approximately half of the coefficients are zero and interleaved between non-zero coefficients, as shown in FIG. 2, are half-band filters with 11 taps; in designing a half-band FIR filter, a circuit configuration as shown in fig. 3 can be obtained based on the characteristics of the half-band filter: in the figure a 2n represents the coefficient value of the corresponding order, where D represents a register, x n represents the input signal, and y n represents the output signal.
The conventional circuit structure as shown in fig. 3 has various problems: (1) In order to pursue higher precision output and steeper amplitude-frequency response, which cannot be applied to high-speed digital circuits, the required output is usually higher in order, which has a longer critical path and more arithmetic units, and is difficult to complete in one clock cycle. (2) There is a larger power consumption loss and a larger area, more LVT transistors can be used to achieve faster speed performance under the same clock constraint to meet the condition, the threshold voltage of the LVT transistors is low, the power consumption is larger, and the larger area is occupied after synthesis, which leads to increased cost.
Disclosure of Invention
The invention aims to provide a half-band FIR filter circuit structure to solve the problems in the background technology.
In order to solve the above technical problems, the present invention provides a circuit structure of a half-band FIR filter, including:
a symmetrical shift register chain for storing the data amount required by the filter operation;
the multiplication and addition logic operation storage module calculates the operation result of each order in the filter formula, groups the operation results of each order according to the bit width size similarity, adds the operation results two by two and stores the operation results in the corresponding register;
and the accumulation storage module is used for obtaining a final output result through n steps of accumulation, namely obtaining the final result in a plurality of clock cycles through pipeline structure.
In one embodiment, the symmetrical shift register chain comprises (n+1) D flip-flops and [ (n-1)/4 ] adders sequentially connected in series, and the symbol [ ] represents an upward rounding;
one positive input end of the first adder is connected with the input end of the first D trigger, and the other positive input end of the first adder is connected with the output end of the (n+1) th D trigger;
one positive input end of the second adder is connected with the input end of the third D trigger, and the other positive input end of the second adder is connected with the output end of the (n-1) th D trigger;
...；
one positive input end of the [ (n-1)/4 ] adder is connected with the input end of the [ (n+1)/2 ] D trigger, and the other positive input end is connected with the output end of the [ (n+1)/2+1 ] D trigger.
In one embodiment, the symmetrical shift register chain outputs [ (n-1)/4 ] +1 output results, the former [ (n-1)/4 ] output results are output from the output end of each adder, and the [ (n-1)/4 ] +1 output results are output from the output end of the [ (n+1)/2 ] D flip-flop.
In one embodiment, the multiplication and addition logic operation storage module comprises [ (n-1)/4 ] +1 multipliers, ([ (n-1)/4 ] +1)/2 adders and ([ (n-1)/4 ] +1)/2 registers, each output result output by the symmetrical shift register chain is respectively input into one multiplier, the output ends of every two multipliers are connected with the input end of one adder, and the output end of each adder is connected with the input end of one register.
In one embodiment, the accumulation memory module includes [ ([ (n-1)/4 ] +1 adders and [ ([ (n-1)/4 ] +1)/4 ] registers, one adder being connected to one register, all registers being input to the last adder, the last adder outputting y [ n ].
The circuit structure of the half-band FIR filter provided by the invention breaks an original lengthy addition chain, has a short critical path and is easy to realize in a high-speed circuit; and the symmetrical FIR structure is used for reducing hardware consumption, and the comprehensive implementation can be realized by using only RVT process libraries, and the pipeline structure avoids using LVT process libraries, so that the total hardware consumption is smaller than that realized by RVT. The invention can disable the LVT process library in comprehensive constraint, and can effectively achieveLow power consumption and low complexity; on the basis of using the same process nodes, the comprehensive implementation is carried out on the traditional structure and the structure provided by the invention, the clock frequency is restricted at 400MHz, and the area of the netlist after the comprehensive implementation is 8577.156The latter synthesis achieves a netlist area of 6713.000 +.>The method comprises the steps of carrying out a first treatment on the surface of the And the former uses a large number of RVT transistors to make the circuit barely satisfactory for timing at 400MHz, while the latter can be satisfactory with only LVT process libraries and can satisfy higher clock frequency constraints.
Drawings
Fig. 1 is a schematic diagram of a general frequency response curve of a half-band FIR filter.
Fig. 2 is a schematic diagram of tap coefficients of a half-band filter with 11 taps.
Fig. 3 is a schematic diagram of a conventional half-band FIR filter circuit structure.
Fig. 4 is an overall block diagram of a half-band FIR filter circuit according to the present invention.
FIG. 5 is a schematic diagram of an n-step calculation of the accumulation memory module.
Fig. 6 is a schematic diagram of a circuit detail structure of a half-band FIR filter according to the present invention.
Fig. 7 is a graph showing the amplitude-frequency response of the 19 th order.
Detailed Description
The following describes a circuit structure of a half-band FIR filter according to the present invention in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
The invention provides a circuit structure of a half-band FIR filter, which adopts a symmetrical structure design to reduce unnecessary consumption of a multiplier; and a half-band FIR filter is split into a two-section or three-section structure through a pipeline structure, and is judged according to the order length; in addition, the filter coefficients are sorted in groups according to the sizes of the coefficients and expanded according to the bits, so that the filter coefficients are prevented from being expanded according to the maximum bit width, unnecessary register areas are wasted, and the whole structure is shown in fig. 4.
The half-band FIR filter of the invention is mainly divided into three parts of a symmetrical shift register chain, a multiplication and addition logic operation storage module and an accumulation storage module. The symmetrical shift register chain stores the data quantity required by the filter operation; the multiplication and addition logic operation storage module calculates the operation result of each order in the filter formula, groups the operation results of each order according to the bit width size similarity, adds the operation results two by two and stores the operation results in a corresponding register; the accumulation storage module adds all the multiplication and addition operation results of all the orders in one clock cycle to obtain a final output, and the final output result is obtained through n steps of accumulation, namely, the final result is obtained in a plurality of clock cycles through pipeline structure implementation, as shown in fig. 5.
The specific structure of the half-band FIR filter is shown in fig. 6, and it is assumed that the number of tap coefficients of the half-band FIR filter is n, and the characteristic of the half-band FIR filter is that the odd tap coefficient is 0, and (n-1)/2 constant multipliers are required. In order to ensure that the adder chain is not too long, so that the whole circuit cannot work under too high frequency, a pipeline structure, namely a D trigger is inserted to improve the working frequency of the whole circuit, and the whole structure is divided into three stages of pipeline structures.
The first stage symmetrical shift register chain comprises (n+1) D flip-flops and [ (n-1)/4 ] adders which are sequentially connected in series, and the symbol [ ] represents upward rounding. One positive input end of the first adder is connected with the input end of the first D trigger, and the other positive input end of the first adder is connected with the output end of the (n+1) th D trigger; one positive input of the second adder is connected with the input end of the third D trigger, the other positive input is connected with the output end of the (n-1) th D trigger, the positive input of the [ (n-1)/4 ] th adder is connected with the input end of the [ (n+1)/2 ] th D trigger, and the other positive input is connected with the output end of the [ (n+1)/2+1 ] th D trigger. The symmetrical shift register chain outputs [ (n-1)/4 ] +1 output results, the former [ (n-1)/4 ] output results are respectively output from the output end of each adder, and the [ (n-1)/4 ] +1 output results are output from the output end of the [ (n+1)/2 ] D trigger.
The second-stage multiplication and addition logic operation storage module comprises [ (n-1)/4 ] +1 multipliers, ([ (n-1)/4 ] +1)/2 adders and ([ (n-1)/4 ] +1)/2 registers, each output result is respectively input into one multiplier, the output end of each two multipliers is connected with the input end of one adder, and the output end of each adder is connected with the input end of one register.
The third-stage accumulation storage module comprises [ ([ (n-1)/4 ] +1 adders and [ ([ (n-1)/4 ] +1)/4 ] registers, one adder is connected with one register, all registers are input into the last (namely [ ([ (n-1)/4 ] +1) adder, and finally [ ([ (n-1)/4 ] +1 adder output y [ n ].
In this embodiment, a 19-order half-band FIR filter is taken as an example, that is, the tap coefficient n of the half-band FIR filter is 19, and when the amplitude-frequency response curve is satisfied, the curve is shown in fig. 7. The corresponding filter coefficients are shown in table 1, and the quantization process is allowed to be performed according to 18 bits when the hardware implementation is performed according to the quantization criterion, which is shown in the third column shown in table 1:
if all coefficients are expanded to 18 bits according to the conventional scheme and then logic operation is performed, the bit width of each coefficient is set to be enough not to overflow, and the maximum bit width of the corresponding coefficient is calculated as shown in table 2:
if input signal x [ n ]]Is 16 bits in bit width, and is calculated in the first clock period，/>，The three multiplication and addition calculation formulas respectively pass through a D trigger to obtain three results with basic bit widths of 27, 31 and 33 respectively; and adding the first two output results and respectively passing the third output result through a D trigger in the second clock period to obtain two output results, wherein the basic bit widths of the obtained two output results are respectively 32 and 33. The third clock period adds the two output results of the previous stage by a D trigger to obtain the final calculation result y [ n ]]The bit width of the final output result is 33 bits, so that the problem that the output result cannot overflow or be saturated can be guaranteed. If calculated according to the conventional structure, the coefficients must be quantized as in table 1 to calculate the theoretical final output result bit width of 39 bits.
The invention combines the same multipliers through symmetrical FIR structures, reduces the consumption of the multipliers, reduces the consumption of hardware on the basis of not affecting the half-band FIR filter, and optimizes the area of a digital circuit; the addition chain of one half-band FIR filter is optimized to a key path through a multi-step calculation method by a pipeline structure, the calculation steps are determined according to the designed order length of the half-band FIR filter, and the longer the order is, the longer the split calculation steps are. In the above embodiment, the multiplication and addition calculation result of the 19 th order half-band FIR filter has 6 terms, and only needs to be divided into two steps for calculation. In addition, the grouping ordering is carried out according to the coefficient size, the bit expansion is carried out, and the situation that the filter coefficients are all subjected to the bit expansion calculation according to the maximum bit width is avoided, so that unnecessary register area is wasted. The half-band FIR filter circuit structure can be realized by only using an RVT process library when in synthesis, the critical path is short, and the time sequence constraint can meet higher clock frequency.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.
Claims (5)
1. A half-band FIR filter circuit structure, comprising:
a symmetrical shift register chain for storing the data amount required by the filter operation;
the multiplication and addition logic operation storage module calculates the operation result of each order in the filter formula, groups the operation results of each order according to the bit width size similarity, adds the operation results two by two and stores the operation results in the corresponding register;
and the accumulation storage module is used for obtaining a final output result through n steps of accumulation, namely obtaining the final result in a plurality of clock cycles through pipeline structure.
2. The half-band FIR filter circuit structure according to claim 1, characterized in that the symmetrical shift register chain comprises (n+1) D flip-flops and [ (n-1)/4 ] adders sequentially connected in series, the symbol [ ] representing an upward rounding;
one positive input end of the first adder is connected with the input end of the first D trigger, and the other positive input end of the first adder is connected with the output end of the (n+1) th D trigger;
one positive input end of the second adder is connected with the input end of the third D trigger, and the other positive input end of the second adder is connected with the output end of the (n-1) th D trigger;
...；
one positive input end of the [ (n-1)/4 ] adder is connected with the input end of the [ (n+1)/2 ] D trigger, and the other positive input end is connected with the output end of the [ (n+1)/2+1 ] D trigger.
3. The half-band FIR filter circuit structure according to claim 2, characterized in that the symmetrical shift register chain outputs [ (n-1)/4 ] +1 output results, the former [ (n-1)/4 ] output results being output from the output terminal of each adder, respectively, [ -1)/4 ] +1 output results being output from the output terminal of the [ (n+1)/2 ] D flip-flop.
4. A half-band FIR filter circuit arrangement according to claim 3, characterized in that the multiply-add logic memory module comprises [ (n-1)/4 ] +1 multipliers, ([ (n-1)/4 ] +1)/2 adders and ([ (n-1)/4 ] +1)/2 registers, each output result of the symmetrical shift register chain output being input to one multiplier respectively, the output of each multiplier being connected to the input of one adder, the output of each adder being connected to the input of one register.
5. The half-band FIR filter circuit arrangement according to claim 4, characterized in that the accumulation memory module comprises [ ([ (n-1)/4 ] +1 adders and [ ([ (n-1)/4 ] +1)/4 ] registers, one adder being connected to one register, all registers being input to the last adder, the last adder outputting y [ n ].
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10322164A (en) * | 1997-05-21 | 1998-12-04 | Nec Corp | Digital filter |
| CN102185587A (en) * | 2011-03-21 | 2011-09-14 | 浙江大学 | Low-power-consumption multi-order interpolation half-band filter with two-phase structure |
| CN104467739A (en) * | 2014-12-15 | 2015-03-25 | 天津大学 | Bandwidth-adjustable and center-frequency-adjustable digital filter and implementation method thereof |
| CN106059530A (en) * | 2016-05-25 | 2016-10-26 | 东南大学 | Half-band filter structure with frequency response weakly correlated with coefficient quantization digit |
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- 2023-07-17 CN CN202310874209.XA patent/CN116599496A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10322164A (en) * | 1997-05-21 | 1998-12-04 | Nec Corp | Digital filter |
| CN102185587A (en) * | 2011-03-21 | 2011-09-14 | 浙江大学 | Low-power-consumption multi-order interpolation half-band filter with two-phase structure |
| CN104467739A (en) * | 2014-12-15 | 2015-03-25 | 天津大学 | Bandwidth-adjustable and center-frequency-adjustable digital filter and implementation method thereof |
| CN106059530A (en) * | 2016-05-25 | 2016-10-26 | 东南大学 | Half-band filter structure with frequency response weakly correlated with coefficient quantization digit |
Non-Patent Citations (1)
| Title |
|---|
| YU PAN: "Bit-Level Optimization of Adder-Trees for Multiple Constant Multiplications for Efficient FIR Filter Implementation", IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, pages 1 - 8 * |
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