CN116594955A - Dynamic global reconfigurable method based on DSP chip - Google Patents
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Abstract
The invention relates to the technical field of DSP application, in particular to a dynamic global reconfigurable method based on a DSP chip. After the starting parameters in the FLASH and the mirror image data are all programmed, the system is electrified and operated, at the moment, the DSP executes mirror image starting, initializes the peripheral devices and then starts to receive protocol data transmitted from the outside; after receiving the protocol data, firstly analyzing the protocol, and then executing corresponding operation, such as starting reconstruction, according to the analyzed command word; during reconstruction, according to the analyzed protocol data, firstly reading out the starting parameters stored in the FLASH, changing the mirror image data pointed at the starting time from the execution mirror image to the reconstruction mirror image through modifying the parameters, then controlling the DSP to reset, and finally entering the reboot; after the DSP re-BOOT, the reconstructed image is started. The invention mainly solves the problem that in a DSP+FPGA heterogeneous platform, the system service can not be switched according to the need because the software of the DSP chip can not be reconstructed as conveniently as the FPGA chip.
Description
Technical Field
The invention relates to the technical field of DSP application, in particular to a dynamic global reconfigurable method based on a DSP chip.
Background
From historical experience in the development of computing systems, it can be seen that there is a natural discrepancy between computing performance, computing efficiency, and computing flexibility. A number of studies and practices have led to the proposal of reconfigurable computing techniques. Reconfigurable computing refers to a form of computing organization that enables spatial mapping of algorithms to compute engines, and also has customization capabilities after being manufactured into integrated circuits. The method can flexibly switch in a certain range of application sets, maintain flexibility and realize high utilization rate of computing resources.
The dynamic reconfiguration is a branch of reconfigurable computation, which realizes the time division multiplexing of hardware resources, can effectively improve the flexibility and reliability of an embedded system, and enables the system to realize the most efficient multi-task processing capability on the basis of paying the minimum hardware cost. The dynamic reconfigurable technology is applied to an FPGA platform at the earliest, has a plurality of research results, and is widely applied to the front-edge technological fields of aerospace, power electronic engineering, computer science and the like.
However, in the conventional dsp+fpga heterogeneous multi-core platform, since the service is an integral unit, and includes the program of the FPGA and the program of the DSP, only the FPGA program is reconstructed, and the entire service cannot be switched as required, it is necessary to develop a dynamic global reconfigurable method based on the DSP chip to solve the above-mentioned problems.
Disclosure of Invention
The invention aims to provide a dynamic global reconfigurable method based on a DSP chip, which mainly solves the problem that in a DSP+FPGA heterogeneous platform, system service can not be switched as required because software of the DSP chip can not be reconfigured as conveniently as an FPGA chip.
In order to solve the technical problems, the invention provides a dynamic global reconfigurable method based on a DSP chip, which comprises the following steps:
step S1: modifying an official programming tool chain, changing execution steps and processes, and dividing each image file used for programming a DSP chip into a starting parameter file param.dat and an image data file image.dat through the programming tool chain;
step S2: the method comprises the steps of executing an image A by using any one of the generated starting parameter files param and image data file image_A.dat used when a DSP chip is electrified and started, and writing a reconstructed image B into a FLASH of the DSP chip in a partition mode by using the reconstructed image data file image_B.dat; the starting parameter file param.dat occupies the first 1024 bytes of FLASH from the 0 address, and the execution mirror image A and the reconstruction mirror image B are sequentially programmed into different partitions which are not overlapped with each other according to the actual size of the execution mirror image A and the reconstruction mirror image B;
step S3: after the DSP chip is electrified, executing the mirror image A to start running, and receiving external protocol data through a peripheral interface in the running process, wherein the protocol content is defined in advance;
step S4: analyzing protocol data, and starting to execute a reconstruction flow when analyzing the reconstruction command and the position information of the reconstruction mirror image B stored in the FLASH;
step S5: firstly, reading out data of a parameter file param.dat in FLASH, then modifying the starting mirror image position field data into position information data obtained in the step S4, and finally writing back to FLASH;
step S6: and controlling the DSP chip to be in soft reset, enabling the DSP chip to enter a BOOT resetting flow, and then automatically starting the reconstructed image B.
Preferably, the method for dividing the image file into a parameter file and an image data file includes, but is not limited to, modifying an official write tool chain.
Preferably, the start-up parameter file includes, but is not limited to, an SPI parameter used in an SPI BOOT mode and an EMIF parameter used in an EMIF BOOT mode.
Preferably, the software API interface called by the DSP chip in the reconstruction process comprises the following functions:
ParamTableNorwrite () function: the method is used for writing a starting parameter file into the FLASH;
APPSelect () function: for performing a reconstruction operation;
APPNorWrite () function: the method is used for writing mirror image data files into the FLASH;
APPSetBootAddr0 () function: the method is used for setting the mirror image selected when the DSP chip is started and pointing the mirror image to APP0.
Preferably, when a plurality of mirror image files are programmed in FLASH, the files can be reconstructed to any mirror image according to the requirement. For example, when the reconstruction image B is running after a reconstruction operation is performed, steps S3-S6 may be repeated to reconstruct the program into the response image a.
Compared with the prior art, the invention has the following beneficial effects:
(1) The invention provides a general reconstruction method, which not only aims at a specific DSP chip, but also can adjust the communication mode with the outside according to the chip, and has strong applicability under the condition of determining the reconstruction method and the flow.
(2) The invention partitions FLASH and stores different mirror image data files. On the premise of meeting the demand, the specific partition size is completely determined according to the application program, and a plurality of image files can be stored at the same time. When in reconstruction, a plurality of mirror image files can be mutually reconstructed back and forth, and the reconstruction is very flexible. When the method is applied to actual testing, different service functions of the DSP, such as electronic investigation, SAR image processing and network DEMO programs, can be reconstructed in real time as required.
(3) Taking TMS320C6678 multi-core DSP chip of TI company as an example, the method completes the replacement of the mirror image program operated by the DSP by means of the heavy BOOT of the DSP chip so as to realize the real-time reconstruction of service logic.
Drawings
Fig. 1 is a schematic diagram of hardware connection provided in the present invention.
Fig. 2 is a FLASH memory allocation diagram provided by the present invention.
Fig. 3 is a reconstruction flow chart provided by the present invention.
Fig. 4 is a schematic diagram of a software interface for DSP calls provided by the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and the specific examples. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
The embodiment of the invention particularly provides a dynamic global reconfigurable method based on a DSP chip, which can be applied to the TMS320C6678/TMS320C6655/TMS320C6657 and other C66x core DSP chips of TI company. Other series of DSPs, such as domestic FT-M6678, can be used as long as the principle of the starting mode is communicated with the domestic FT-M6678. The embodiment of the invention is suitable for a DSP chip, taking a TMS320C6678 chip produced by TI company as an example, the TMS320C6678 is a multi-core high-performance fixed/floating point DSP which is proposed by TI company and has 8C 66x cores, the highest single-core main frequency can reach 1.4G, the fixed-point computing of 44.8 GMAC/core and the floating point computing capability of 22.4 GFLOP/core, each core has 32KB L1 SRAM, 512KB L2 SRAM,8 cores share 4MB MSRAM and the maximum 2GB DDR space, and the invention is flexible for users to apply. Because of its strong computing power, it is widely used in the fields of mobile communication, aerospace, radar signal processing, industrial detection, high performance computing, etc. (see, in particular, the patent of the invention issued with publication number CN 115185746B).
As shown in fig. 1, in the reconfigurable flow, the DSP needs to receive the protocol data sent by an external device, such as a host computer or other CPU host, and trigger the reconfiguration of the DSP with a specific command word after parsing. The communication interface can be set according to the actual application requirements, and peripheral devices supported by DSPs such as a network port, a serial port, an SRIO and the like can be used. The most typical application scenario is that the upper computer is connected with the DSP through the gigabit Ethernet and controls the DSP to complete the whole flow.
As shown in fig. 2, the reconstruction operation requires a plurality of image files, such as image a (execution image a) executed when the DSP is started, and image B (reconstruction image B) running after reconstruction, or even more images C, D. In order to improve the instantaneity of the reconstruction process, it is necessary to store these images in different areas of the FLASH in advance. For example, the image occupation area A is executed, the image occupation area B is reconstructed, and the image occupation area A and the image occupation area B are strictly isolated on the memory address and are not overlapped with each other. The first 1kB space of the FLASH from the 0 address fixedly stores the starting parameters of the DSP, the sizes of all the areas of the mirror image can be set manually according to actual conditions, and the data in the figure are only examples, so long as each area can completely contain corresponding mirror image data. For example, the size of the mirror image is 2.1MB, the corresponding area may be set to 2.5MB or 3MB.
As shown in fig. 3, after the starting parameters in the FLASH and the mirror image data are all programmed, the system is powered on to run, at this time, the DSP executes mirror image starting, initializes the peripheral devices, and then starts to receive externally transmitted protocol data; after receiving the protocol data, firstly analyzing the protocol, and then executing corresponding operation, such as starting reconstruction, according to the analyzed command word; during reconstruction, according to the analyzed protocol data, firstly reading out the starting parameters stored in the FLASH, changing the mirror image data pointed at the starting time from the execution mirror image to the reconstruction mirror image through modifying the parameters, then controlling the DSP to reset, and finally entering the reboot; after the DSP re-BOOT, the reconstructed image is started.
And dividing the image file used by the DSP programming into two parts, namely a startup parameter file and an image data file. The method for dividing the file is not limited to modifying the official writing tool chain, but can be used in other ways, but the core is to divide the image file into a parameter file and an image data file. The starting parameter file includes parameters used by other starting modes supported by the DSP besides SPI parameters used by a common SPI BOOT mode, EMIF parameters used by an EMIF BOOT mode and the like.
As shown in fig. 4, where the ParamTableNorWrite () function is used to write a start-up parameter file into FLASH, the APPSelect () function is used to perform a reconstruction operation, the APPNorWrite () function is used to write a mirror data file into FLASH, and the APPSetBootAddr0 () function is used to set the mirror selected at start-up of the DSP, pointing it to APP0.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.
Claims (6)
1. The dynamic global reconstruction method based on the DSP chip is characterized by comprising the following steps of:
step S1: modifying an official programming tool chain, changing execution steps and processes, and dividing each image file used for programming a DSP chip into a starting parameter file param.dat and an image data file image.dat through the programming tool chain;
step S2: the method comprises the steps of executing an image A by using any one of the generated starting parameter files param and image data file image_A.dat used when a DSP chip is electrified and started, and writing a reconstructed image B into a FLASH of the DSP chip in a partition mode by using the reconstructed image data file image_B.dat; the starting parameter file param.dat occupies the first 1024 bytes of FLASH from the 0 address, and the execution mirror image A and the reconstruction mirror image B are sequentially programmed into different partitions which are not overlapped with each other according to the actual size of the execution mirror image A and the reconstruction mirror image B;
step S3: after the DSP chip is electrified, executing the mirror image A to start running, and receiving external protocol data through a peripheral interface in the running process, wherein the protocol content is defined in advance;
step S4: analyzing protocol data, and starting to execute a reconstruction flow when analyzing the reconstruction command and the position information of the reconstruction mirror image B stored in the FLASH;
step S5: firstly, reading out data of a parameter file param.dat in FLASH, then modifying the starting mirror image position field data into position information data obtained in the step S4, and finally writing back to FLASH;
step S6: and controlling the DSP chip to be in soft reset, enabling the DSP chip to enter a BOOT resetting flow, and then automatically starting the reconstructed image B.
2. A dynamic global reconstruction method based on a DSP chip as in claim 1 wherein the method of splitting the image file into a startup parameter file and an image data file includes, but is not limited to, modifying an official burn tool chain.
3. A dynamic global reconfigurable method based on a DSP chip as claimed in claim 1, wherein the start-up parameter file includes, but is not limited to, SPI parameters used in the SPI BOOT mode and EMIF parameters used in the EMIF BOOT mode.
4. The dynamic global reconfigurable method of claim 1, wherein the software API interface invoked by the DSP chip during the reconfiguration process comprises the following functions:
ParamTableNorwrite () function: the method is used for writing a starting parameter file into the FLASH;
APPSelect () function: for performing a reconstruction operation;
APPNorWrite () function: the method is used for writing mirror image data files into the FLASH;
APPSetBootAddr0 () function: the method is used for setting the mirror image selected when the DSP chip is started and pointing the mirror image to APP0.
5. A dynamic global reconstruction method based on a DSP chip as claimed in any one of claims 1-4, wherein when a plurality of image files are written in FLASH, they can be reconstructed to any image as required.
6. The method of claim 5, wherein when the reconfiguration mirror B is running after a reconfiguration operation is performed, steps S3-S6 are repeated to reconstruct the response piece program as mirror a.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109683985A (en) * | 2018-12-19 | 2019-04-26 | 中国电子科技集团公司第五十四研究所 | A kind of more image starting methods of DSP based on AIS order |
| CN113760308A (en) * | 2021-02-05 | 2021-12-07 | 北京沃东天骏信息技术有限公司 | DSP system construction method and device, electronic equipment and storage medium |
| CN115185746A (en) * | 2022-09-07 | 2022-10-14 | 中国电子科技集团公司第五十八研究所 | Context environment backup and recovery method based on C66x multi-core DSP chip |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109683985A (en) * | 2018-12-19 | 2019-04-26 | 中国电子科技集团公司第五十四研究所 | A kind of more image starting methods of DSP based on AIS order |
| CN113760308A (en) * | 2021-02-05 | 2021-12-07 | 北京沃东天骏信息技术有限公司 | DSP system construction method and device, electronic equipment and storage medium |
| CN115185746A (en) * | 2022-09-07 | 2022-10-14 | 中国电子科技集团公司第五十八研究所 | Context environment backup and recovery method based on C66x multi-core DSP chip |
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