CN116578324A - Multi-board FPGA upgrading method, system and storage medium based on ATE equipment - Google Patents

Multi-board FPGA upgrading method, system and storage medium based on ATE equipment Download PDF

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Publication number
CN116578324A
CN116578324A CN202310424407.6A CN202310424407A CN116578324A CN 116578324 A CN116578324 A CN 116578324A CN 202310424407 A CN202310424407 A CN 202310424407A CN 116578324 A CN116578324 A CN 116578324A
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firmware
updated
fpga
board
update
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陆永辉
庞贤明
黄丽婉
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Zhuhai Xinye Measurement And Control Co ltd
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Zhuhai Xinye Measurement And Control Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/60—Software deployment
    • G06F8/65—Updates
    • G06F8/654—Updates using techniques specially adapted for alterable solid state memories, e.g. for EEPROM or flash memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/60—Protecting data
    • G06F21/602—Providing cryptographic facilities or services
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/70—Software maintenance or management
    • G06F8/71—Version control; Configuration management
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • General Physics & Mathematics (AREA)
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Abstract

The application discloses a multi-board FPGA upgrading method, a system and a storage medium based on ATE equipment, which comprise the following steps: acquiring a first secret key through a control board, verifying the first secret key, and opening FLASH writing authorities of the corresponding FPGAs of a plurality of function boards when the verification is passed; judging whether firmware to be updated exists in FLASH of the FPGA according to the update flag bit; when the firmware to be updated does not exist in the FLASH of the FPGA, the control panel is used for acquiring the encrypted firmware data, and the function panel is used for decrypting the encrypted firmware data to obtain the firmware to be updated, so that the firmware to be updated is checked; and when the firmware to be updated exists in the FLASH of the FPGA, starting an updating program to load the firmware to be updated, reading a first firmware version number of the firmware to be updated, and further carrying out version verification on the firmware to be updated according to the first firmware version number. The application improves the safety and reliability of the FPGA upgrade of ATE equipment, and can be widely applied to the technical field of semiconductor chip test.

Description

Multi-board FPGA upgrading method, system and storage medium based on ATE equipment
Technical Field
The application relates to the technical field of semiconductor chip testing, in particular to a multi-board FPGA upgrading method, a system and a storage medium based on ATE equipment.
Background
ATE (Automatic Test Equipment) is an automatic test equipment, which is an aggregate of test instruments controlled by a high-performance computer, which is a test system composed of a tester and a computer, and the computer controls test hardware by running instructions of a tester program. Semiconductor chip ATE is used for detecting the integrity of functions and performances of integrated circuits, and is an important device for ensuring the quality of integrated circuits in the integrated circuit production and manufacturing process, and four processes of tester programming, program compiling, vector loading and test are usually required to be performed on the integrated circuits.
In the prior art, the FPGA firmware upgrading scheme aiming at the ATE test equipment generally reads out the original FPGA firmware information, compares the original FPGA firmware information with the firmware information to be upgraded, and selects information different from the original firmware to write in FLASH. On one hand, when the scheme is updated, communication interruption or machine outage can bring downtime risk to the testing machine, and a protection mechanism for coping with the sudden outage or the sudden disconnection of a communication link is lacked, so that the security of FPGA upgrading is influenced; on the other hand, when the written image file is verified, starting verification is not performed on the new image file, and the condition that the next starting cannot enter firmware due to insufficient verification possibly occurs, so that the reliability of FPGA upgrading is affected.
Disclosure of Invention
The present application aims to solve at least one of the technical problems existing in the prior art to a certain extent.
Therefore, an object of the embodiments of the present application is to provide a multi-board FPGA upgrade method based on ATE equipment, which improves the security and reliability of the FPGA upgrade of the ATE equipment.
Another object of the embodiment of the present application is to provide a multi-board FPGA upgrade system based on ATE equipment.
In order to achieve the technical purpose, the technical scheme adopted by the embodiment of the application comprises the following steps:
in a first aspect, an embodiment of the present application provides a method for upgrading a multi-board FPGA based on ATE equipment, including the following steps:
acquiring a first secret key through a control board, verifying the first secret key, and opening FLASH write-in authorities of the corresponding FPGAs of a plurality of function boards when verification is passed;
judging whether firmware to be updated exists in FLASH of the FPGA according to the update flag bit;
when the firmware to be updated does not exist in the FLASH of the FPGA, acquiring encrypted firmware data through the control board, decrypting the encrypted firmware data through the function board to obtain the firmware to be updated, further checking the firmware to be updated, writing the update flag bit if the checking is successful, and returning to acquire the encrypted firmware data through the control board if the checking is failed;
when firmware to be updated exists in FLASH of the FPGA, an updating program is started to load the firmware to be updated, a first firmware version number of the firmware to be updated is read, and further version verification is carried out on the firmware to be updated according to the first firmware version number;
the control board communicates with a plurality of function boards through a data bus at the same time, so that each function board carries out firmware update at the same time.
Further, in an embodiment of the present application, the method for upgrading a multi-board FPGA further includes the following steps:
and responding to a first operation instruction of a user, generating a corresponding board selection signal, and starting the corresponding FPGA upgrading of the function board through the control board according to the board selection signal.
Further, in one embodiment of the present application, the internal space of the FLASH of the FPGA includes an original code area, an update code area, and a flag data storage area, where the original code area is used to store an original factory code of the FPGA, the update code area is used to store the firmware to be updated, and the flag data storage area is used to store the update flag bit and firmware version information of the function board.
Further, in one embodiment of the present application, the step of obtaining the encrypted firmware data through the control board and decrypting the encrypted firmware data through the function board to obtain the firmware to be updated specifically includes:
the control board acquires the encrypted firmware data from the upper computer and sends the encrypted firmware data to the corresponding function board;
and decrypting the encrypted firmware data through the function board to obtain the firmware to be updated, and writing the firmware to be updated into the updating code area.
Further, in one embodiment of the present application, the step of verifying the firmware to be updated specifically includes:
performing CRC on the firmware to be updated;
when the CRC check fails, the updating code area is erased, and the control board is returned to acquire the encrypted firmware data;
and when the CRC check is successful, enabling the firmware to be reloaded, carrying out reloading check, if the reloading check is successful, setting the update mark position to be in a state waiting for update, and if the reloading check is failed, returning to acquire the encrypted firmware data through the control board.
Further, in an embodiment of the present application, the step of reading the first firmware version number of the firmware to be updated, and further performing version verification on the firmware to be updated according to the first firmware version number specifically includes:
reading the firmware version information from the mark data storage area, and determining the first firmware version number according to the firmware version information;
acquiring a target version number, and determining whether the firmware to be updated is a target updated firmware according to the target version number and the first firmware version number;
and when the firmware to be updated is determined to be the target updated firmware, checking whether the startup initialization state is normal, if so, taking the update mark position as an update completion state, ending the FPGA update of the function board, and if not, jumping to acquire encrypted firmware data through the control board.
Further, in an embodiment of the present application, the step of determining whether the firmware to be updated exists in the FLASH of the FPGA according to the update flag bit specifically includes:
reading the update flag bit from the flag data storage area, determining that firmware to be updated exists in the FLASH of the FPGA when the update flag bit is in a state waiting for update, and determining that the firmware to be updated does not exist in the FLASH of the FPGA when the update flag bit is in a state of completion of update.
In a second aspect, an embodiment of the present application provides a multi-board FPGA upgrade system based on ATE equipment, including:
the key verification module is used for obtaining a first key through the control board, verifying the first key, and opening FLASH write-in authorities of the corresponding FPGAs of the plurality of function boards when the verification is passed;
the flag bit judging module is used for judging whether firmware to be updated exists in FLASH of the FPGA according to the update flag bit;
the firmware verification module is used for obtaining encrypted firmware data through the control board when no firmware to be updated exists in the FLASH of the FPGA, decrypting the encrypted firmware data through the function board to obtain the firmware to be updated, further verifying the firmware to be updated, writing the update flag bit if verification is successful, and returning to obtain the encrypted firmware data through the control board if verification fails;
the version verification module is used for starting an updating program to load the firmware to be updated when the firmware to be updated exists in the FLASH of the FPGA, reading a first firmware version number of the firmware to be updated, and further carrying out version verification on the firmware to be updated according to the first firmware version number;
the control board communicates with a plurality of function boards through a data bus at the same time, so that each function board carries out firmware update at the same time.
In a third aspect, an embodiment of the present application provides a multi-board FPGA upgrade apparatus based on ATE equipment, including:
at least one processor;
at least one memory for storing at least one program;
and when the at least one program is executed by the at least one processor, the at least one processor is caused to implement the multi-board FPGA upgrading method based on the ATE equipment.
In a fourth aspect, an embodiment of the present application further provides a computer readable storage medium, where a processor executable program is stored, where the processor executable program when executed by a processor is configured to perform a multi-board FPGA upgrade method based on an ATE device as described above.
The advantages and benefits of the application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application.
The embodiment of the application firstly obtains the first secret key through the control board, verifies the first secret key, and opens FLASH write-in authorities of the corresponding FPGAs of the plurality of function boards when the verification is passed; judging whether firmware to be updated exists in FLASH of the FPGA according to the update flag bit; when the FLASH of the FPGA does not have the firmware to be updated, acquiring the encrypted firmware data through the control board, decrypting the encrypted firmware data through the function board to obtain the firmware to be updated, further checking the firmware to be updated, writing an update flag bit if the checking is successful, and returning to acquire the encrypted firmware data through the control board if the checking is failed; and when the firmware to be updated exists in the FLASH of the FPGA, starting an updating program to load the firmware to be updated, reading a first firmware version number of the firmware to be updated, and further carrying out version verification on the firmware to be updated according to the first firmware version number. According to the embodiment of the application, the communication connection between the control board and the plurality of functional boards is established by using the parallel bus, so that the plurality of functional boards can be upgraded simultaneously, and the FPGA upgrading efficiency of ATE equipment is improved; by using a CRC file check and reload check double check mechanism, the lossless writing of the firmware file before starting and the smooth starting and working of the written firmware file are ensured, and the safety and reliability of the FPGA upgrading of ATE equipment are improved; after verification by the secret key, the FLASH write-in authority is opened, so that the security of updating the FPGA of the ATE equipment is further improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following description will refer to the drawings that are needed in the embodiments of the present application, and it should be understood that the drawings in the following description are only for convenience and clarity to describe some embodiments in the technical solutions of the present application, and other drawings may be obtained according to these drawings without any inventive effort for those skilled in the art.
Fig. 1 is a step flowchart of a multi-board FPGA upgrading method based on ATE equipment according to an embodiment of the present application;
FIG. 2 is a block diagram of a multi-board FPGA upgrade system based on ATE equipment according to an embodiment of the present application;
fig. 3 is a block diagram of a multi-board FPGA upgrade apparatus based on ATE equipment according to an embodiment of the present application.
Detailed Description
Embodiments of the present application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the application. The step numbers in the following embodiments are set for convenience of illustration only, and the order between the steps is not limited in any way, and the execution order of the steps in the embodiments may be adaptively adjusted according to the understanding of those skilled in the art.
In the description of the present application, the plurality means two or more, and if the description is made to the first and second for the purpose of distinguishing technical features, it should not be construed as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the precedence of the indicated technical features. Furthermore, unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art.
Referring to fig. 1, an embodiment of the present application provides a multi-board FPGA upgrade method based on ATE equipment, which specifically includes the following steps:
s101, acquiring a first secret key through a control board, verifying the first secret key, and opening FLASH write-in authorities of corresponding FPGAs of a plurality of function boards when verification is passed;
the control board communicates with the plurality of function boards through the data bus at the same time, so that the function boards update firmware at the same time.
Specifically, the embodiment of the application uses a data bus to carry out communication connection, a plurality of function boards with identical functions can burn the same firmware at the same time, and the control board can control and enable the function boards through one-to-one board selection signals. The PC upper computer is communicated with the control board through a communication link, and the control board controls the multi-block functional daughter card at one time in a data bus mode. When updating the FPGA, the upper computer writes the secret key, the function board verifies the written secret key, and the verification enables the FLASH through the opening of the FPGA later. The upper computer can send the encrypted firmware data to the control board, the control board transmits the data to the function board, the function board decrypts and verifies the data, and the data can be written into the FLASH after verification is successful.
Further as an optional implementation manner, the multi-board FPGA upgrade method further includes the following steps:
and S100, responding to a first operation instruction of a user, generating a corresponding board selection signal, and starting the FPGA upgrade of the corresponding function board through the control board according to the board selection signal.
Specifically, the user can select any function board to write operation on the upper computer, and when the remote upgrading process is operated, the user can control all function boards to write files, and after the writing is finished, the CRC information of the file is read and written in the next block. Since the plurality of function boards use unified firmware, all boards can be updated simultaneously in a bus mode.
S102, judging whether firmware to be updated exists in FLASH of the FPGA according to the update flag bit.
Further as an optional implementation manner, the internal space of the FLASH of the FPGA includes an original code area, an update code area and a flag data storage area, the original code area is used for storing an original factory code of the FPGA, the update code area is used for storing firmware to be updated, and the flag data storage area is used for storing update flag bits and firmware version information of the function board.
Specifically, in the embodiment of the application, the internal space of the FLASH is divided into 3 main areas, namely an original code area, an update code area and a mark data storage area, wherein the original factory code stored in the original code area is always available, no authority is given to modify any operation, the update code area can be completely erased only when a burner is used for downloading firmware, the start, writing and reading of the mark data storage area can be carried out after key verification, and the area stores firmware version information, update mark bits, update times and other power-down non-loss information of the board card.
Further as an optional implementation manner, the step of judging whether the firmware to be updated exists in the FLASH of the FPGA according to the update flag bit specifically includes:
and reading an update flag bit from the flag data storage area, determining that firmware to be updated exists in the FLASH of the FPGA when the update flag bit is in a waiting update state, and determining that the firmware to be updated does not exist in the FLASH of the FPGA when the update flag bit is in an update completion state.
Specifically, in the embodiment of the present application, if the firmware to be updated is downloaded, the update flag is set to be in a state of waiting for update, the updated firmware is automatically reloaded after the next time the device is powered on, if both the version verification and the start verification pass, the update flag is set to be in a state of completion of update, and the next time the device firmware is updated, it is determined that the firmware to be updated does not exist and the firmware is downloaded.
The embodiment of the application determines whether the FLASH contains the downloaded firmware to be updated through the update flag bit, if so, the firmware can be selectively loaded, if the firmware downloaded by the FLASH cannot be read, the firmware is required to be downloaded from the update code area, and in addition, the file verification and the reload verification are carried out on the downloaded file when the firmware is downloaded.
S103, when the firmware to be updated does not exist in the FLASH of the FPGA, the control panel is used for obtaining the encrypted firmware data, the function panel is used for decrypting the encrypted firmware data to obtain the firmware to be updated, the firmware to be updated is further checked, if the check is successful, the update flag bit is written, and if the check is failed, the control panel is returned to obtain the encrypted firmware data.
Further, as an optional implementation manner, the step of obtaining the encrypted firmware data through the control board and decrypting the encrypted firmware data through the function board to obtain the firmware to be updated specifically includes:
s1031, acquiring encrypted firmware data from an upper computer through a control board, and sending the encrypted firmware data to a corresponding function board;
s1032, decrypting the encrypted firmware data through the function board to obtain the firmware to be updated, and writing the firmware to be updated into the updating code area.
Further as an optional implementation manner, the step of verifying the firmware to be updated specifically includes:
s1033, performing CRC on the firmware to be updated;
s1034, when the CRC fails, erasing the updated code area, and returning to acquire the encrypted firmware data through the control board;
s1035, when the CRC check is successful, enabling firmware reload, and carrying out reload check, if the reload check is successful, setting the update mark position to be in a state of waiting for update, and if the reload check is failed, returning to acquire encrypted firmware data through the control board.
Specifically, the embodiment of the application uses a mode of downloading a small data volume for a plurality of times when downloading the firmware file; the FPGA performs CRC (cyclic redundancy check) on the written data, reads the check condition of each board card after the downloading of a single data packet is finished, and rewrites the updated code area after erasing if the check condition fails, and prints error information of 'file downloading check failure'; if the download verification is successful, the firmware is enabled to be reloaded, the reload verification is successful, the update mark position can be set to be in a state of waiting for update, the next time the firmware is powered on and automatically reloaded into the updated firmware, if the reload fails, the error information of 'file reload verification failure' can be printed, and whether the download operation is carried out again is prompted.
And S104, when the firmware to be updated exists in the FLASH of the FPGA, starting an updating program to load the firmware to be updated, reading a first firmware version number of the firmware to be updated, and further carrying out version verification on the firmware to be updated according to the first firmware version number.
Further, as an optional implementation manner, the step of reading the first firmware version number of the firmware to be updated and further performing version verification on the firmware to be updated according to the first firmware version number specifically includes:
s1041, reading firmware version information from the mark data storage area, and determining a first firmware version number according to the firmware version information;
s1042, obtaining a target version number, and determining whether the firmware to be updated is the target upgrade firmware according to the target version number and the first firmware version number;
s1043, checking whether the startup initialization state is normal when the firmware to be updated is determined to be the target updated firmware, if so, setting the update flag position as the update completion state, ending the FPGA update of the function board, and if not, jumping to acquire the encrypted firmware data through the control board.
Specifically, after the system is powered on successfully, a special key is input to check the firmware update condition, and if the key is checked to pass and an update flag bit waiting for an update state is detected, the system can start an update program to start loading new firmware; after the new firmware is loaded, judging whether the loaded new firmware is the target firmware or not by reading the firmware version; if the verification of the new version number is passed, the verification of the initialization state is started, whether the startup initialization state is normal or not is checked, whether the system can work normally or not is checked, if not, a version disagreement warning is given, and the writing of updated firmware is started to be enabled again.
The customized upper computer is an important guarantee for ensuring that ATE chip test equipment can safely and quickly finish remote upgrade; when the image file of the new firmware is downloaded, the upper computer can enable the firmware to be reloaded, immediately load the new code area and judge the version number of the loaded new firmware, so that the loading test can be carried out before the writing of the update flag bit to verify the correctness of the firmware, and the method is the most powerful guarantee of system safety.
The embodiment of the application performs space planning on FLASH, divides three functional areas, logically avoids any read-write operation on an original code area, and is used for ensuring that any error condition of a system in operation can reset and restore factory firmware and start a new round of upgrading operation; key verification is required as enabling for the operation of updating the code region; the writing of the update flag bit must pass version verification and start verification, that is, the updated flag bit can be written if and only if the firmware of the loading area passes the start verification of the upper computer and after the version verification is successful after the start. After updating, the system is powered on again, and the FPGA selects the firmware to be started according to key verification; the system can be directly warned when the firmware is in error or the firmware version verification fails after the firmware is started, and prompts the administrator to process.
The embodiment of the application is suitable for the XT2100Lite, the XT2100Plus and the XT2100Stnd ATE test equipment.
When the recorder is used for recording normally, the recording time of 1 FPGA is about 2.5 minutes, and when the system is provided with 2 FPGAs for each of 8 boards, the recorder is used for recording once, the time for recording is 2.5 times 2 times 8, so that all boards can be recorded in 40 minutes, in addition, the operation of plugging and unplugging the recorder for many times is required, and the actual time is far longer than 40 minutes. The time for upgrading one board card by adopting the embodiment of the application is 8 minutes, because the board card is upgraded simultaneously in parallel, the whole machine is upgraded for 8 minutes, the efficiency is far higher than that of the conventional downloader, the machine disassembly operation is not needed in the upgrading process, and a plurality of machines can be updated simultaneously by one person.
The method steps of the embodiments of the present application are described above. It can be appreciated that in the embodiment of the application, the communication connection between the control board and the plurality of functional boards is established by using the parallel bus, so that the plurality of functional boards can be simultaneously upgraded, and the upgrading efficiency of the FPGA of the ATE equipment is improved; by using a CRC file check and reload check double check mechanism, the lossless writing of the firmware file before starting and the smooth starting and working of the written firmware file are ensured, and the safety and reliability of the FPGA upgrading of ATE equipment are improved; after verification by the secret key, the FLASH write-in authority is opened, so that the security of updating the FPGA of the ATE equipment is further improved.
Referring to fig. 2, an embodiment of the present application provides a multi-board FPGA upgrade system based on ATE equipment, including:
the key verification module is used for obtaining a first key through the control board, verifying the first key, and opening FLASH write-in authorities of the corresponding FPGAs of the plurality of function boards when the verification is passed;
the flag bit judging module is used for judging whether firmware to be updated exists in FLASH of the FPGA according to the update flag bit;
the firmware verification module is used for obtaining the encrypted firmware data through the control board when the firmware to be updated does not exist in the FLASH of the FPGA, decrypting the encrypted firmware data through the function board to obtain the firmware to be updated, further verifying the firmware to be updated, writing in an update flag bit if verification is successful, and returning to obtain the encrypted firmware data through the control board if verification is failed;
the version verification module is used for starting an updating program to load the firmware to be updated when the firmware to be updated exists in the FLASH of the FPGA, reading a first firmware version number of the firmware to be updated, and further carrying out version verification on the firmware to be updated according to the first firmware version number;
the control board communicates with the plurality of function boards through the data bus at the same time, so that the function boards update firmware at the same time.
The content in the method embodiment is applicable to the system embodiment, the functions specifically realized by the system embodiment are the same as those of the method embodiment, and the achieved beneficial effects are the same as those of the method embodiment.
Referring to fig. 3, an embodiment of the present application provides a multi-board FPGA upgrade apparatus based on ATE equipment, including:
at least one processor;
at least one memory for storing at least one program;
when the at least one program is executed by the at least one processor, the at least one processor is caused to implement the multi-board FPGA upgrade method based on the ATE device.
The content in the method embodiment is applicable to the embodiment of the device, and the functions specifically realized by the embodiment of the device are the same as those of the method embodiment, and the obtained beneficial effects are the same as those of the method embodiment.
The embodiment of the application also provides a computer readable storage medium, wherein a program executable by a processor is stored, and the program executable by the processor is used for executing the multi-board FPGA upgrading method based on the ATE equipment when being executed by the processor.
The computer readable storage medium of the embodiment of the application can execute the multi-board FPGA upgrading method based on the ATE equipment, can execute the implementation steps of any combination of the embodiment of the method, and has the corresponding functions and beneficial effects of the method.
Embodiments of the present application also disclose a computer program product or computer program comprising computer instructions stored in a computer readable storage medium. The computer instructions may be read from a computer-readable storage medium by a processor of a computer device, and executed by the processor, to cause the computer device to perform the method shown in fig. 1.
In some alternative embodiments, the functions/acts noted in the block diagrams may occur out of the order noted in the operational illustrations. For example, two blocks shown in succession may in fact be executed substantially concurrently or the blocks may sometimes be executed in the reverse order, depending upon the functionality/acts involved. Furthermore, the embodiments presented and described in the flowcharts of the present application are provided by way of example in order to provide a more thorough understanding of the technology. The disclosed methods are not limited to the operations and logic flows presented herein. Alternative embodiments are contemplated in which the order of various operations is changed, and in which sub-operations described as part of a larger operation are performed independently.
Furthermore, while the present application has been described in the context of functional modules, it should be appreciated that, unless otherwise indicated, one or more of the functions and/or features described above may be integrated in a single physical device and/or software module or one or more of the functions and/or features may be implemented in separate physical devices or software modules. It will also be appreciated that a detailed discussion of the actual implementation of each module is not necessary to an understanding of the present application. Rather, the actual implementation of the various functional modules in the apparatus disclosed herein will be apparent to those skilled in the art from consideration of their attributes, functions and internal relationships. Accordingly, one of ordinary skill in the art can implement the application as set forth in the claims without undue experimentation. It is also to be understood that the specific concepts disclosed are merely illustrative and are not intended to be limiting upon the scope of the application, which is to be defined in the appended claims and their full scope of equivalents.
The above functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on this understanding, the technical solution of the present application may be embodied in essence or a part contributing to the prior art or a part of the technical solution in the form of a software product stored in a storage medium, including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the above-described method of the various embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
Logic and/or steps represented in the flowcharts or otherwise described herein, e.g., a ordered listing of executable instructions for implementing logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device.
More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium upon which the program described above is printed, as the program described above may be electronically captured, via, for instance, optical scanning of the paper or other medium, then compiled, interpreted, or otherwise processed in a suitable manner, if necessary, and then stored in a computer memory.
It is to be understood that portions of the present application may be implemented in hardware, software, firmware, or a combination thereof. In the above-described embodiments, the various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, may be implemented using any one or combination of the following techniques, as is well known in the art: discrete logic circuits having logic gates for implementing logic functions on data signals, application specific integrated circuits having suitable combinational logic gates, programmable Gate Arrays (PGAs), field Programmable Gate Arrays (FPGAs), and the like.
In the foregoing description of the present specification, reference has been made to the terms "one embodiment/example", "another embodiment/example", "certain embodiments/examples", and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
While embodiments of the present application have been shown and described, it will be understood by those of ordinary skill in the art that: many changes, modifications, substitutions and variations may be made to the embodiments without departing from the spirit and principles of the application, the scope of which is defined by the claims and their equivalents.
While the preferred embodiment of the present application has been described in detail, the present application is not limited to the above embodiments, and various equivalent modifications and substitutions can be made by those skilled in the art without departing from the spirit of the present application, and these equivalent modifications and substitutions are intended to be included in the scope of the present application as defined in the appended claims.

Claims (10)

1. A multi-board FPGA upgrading method based on ATE equipment is characterized by comprising the following steps:
acquiring a first secret key through a control board, verifying the first secret key, and opening FLASH write-in authorities of the corresponding FPGAs of a plurality of function boards when verification is passed;
judging whether firmware to be updated exists in FLASH of the FPGA according to the update flag bit;
when the firmware to be updated does not exist in the FLASH of the FPGA, acquiring encrypted firmware data through the control board, decrypting the encrypted firmware data through the function board to obtain the firmware to be updated, further checking the firmware to be updated, writing the update flag bit if the checking is successful, and returning to acquire the encrypted firmware data through the control board if the checking is failed;
when firmware to be updated exists in FLASH of the FPGA, an updating program is started to load the firmware to be updated, a first firmware version number of the firmware to be updated is read, and further version verification is carried out on the firmware to be updated according to the first firmware version number;
the control board communicates with a plurality of function boards through a data bus at the same time, so that each function board carries out firmware update at the same time.
2. The multi-board FPGA upgrade method based on ATE equipment of claim 1, further comprising the steps of:
and responding to a first operation instruction of a user, generating a corresponding board selection signal, and starting the corresponding FPGA upgrading of the function board through the control board according to the board selection signal.
3. The method for upgrading the multi-board-card FPGA based on the ATE equipment according to claim 1, wherein an internal space of a FLASH of the FPGA comprises an original code area, an update code area and a flag data storage area, wherein the original code area is used for storing original factory codes of the FPGA, the update code area is used for storing the firmware to be updated, and the flag data storage area is used for storing the update flag bit and firmware version information of the function board.
4. The method for upgrading a multi-board FPGA of an ATE-based device according to claim 3, wherein the step of obtaining encrypted firmware data through the control board and decrypting the encrypted firmware data through the function board to obtain the firmware to be updated specifically comprises:
the control board acquires the encrypted firmware data from the upper computer and sends the encrypted firmware data to the corresponding function board;
and decrypting the encrypted firmware data through the function board to obtain the firmware to be updated, and writing the firmware to be updated into the updating code area.
5. The method for upgrading a multi-board FPGA of an ATE-based device according to claim 3, wherein the step of verifying the firmware to be updated comprises:
performing CRC on the firmware to be updated;
when the CRC check fails, the updating code area is erased, and the control board is returned to acquire the encrypted firmware data;
and when the CRC check is successful, enabling the firmware to be reloaded, carrying out reloading check, if the reloading check is successful, setting the update mark position to be in a state waiting for update, and if the reloading check is failed, returning to acquire the encrypted firmware data through the control board.
6. The method for upgrading a multi-board FPGA of an ATE-based device according to claim 3, wherein the step of reading a first firmware version number of the firmware to be updated and further performing version verification on the firmware to be updated according to the first firmware version number specifically comprises:
reading the firmware version information from the mark data storage area, and determining the first firmware version number according to the firmware version information;
acquiring a target version number, and determining whether the firmware to be updated is a target updated firmware according to the target version number and the first firmware version number;
and when the firmware to be updated is determined to be the target updated firmware, checking whether the startup initialization state is normal, if so, taking the update mark position as an update completion state, ending the FPGA update of the function board, and if not, jumping to acquire encrypted firmware data through the control board.
7. The method for upgrading a multi-board FPGA based on an ATE device according to any one of claims 3 to 6, wherein the step of determining whether firmware to be updated exists in FLASH of the FPGA according to an update flag bit specifically includes:
reading the update flag bit from the flag data storage area, determining that firmware to be updated exists in the FLASH of the FPGA when the update flag bit is in a state waiting for update, and determining that the firmware to be updated does not exist in the FLASH of the FPGA when the update flag bit is in a state of completion of update.
8. A multi-board FPGA upgrading system based on ATE equipment is characterized by comprising:
the key verification module is used for obtaining a first key through the control board, verifying the first key, and opening FLASH write-in authorities of the corresponding FPGAs of the plurality of function boards when the verification is passed;
the flag bit judging module is used for judging whether firmware to be updated exists in FLASH of the FPGA according to the update flag bit;
the firmware verification module is used for obtaining encrypted firmware data through the control board when no firmware to be updated exists in the FLASH of the FPGA, decrypting the encrypted firmware data through the function board to obtain the firmware to be updated, further verifying the firmware to be updated, writing the update flag bit if verification is successful, and returning to obtain the encrypted firmware data through the control board if verification fails;
the version verification module is used for starting an updating program to load the firmware to be updated when the firmware to be updated exists in the FLASH of the FPGA, reading a first firmware version number of the firmware to be updated, and further carrying out version verification on the firmware to be updated according to the first firmware version number;
the control board communicates with a plurality of function boards through a data bus at the same time, so that each function board carries out firmware update at the same time.
9. A multi-board FPGA upgrading device based on ATE equipment is characterized by comprising:
at least one processor;
at least one memory for storing at least one program;
the at least one program, when executed by the at least one processor, causes the at least one processor to implement a multi-board FPGA upgrade method based on an ATE device as claimed in any of claims 1 to 7.
10. A computer readable storage medium, in which a processor executable program is stored, which when executed by a processor is adapted to perform a multi-board FPGA upgrade method based on ATE equipment as claimed in any of claims 1 to 7.
CN202310424407.6A 2023-04-19 2023-04-19 Multi-board FPGA upgrading method, system and storage medium based on ATE equipment Pending CN116578324A (en)

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CN202310424407.6A CN116578324A (en) 2023-04-19 2023-04-19 Multi-board FPGA upgrading method, system and storage medium based on ATE equipment

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CN202310424407.6A CN116578324A (en) 2023-04-19 2023-04-19 Multi-board FPGA upgrading method, system and storage medium based on ATE equipment

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CN116578324A true CN116578324A (en) 2023-08-11

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