CN116564852A - Jig for sintering interconnection and patch between semiconductor devices and method for interconnection and patch - Google Patents
Jig for sintering interconnection and patch between semiconductor devices and method for interconnection and patch Download PDFInfo
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- CN116564852A CN116564852A CN202310504349.8A CN202310504349A CN116564852A CN 116564852 A CN116564852 A CN 116564852A CN 202310504349 A CN202310504349 A CN 202310504349A CN 116564852 A CN116564852 A CN 116564852A
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- jig
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- device limiting
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- 238000005245 sintering Methods 0.000 title claims abstract description 139
- 239000004065 semiconductor Substances 0.000 title claims abstract description 85
- 238000000034 method Methods 0.000 title claims abstract description 83
- 230000000670 limiting effect Effects 0.000 claims abstract description 190
- 239000000758 substrate Substances 0.000 claims abstract description 100
- 230000008569 process Effects 0.000 claims abstract description 38
- 230000001681 protective effect Effects 0.000 claims description 23
- 230000000694 effects Effects 0.000 abstract description 15
- 239000000306 component Substances 0.000 description 33
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 19
- 229910052802 copper Inorganic materials 0.000 description 19
- 239000010949 copper Substances 0.000 description 19
- 239000000463 material Substances 0.000 description 15
- 229910000679 solder Inorganic materials 0.000 description 11
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 7
- 229910052709 silver Inorganic materials 0.000 description 6
- 239000004332 silver Substances 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 229910000831 Steel Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000007650 screen-printing Methods 0.000 description 4
- 238000001179 sorption measurement Methods 0.000 description 4
- 239000010959 steel Substances 0.000 description 4
- 230000009471 action Effects 0.000 description 3
- 238000006073 displacement reaction Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 238000001035 drying Methods 0.000 description 2
- 238000009791 electrochemical migration reaction Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000002427 irreversible effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 238000005086 pumping Methods 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical group [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000010923 batch production Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000010924 continuous production Methods 0.000 description 1
- 239000008358 core component Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000009776 industrial production Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67121—Apparatus for making assemblies not otherwise provided for, e.g. package constructions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6838—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping with gripping and holding devices using a vacuum; Bernoulli devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
- H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Abstract
The invention provides a jig for sintering interconnection and patch between semiconductor devices and a method for interconnecting and patch, wherein the jig comprises the following components: the first jig is provided with at least one first device limiting groove for accommodating the first semiconductor device; the second jig is provided with at least one second device limiting groove suitable for accommodating a second semiconductor device; the alignment component can fix the relative position of the first jig and the second jig in the horizontal direction; the first jig and the second jig are provided with fixing parts for fixing the semiconductor device in the first device limiting groove or the second device limiting groove. The fixture can fix the position of the chip above the sintering layer on the substrate, and then the fixture is integrally transferred to other working procedures with the sample, and the chip cannot shift on the substrate due to the fixing effect of the fixture in the transferring process, so that the chip connection dislocation cannot be generated.
Description
Technical Field
The invention belongs to the technical field of chip interconnection and chip mounting, and particularly relates to a jig for sintering interconnection and chip mounting between semiconductor devices and an interconnection and chip mounting method.
Background
The power device is a core component in the technologies of new energy automobiles, 5G base stations and the like, and along with the popularization of the new energy automobiles, the construction of the 5G base stations increases the demands for the power device. Conventional silicon-based semiconductor devices are unable to meet the more stringent operating conditions and higher performance requirements. Wide band gap semiconductor devices, such as silicon carbide, still have good conversion characteristics and operating capabilities at high temperatures of 350 c and, therefore, have significant advantages under high temperature high power or high heat dissipation application conditions, known as the most important materials for third generation semiconductors.
The packaging technology is a key link in the production process of the power device, the chip packaging is one of the most commonly used interconnection technologies, the chip is required to be connected with the substrate by using high-temperature solder in the chip packaging technology, and in the traditional technology, the commonly used solder is tin-based lead-free solder, namely solder paste, but the solder paste has the problem of remelting, and cannot meet the working requirement of more than 250 ℃. The metal sintering connection is a connection method based on sintering theory, wherein atoms on the surface of a material are mutually diffused through high temperature, so that compact crystals are formed. Nano silver and nano copper sintering technology is the most representative technology at present. Among them, the silver particle sintered material has problems of higher cost, poor resistance to electrochemical migration and poor thermal reliability. Copper particles have good electrical and thermal conductivity and lower cost than silver, and more importantly copper has better resistance to electrochemical migration, so that copper is the most potential material.
In an industrial process, the process prior to sintering interconnection of the chip and the substrate includes: the wet paste-shaped sintering layer material is coated on a substrate through steel screen printing or other processes, then is dried, chips are picked up and placed on the dried sintering layer material through a mechanical arm sucker, then the sandwich structure of the whole substrate-sintering layer-chip is transferred to sintering equipment for pressure-assisted or non-pressure-assisted sintering, or a film is covered above the chip to protect the chip, and the structure of the substrate-sintering layer-chip-film is transferred to the sintering equipment for sintering. For the chip patch layer material using the welding process traditionally, the state of the solder is wet paste, and the chip is placed on the solder paste to generate the pre-bonding effect of the solder paste on the chip, so that the pre-connection is generated between the chip and the solder paste; in the case of sintered silver processes, the silver material, due to its softer texture, may also create a pre-connection that may make the sandwich structure of substrate-sintered layer-chip less prone to chip shifting on the substrate when transferred to sintering equipment or other processes. In the case of the sintered copper process, the copper material cannot be pre-joined between the copper sintered layer and the chip by heating (to 130 ℃) or pressurizing (to 10 kg) due to its hard texture, which causes a great problem for industrial continuous production. When industrial batch production, need place a large amount of samples in the tool, one step of operation produces a large amount of samples simultaneously, and each operation link of automated production all goes on based on the accurate sample of alignment location, if pick up when placing the process on chip and the base plate sintered layer can't form the pre-connection, then easily produce the chip dislocation in the in-process that shifts to the sintering process, more serious, to the condition of covering the protection film buffer layer on the chip, the electrostatic adsorption effect of film is more liable to cause the dislocation of chip, the condition of above-mentioned chip dislocation can cause irreversible connection of inaccurate location at the sintering process, lead to follow-up wire bonding process "wire bonding" inaccurate, make the product percent of pass reduce.
Therefore, the copper sintered layer cannot be pre-connected with the chip, so that the problem of chip displacement in the transfer process is solved, the application of the chip sintering copper interconnection method is limited, and the problem is an urgent need to be solved in the current industrial production.
Disclosure of Invention
The invention provides a jig for sintering interconnection and chip bonding between semiconductor devices and a method for interconnecting and bonding, which aims to solve the technical problem that a chip is easy to shift and chip dislocation when a sandwich structure of a chip-sintering layer-substrate is transferred in different working procedures because a copper sintering layer and the chip cannot be pre-connected in a sintering copper interconnection and chip bonding process.
In order to solve the above-described problems, a first aspect of the present invention provides a jig for sintering interconnection and bonding between semiconductor devices, comprising:
the first jig is provided with at least one first device limiting groove, and the first device limiting groove is suitable for accommodating a first semiconductor device and can limit the first semiconductor device to move in the horizontal direction;
The second jig is provided with at least one second device limiting groove, and the second device limiting groove is suitable for accommodating a second semiconductor device and can limit the movement of the second semiconductor device in the horizontal direction;
the alignment component can fix the relative position of the first jig and the second jig in the horizontal direction;
the first fixture is provided with a first fixing part, and the first fixing part is used for fixing the first semiconductor device in the first device limiting groove; and/or
The second fixture is provided with a second fixing part, and the second fixing part is used for fixing the second semiconductor device in the second device limiting groove.
Preferably, the first fixing component is a first vacuum through hole, the first vacuum through hole is communicated with the first device limiting groove, and the first vacuum through hole is suitable for being connected with a vacuumizing assembly.
Preferably, the second fixing component is a second vacuum through hole, the second vacuum through hole is communicated with the second device limiting groove, and the second vacuum through hole is suitable for being connected with a vacuumizing assembly.
Preferably, the second fixing component is a buckle, and the buckle is arranged at the edge of the second device limiting groove.
Preferably, the outer edge of the first jig or the second jig is further provided with a frame, and the height of the frame is not greater than the distance between the first jig and the second jig when the film, the chip, the sintered layer and the substrate are laminated and laminated.
Preferably, the alignment component comprises a positioning column arranged on the first jig and a positioning hole arranged at the opposite position on the second jig; or (b)
The alignment part comprises a positioning column arranged on the second jig and a positioning hole arranged at the relative position of the first jig.
A second aspect of the present invention provides a method for sintering interconnection and bonding of chips, which is completed by using the jig for sintering interconnection and bonding between semiconductor devices, wherein at least a first fixture is provided with a first fixing member, the method comprising the steps of:
s1, placing a substrate provided with a sintering layer in the second device limiting groove of the second jig;
s2, arranging a chip in the first device limiting groove of the first jig, fixing the chip in the first device limiting groove through the first fixing part, and enabling the opening of the first device limiting groove of the first jig to be downward;
S3, placing the first jig above the second jig, enabling the chip to be located at a preset position of the sintering layer, and fixing the relative positions of the first jig and the second jig in the horizontal direction through the alignment part;
s4, transferring the jig for sintering interconnection and surface mounting between the semiconductor devices to sintering equipment to perform a sintering process.
Preferably, the first fixing component is a first vacuum through hole, the first vacuum through hole is communicated with the first device limiting groove, and the vacuum component applies negative pressure to the chip through the first vacuum through hole to fix the chip in the first device limiting groove.
A third aspect of the present invention provides a method for sintering interconnection and bonding of chips, which is completed by using the jig for sintering interconnection and bonding of semiconductor devices, wherein at least a second fixture is provided with a second fixing member, the method comprising the steps of:
s1, placing a chip in the first device limiting groove of the first jig;
s2, arranging a substrate provided with a sintered layer in the second device limiting groove of the second jig, and fixing the substrate in the second device limiting groove through the second fixing part, wherein the opening of the second device limiting groove of the second jig is downward;
S3, placing the second jig above the first jig, enabling the chip to be located at a preset position of the sintering layer, and fixing the relative positions of the first jig and the second jig in the horizontal direction through the alignment part;
s4, transferring the jig for sintering interconnection and surface mounting between the semiconductor devices to sintering equipment to perform a sintering process.
Preferably, the method further comprises the step of arranging a protective film between the first device limiting groove of the first jig and the chip; the protective film is used for protecting the chip, and micropores through which gas can pass are formed in the protective film.
Compared with the prior art, the invention has the following beneficial effects:
the jig for sintering interconnection and surface mounting between semiconductor devices is provided with the first device limiting groove which can fix the chip and the second device limiting groove which can fix the substrate, so that the position of the chip above a sintering layer on the substrate is fixed, and then the jig is integrally transferred to other working procedures, and the chip cannot shift on the substrate due to the fixing effect of the jig in the transfer process, so that the condition of chip connection dislocation cannot be generated. The jig for sintering interconnection and patch between semiconductor devices not only can be used for the process of sintering interconnection and patch between a chip and a substrate, but also can be used for the process of sintering interconnection or patch between two semiconductor devices of other types.
According to the method for sintering, interconnecting and attaching the chip, when the sample to be sintered is prepared, the position of the chip above the sintering layer on the substrate is fixed through the jig, and then the jig with the sample is integrally transferred to other working procedures, such as the sintering working procedure, the chip cannot shift on the substrate due to the fixing effect of the jig in the transferring process, and the chip connection dislocation cannot occur.
Drawings
Fig. 1 is a schematic view of the jig for sintering interconnection and bonding between semiconductor devices according to embodiment 1 of the present invention in use;
fig. 2 is a schematic structural diagram of a jig for sintering interconnection and bonding between semiconductor devices according to embodiment 2 of the present invention in use;
fig. 3 is a schematic structural diagram of the jig for sintering interconnection and bonding between semiconductor devices according to embodiment 2 of the present invention after the first jig and the second jig are covered in use;
fig. 4 is a schematic structural diagram of a jig for sintering interconnection and bonding between semiconductor devices according to embodiment 3 of the present invention in use;
fig. 5 is a schematic structural diagram of the jig for sintering interconnection and bonding between semiconductor devices according to embodiment 3 of the present invention after the first jig and the second jig are covered in use;
Fig. 6 is a schematic view of the jig for sintering interconnection and bonding between semiconductor devices according to embodiment 4 of the present invention in use.
Wherein: 1-a first jig; 2-a first device limiting groove; 3-chip; 4-a second jig; 5-a second device limiting groove; 6-a substrate; 7-vacuum through holes; 8-positioning holes; 9-a protective film; 10-sintering layers; 11-vacuum through holes; 12-frame; 13-a buckle; 14-positioning columns.
Detailed Description
The technical solutions of the present invention will be clearly and completely described in conjunction with the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The preparation process of the sample to be interconnected for sintering and interconnecting the chip and the substrate comprises the following steps: the wet paste-shaped sintered layer material is coated on a substrate through steel screen printing, then is dried, then the chip is picked up and placed on the dried sintered layer material, and then the sandwich structure of the whole substrate-sintered layer-chip is transferred into sintering equipment for sintering. In the interconnection process using copper as the sintering material, heating or pressurizing the copper cannot generate a pre-connection effect between the copper sintering layer and the chip due to the harder texture of the copper, the chip is easily misplaced when the whole structure is transferred to the sintering process, and in the case of covering a buffer layer such as a protective film on the chip, the film is easily subjected to electrostatic adsorption effect, the chip is easily misplaced, and irreversible connection with inaccurate positioning is caused.
To solve the above problems, a first aspect of an embodiment of the present invention provides a jig for sintering interconnection and bonding between semiconductor devices, including:
the first jig is provided with at least one first device limiting groove, and the first device limiting groove is suitable for accommodating a first semiconductor device and can limit the first semiconductor device to move in the horizontal direction;
the second jig is provided with at least one second device limiting groove, and the second device limiting groove is suitable for accommodating a second semiconductor device and can limit the movement of the second semiconductor device in the horizontal direction;
the alignment component can fix the relative position of the first jig and the second jig in the horizontal direction;
the first fixture is provided with a first fixing part, and the first fixing part is used for fixing the first semiconductor device in the first device limiting groove; and/or
The second fixture is provided with a second fixing part, and the second fixing part is used for fixing the second semiconductor device in the second device limiting groove.
The jig for sintering interconnection and surface mounting between semiconductor devices can be used for independently arranging the first fixing component on the first jig, independently arranging the second fixing component on the second jig, and arranging the first fixing component on the first jig and simultaneously arranging the second fixing component on the second jig.
When the first fixing part is separately arranged on the first jig, the process of preparing the sample to be interconnected is as follows: the second device limiting groove of the second jig is opened upwards, the substrate is placed in the second device limiting groove, the sintering layer is arranged on the substrate, the first device limiting groove of the first jig is opened downwards, the chip is arranged in the first device limiting groove, the chip is fixed in the first device limiting groove through the first fixing component, or after the protective film is arranged above the chip, the chip is arranged in the first device limiting groove, then the first jig is moved to the position above the second jig, the chip is located at a preset position above the sintering layer, the first jig is lowered or the second jig is raised, the first jig is arranged on the second jig, the relative position of the first jig and the second jig in the horizontal direction is fixed through the alignment component, and therefore, when the jig and a sample to be interconnected are transferred to other processes (such as sintering processes), the relative position of the chip and the substrate in the horizontal direction is fixed due to the limiting effect of the first device limiting groove and the second device limiting groove, and no displacement is generated.
When the second fixing part is separately arranged on the second jig, the process of preparing the sample to be interconnected is as follows: the opening of a first device limiting groove of the first jig is upward, a chip is placed in the first device limiting groove upside down (namely the upper surface of the chip is downward), or after a protective film is arranged below the upside-down chip, the chip and the protective film are arranged in the first device limiting groove; the second device limiting groove of the second jig is opened downwards, the substrate provided with the sintering layer is arranged in the second device limiting groove upside down (namely the upper surface of the substrate faces downwards), the substrate is fixed in the second device limiting groove through the second fixing part, then the second jig is moved to the upper part of the first jig, the chip is located at the preset position of the sintering layer, the second jig is lowered or the first jig is lifted, the second jig is arranged on the first jig, the relative positions of the first jig and the second jig in the horizontal direction are fixed through the alignment part, and therefore, when the jig and a sample to be interconnected are transferred to other processes (such as sintering processes), the relative positions of the chip and the substrate in the horizontal direction are fixed due to the limiting effect of the first device limiting groove and the second device limiting groove, and no displacement is generated.
The jig for sintering interconnection and patch between semiconductor devices, provided by the embodiment of the invention, not only can be used for sintering interconnection and patch between a chip and a substrate, but also can be used for sintering interconnection or patch between two semiconductor devices of other types, such as sintering of a metal film and the upper surface of the chip, sintering of a wire bonding buffer metal layer and the upper surface of the chip, and the like.
The jig for sintering interconnection and patch between semiconductor devices can be used for fixing the relative positions of chips and substrates in the horizontal direction under the condition that the chips and the substrates cannot form the sintering copper interconnection and patch with the pre-connection function; the method can also be used for the situation that solder paste, sintered silver and the like can form a pre-connection function between the chip and the substrate, so that the relative positions of the chip and the substrate are further stabilized, and the chip and the substrate are ensured not to shift.
In some embodiments, the first fixture is provided with the first fixing component, and the second fixture is provided with the second fixing component, that is, the substrate in the second fixture and the chip in the first fixture are fixed, so that the process of transferring the sample to be interconnected can be more stable, and the chip dislocation is further prevented.
In some embodiments, the specific shapes of the first jig and the second jig may be adjusted, and are not particularly limited, and may be, for example, a flat plate. The size of the device can be adjusted according to the number of samples to be placed in the jig. The materials of the first jig and the second jig are not particularly limited, as long as the material performance is stable and does not change under the condition of the sintering process.
In some embodiments, the number of the first device limiting grooves on the first jig and the number of the second device limiting grooves on the second jig can be set according to actual requirements, for example, 1, 2 and 3 chips are connected on one substrate, then 1 second device limiting groove can be arranged on the second jig, 1, 2 and 3 first device limiting grooves are arranged on the first jig, and as long as the number and the positions of the first device limiting grooves are consistent with those of the chips to be connected, the number and the positions of the second device limiting grooves are consistent with those of the substrates.
In some embodiments, the cross-sectional shape and size of the first device limiting groove are not particularly limited as long as it can limit the movement of the first semiconductor device in the horizontal direction. For example, the first device limiting groove may have a structure with a cross section completely identical to the cross section shape and size of the first semiconductor device, or may have a structure with a cross section connected to the cross section shape of the first semiconductor device, for example, may have a circular shape, an oval shape, a triangle shape, etc. circumscribed with the cross section of the first semiconductor device. As a preferred embodiment, the first device limiting groove has a structure with a cross section identical to the cross section of the first semiconductor device in shape and size.
In some embodiments, the cross-sectional shape and size of the second device-limiting groove are not particularly limited as long as it can limit the movement of the second semiconductor device in the horizontal direction. For example, the second device limiting groove may have a structure with a cross section identical to the cross section shape and size of the second semiconductor device, or may have a structure with a cross section connected to the cross section shape of the second semiconductor device, for example, a circular shape, an oval shape, a triangle shape, etc. circumscribed by the cross section of the second semiconductor device. As a preferred embodiment, the second device limiting groove has a structure with a cross section identical to the cross section of the second semiconductor device in shape and size.
In some embodiments, the heights of the first device limiting groove and the second device limiting groove are not particularly limited, but it is required that when the substrate provided with the sintered layer is placed in the second device limiting groove, the chip (or the chip and the chip protection layer, for example, the protection film) is placed in the first device limiting groove, and the first jig and the second jig are mutually covered, the first device limiting groove still has a limiting effect on the chip, and the second device limiting groove still has a limiting effect on the substrate, that is, the chip is still located in the first device limiting groove, but is not required to be located at the bottom of the first device limiting groove, and the substrate is still located in the second device limiting groove, but is not required to be located at the bottom of the second device limiting groove.
In some embodiments, the specific structure of the first fixing member is not limited as long as the first semiconductor device can be fixed in the first device limiting groove, and further, as long as the movement of the first semiconductor device in the vertical direction in the first device limiting groove can be limited. In order to prevent the chip from being damaged by the fixing component, the chip is fixed by adopting a negative pressure adsorption method, the first fixing component is a first vacuum through hole, the first vacuum through hole is communicated with the first device limiting groove, and the first vacuum through hole is suitable for being connected with a vacuumizing assembly. In the industrial automatic production process, the chip or the substrate or other semiconductor devices are usually adsorbed by utilizing the negative pressure effect of the mechanical arm sucker, so that the devices are picked up and placed, the vacuumizing component is the mechanical arm sucker directly, the negative pressure of the sucker is applied to the chip in the first device limiting groove through the first vacuum through hole, or when the chip protection layer is arranged above the chip, the chip protection layer is made of a material containing a large number of micropores, and the negative pressure of the sucker is applied to the chip in the first device limiting groove through the first vacuum through hole and the micropores of the chip protection layer, so that the chip is adsorbed and fixed in the first device limiting groove by the negative pressure, or the first jig is picked up at the same time. In addition, the vacuum-pumping assembly can be another vacuum-pumping device which is arranged independently, so long as negative pressure can be generated on the chip.
In some embodiments, the specific structure of the second fixing member is not limited as long as the second semiconductor device can be fixed in the second device limiting groove, and further, as long as the movement of the second semiconductor device in the vertical direction in the second device limiting groove can be limited.
In some embodiments, the substrate may be fixed by using a negative pressure adsorption method, and the second fixing component is a second vacuum through hole, where the second vacuum through hole is communicated with the second device limiting groove, and the second vacuum through hole is adapted to be connected with a vacuumizing assembly. The second vacuum through hole is used for applying negative pressure to the substrate in the second device limiting groove under the action of the negative pressure of the manipulator sucker, so that the substrate is adsorbed and fixed to the second device limiting groove by the negative pressure, or the second jig is picked up at the same time.
In some embodiments, the substrate may be further fixed by mechanical fixing, and the second fixing component is a buckle, where the buckle is disposed at an edge of the second device limiting groove. The base plate is fixed in the second device limiting groove through the buckle. Specifically, the buckle can be an inverted-L-shaped buckle with a longitudinal section, or an inverted-T-shaped buckle, and the number of the buckles can be 2, 3, 4 and the like.
The specific structure of the alignment member is not particularly limited as long as it can fix the relative positions of the first jig and the second jig in the horizontal direction.
In some embodiments, the alignment member may include a positioning hole and a positioning column that are matched, the positioning hole may be disposed on the first jig, the positioning column may be disposed at a corresponding position on the second jig, and the positioning hole may also be disposed on the second jig, and the positioning column may be disposed at a corresponding position on the first jig.
In some embodiments, the setting positions of the positioning hole and the positioning post are not limited, so long as the setting positions of the positioning hole and the positioning post correspond. The locating hole and the locating column can be arranged at the position of the jig close to the edge, and can also be arranged at the middle position of the jig. The quantity of locating hole, reference column can be 1, 2, 3 or a plurality of, and when quantity was 1, in order to prevent that first tool, second tool from taking the reference column to rotate as the center, reference column, locating hole can set up to the cross section and be triangle-shaped, quadrangle, pentagon etc. shape. When the number is more than 2, the locating columns are cylindrical.
In some embodiments, the alignment component may be a limiting plate disposed at an edge of the first fixture or the second fixture. Taking the limiting plate arranged on the first jig as an example, the limiting plate can be arranged at the edges of at least two sides of the first jig, after the sample to be interconnected is arranged between the first jig and the second jig and covered, the edge of the second jig is positioned at the inner side of the limiting plate and is limited by the limiting plate to move in the horizontal direction.
In some embodiments, to better prevent the chip or the substrate from sliding out of the jig, a frame is further provided at an outer edge of the first jig or the second jig.
In some embodiments, for the pressed sintering process, in order that the pressure applied by the pressure head of the sintering device can be transferred to the chip, the height of the frame is not greater than the distance between the first jig and the second jig when the film, the chip, the sintered layer, and the substrate lamination stack are disposed between the first jig and the second jig. The height of the frame refers to the distance between the upper surfaces of the jigs with the frame arranged at the top of the frame.
A second aspect of the embodiments of the present invention provides a method for sintering interconnection and bonding a chip, which is completed by using the jig for sintering interconnection and bonding a semiconductor device, wherein at least a first fixture is provided with a first fixing component, and the method includes the following steps:
s1, placing a substrate provided with a sintering layer in the second device limiting groove of the second jig;
s2, arranging a chip in the first device limiting groove of the first jig, fixing the chip in the first device limiting groove through the first fixing part, and enabling the opening of the first device limiting groove of the first jig to be downward;
S3, placing the first jig above the second jig, enabling the chip to be located at a preset position of the sintering layer, and fixing the relative positions of the first jig and the second jig in the horizontal direction through the alignment part;
s4, transferring the jig for sintering interconnection and surface mounting between the semiconductor devices to sintering equipment to perform a sintering process.
According to the chip sintering interconnection and chip mounting method, when the sample to be sintered is prepared, the position of the chip above the sintering layer on the substrate is fixed through the jig, and then the jig with the sample is integrally transferred to other working procedures, such as the sintering working procedure, and the chip cannot shift on the substrate due to the fixing effect of the jig in the transferring process, so that the chip connection dislocation cannot occur.
The chip sintering interconnection and chip mounting method can be used for the situation that the chip and the substrate cannot form the sintering copper interconnection and the chip mounting with the pre-connection function, and the positions of the chip and the substrate are fixed through the jig; the fixture can also be used for the situation that solder paste, sintered silver and the like can form a pre-connection function between the chip and the substrate, and the relative positions of the chip and the substrate are further stabilized by the fixture, so that the chip and the substrate are prevented from shifting.
In some embodiments, the first fixing member is a first vacuum through hole, the first vacuum through hole is communicated with the first device limiting groove, and the vacuum assembly applies negative pressure to the chip through the first vacuum through hole to fix the chip in the first device limiting groove. Because the automation equipment generally utilizes the negative pressure effect of the manipulator sucking disc to adsorb the chip or the substrate or other semiconductor devices, the picking up and placing of the devices are realized, in step S2, the chip is fixed in the first device limiting groove through the negative pressure applied by the manipulator sucking disc, and meanwhile, the sucking disc picks up the first jig.
In some embodiments, the second fixture is provided with a second fixing component at the same time, and in step S1, after the substrate provided with the sintered layer is placed in the second device limiting groove of the second fixture, the substrate is further fixed in the second device limiting groove by the second fixing component. The stability of the substrate fixed in the jig can be further improved.
In some embodiments, the second fixing member may be a second vacuum through hole, the second vacuum through hole being in communication with the second device limiting groove, and the vacuum assembly applying negative pressure to the substrate through the second vacuum through hole to fix the substrate in the second device limiting groove. The second fixing component can also be a buckle, and the buckle is arranged at the edge of the second device limiting groove and is used for fixing the substrate in a mechanical action mode.
In some embodiments, step S1 may specifically be that a substrate is placed in the second device limiting groove of the second jig, the back surface of the substrate faces the bottom of the second device limiting groove, and then a sintered layer is disposed on the substrate; step S1 may further include disposing the sintered layer on the substrate, and then disposing the substrate with the sintered layer in the second device limiting groove of the second jig.
In some embodiments, step S2 may specifically be that a chip is disposed in the first device limiting groove, a front surface of the chip faces to a bottom of the first device limiting groove, the chip is fixed in the first device limiting groove by the first fixing component, and an opening of the first device limiting groove of the first fixture is downward.
In some embodiments, the method further includes disposing a protective film between the first device-limiting groove of the first jig and the chip; the protective film is used for protecting the chip, and micropores through which gas can pass are formed in the protective film. Specifically, in step S2, the protective film is first disposed on the chip, and then the chip is disposed in the first device limiting groove of the first fixture.
A third aspect of the embodiments of the present invention provides a method for sintering interconnection and bonding a chip, which is completed by using the jig for sintering interconnection and bonding a semiconductor device, wherein at least a second fixture is provided with a second fixing component, and the method includes the following steps:
s1, placing a chip in the first device limiting groove of the first jig;
s2, arranging a substrate provided with a sintered layer in the second device limiting groove of the second jig, and fixing the substrate in the second device limiting groove through the second fixing part, wherein the opening of the second device limiting groove of the second jig is downward;
s3, placing the second jig above the first jig, enabling the chip to be located at a preset position of the sintering layer, and fixing the relative positions of the first jig and the second jig in the horizontal direction through the alignment part;
s4, transferring the jig for sintering interconnection and surface mounting between the semiconductor devices to sintering equipment to perform a sintering process.
According to the chip sintering interconnection and chip mounting method, when the sample to be sintered is prepared, the whole sample is inverted, the position of the chip on the sintering layer on the substrate is fixed through the jig, then the jig with the sample is integrally transferred to other working procedures, such as the sintering working procedure, and the chip connection dislocation cannot be generated due to the fixing effect of the jig in the transferring process.
In some embodiments, the second fixing member is a second vacuum through hole, the second vacuum through hole is communicated with the second device limiting groove, and the vacuum assembly applies negative pressure to the substrate through the second vacuum through hole to fix the substrate in the second device limiting groove. Because the automation equipment generally utilizes the negative pressure effect of the manipulator sucking disc to adsorb chips or substrates or other semiconductor devices, the picking and placing of the devices are realized, in step S2, the substrates are fixed in the second device limiting grooves through the negative pressure applied by the manipulator sucking disc, and meanwhile, the sucking disc picks up the second jig.
In some embodiments, the second fixing component may be a buckle, where the buckle is disposed at an edge of the second device limiting groove, and fixes the substrate by a mechanical action manner.
In some embodiments, the first fixture is provided with a first fixing component at the same time, and in step S1, after the chip is placed in the first device limiting groove of the first fixture, the chip is further fixed in the first device limiting groove by the first fixing component. The stability of the chip fixed in the jig can be further improved.
In some embodiments, the first fixing member may be a first vacuum through hole, the first vacuum through hole is in communication with the first device limiting groove, and the vacuum assembly applies negative pressure to the chip through the first vacuum through hole to fix the chip in the first device limiting groove.
In some embodiments, step S1 may specifically be that the chip is placed upside down in the first device limiting groove of the first fixture, that is, the front surface of the chip faces downward toward the bottom of the first device limiting groove, and the front surface of the chip faces toward the bottom of the first device limiting groove.
In some embodiments, step S2 may specifically be that the substrate provided with the sintered layer is inversely disposed in the second device limiting groove of the second fixture, and the substrate is fixed in the second device limiting groove by the second fixing component, where an opening of the second device limiting groove of the second fixture is downward, that is, a front surface of the substrate is downward, and a back surface of the substrate is toward a bottom of the second device limiting groove; step S2 may specifically further include placing the substrate in the second device limiting groove of the second jig, where the back surface of the substrate faces the bottom of the second device limiting groove, disposing a sintered layer on the substrate, and then fixing the substrate in the second device limiting groove by using the second fixing component, where the second device limiting groove of the second jig is opened downward.
In some embodiments, the method further includes disposing a protective film between the first device-limiting groove of the first jig and the chip; the protective film is used for protecting the chip, and micropores through which gas can pass are formed in the protective film. Specifically, in step S1, a protective film is first disposed on a chip, and then the chip is disposed in the first device limiting groove of the first fixture.
Example 1
As shown in fig. 1, the jig for sintering interconnection and bonding between semiconductor devices of the present embodiment includes a first jig 1 and a second jig 4, where the first jig and the second jig are flat. A plurality of first device limiting grooves 2 are formed in the first jig 1, the first device limiting grooves 2 are cuboid grooves with the cross section identical to the cross section of the chip in shape and size, the chip 3 can be accommodated, and the depth of the first device limiting grooves is smaller than the thickness of the chip; the second jig 4 is provided with a plurality of second device limiting grooves 5, the number of which is the same as that of the first device limiting grooves, the second device limiting grooves 5 are cuboid grooves, the cross section of each cuboid groove is the same as that of the base plate 6, the base plate 6 can be accommodated, and the depth of each second device limiting groove is smaller than the thickness of the base plate. The bottom of the first device limiting groove 2 on the first jig 1 is provided with a vacuum through hole 7 penetrating through the bottom wall of the first device limiting groove. Two opposite sides of the second jig are respectively provided with a positioning column 14, and corresponding parts of the first jig are respectively provided with a positioning hole 8.
The method for sintering interconnection and surface mounting of chips in the embodiment is completed by using the jig for sintering interconnection and surface mounting between semiconductor devices, and comprises the following steps:
S1, adsorbing and picking up a substrate by a mechanical arm sucker, placing the substrate in a second device limiting groove 5 of a second jig 4, enabling the back surface of the substrate 6 to face the bottom of the second device limiting groove, coating a copper sintered layer on the substrate by steel screen printing, and drying to form a sintered layer 10;
s2, opening a first device limiting groove 2 of a first jig 1 downwards, paving a protective film 9 on a chip 3, arranging a large number of micropores capable of allowing gas to pass through on the protective film 9, then arranging the chip 3 in the first device limiting groove 2 of the first jig 1, enabling the front surface of the chip 3 to face the bottom of the first device limiting groove 2, fixing the chip in the first device limiting groove by utilizing the negative pressure effect of a sucker of a mechanical arm, and picking up the first jig 1 by the sucker;
s3, moving the first jig 1 to the position above the second jig 4 through a mechanical arm, enabling the chip 3 to be located at the preset position of the sintered layer 10, enabling the mechanical arm to descend the first jig 1 and fall onto the second jig, enabling the positioning column to be inserted into the positioning hole, and positioning the first jig and the second jig;
s4, transferring the whole jig and the sample to be sintered to a sintering furnace through a mechanical arm, applying pressure to the jig through a pressure head, and performing a pressed sintering process.
Example 2
As shown in fig. 2 and 3, the jig for sintering interconnection and bonding between semiconductor devices of the present embodiment is based on embodiment 1, and the bottom of the second device limiting groove 5 on the second jig 4 is further provided with a vacuum through hole 11 penetrating through the second device limiting groove 5, the outer edge of the second jig 4 is further provided with a frame 12, and the frame 12 is smaller than the distance between the first jig and the second jig when the film, the chip, the sintered layer and the substrate are laminated between the first jig and the second jig, so that the pressure exerted by the pressure head of the sintering device can be transmitted to the chip when the pressure sintering is performed.
The method for sintering interconnection and bonding of chips in this embodiment is completed by using the jig for sintering interconnection and bonding between semiconductor devices, and in step S1, the substrate is finally adsorbed and fixed in the second device limiting groove by the negative pressure of the manipulator suction cup at the bottom of the second jig, thereby further fixing the substrate.
Example 3
As shown in fig. 4 and 5, the jig for sintering interconnection and bonding between semiconductor devices of the present embodiment has the same structure as that of embodiment 2.
The method for sintering interconnection and patch of the chip of the embodiment comprises the following steps:
S1, a first device limiting groove of a first jig is opened upwards, a protective film 9 is paved on a chip 3, a large number of micropores through which gas can pass are formed in the protective film 9, the chip is placed in the first device limiting groove of the first jig in an inverted mode, namely, the front face of the chip faces downwards and faces towards the bottom of the first device limiting groove, and the chip is adsorbed and fixed in the first device limiting groove under the negative pressure effect of a manipulator sucker at the bottom of the first jig, so that the chip is further fixed;
s2, coating a copper sintering layer on a substrate through steel screen printing, drying to form a sintering layer 10, opening a second device limiting groove of a second jig downwards, inversely arranging the substrate provided with the sintering layer in the second device limiting groove of the second jig, namely, arranging the front surface of the substrate downwards, arranging the back surface of the substrate towards the bottom of the second device limiting groove, fixing the substrate in the second device limiting groove by utilizing the negative pressure effect of a sucker of a mechanical arm, and picking up the second jig by the sucker;
s3, moving the second jig 4 to the position above the first jig 1 through a mechanical arm, enabling the chip 3 to be located at the preset position of the sintered layer 10, enabling the mechanical arm to descend the second jig 4 and fall onto the first jig, enabling the positioning column to be inserted into the positioning hole, and positioning the first jig and the second jig;
S4, transferring the whole jig and the sample to be sintered to a sintering furnace through a mechanical arm, applying pressure to the jig through a pressure head, and performing a pressed sintering process.
Example 4
As shown in fig. 6, the jig for sintering interconnection and bonding between semiconductor devices in this embodiment is the same as other structures of the jig in embodiment 2, except that the second jig 4 is not provided with a vacuum through hole, but a buckle 13 is provided at an edge of a second device limiting groove, the substrate is fixed in the second device limiting groove by the buckle 13, the buckle is a buckle with an inverted L-shaped longitudinal section, and two buckles are symmetrically provided at edges of two opposite sides of the second device limiting groove.
The method for sintering interconnection and chip mounting in this embodiment is the same as embodiment 3, except that in step S2, the substrate is fixed in the second device limiting groove by the clip 13.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While still being apparent from variations or modifications that may be made by those skilled in the art are within the scope of the invention.
Claims (10)
1. A jig for sintering interconnection and bonding between semiconductor devices, comprising:
the first jig is provided with at least one first device limiting groove, and the first device limiting groove is suitable for accommodating a first semiconductor device and can limit the first semiconductor device to move in the horizontal direction;
the second jig is provided with at least one second device limiting groove, and the second device limiting groove is suitable for accommodating a second semiconductor device and can limit the movement of the second semiconductor device in the horizontal direction;
the alignment component can fix the relative position of the first jig and the second jig in the horizontal direction;
the first fixture is provided with a first fixing part, and the first fixing part is used for fixing the first semiconductor device in the first device limiting groove; and/or
The second fixture is provided with a second fixing part, and the second fixing part is used for fixing the second semiconductor device in the second device limiting groove.
2. The jig for sintering interconnection and bonding between semiconductor devices according to claim 1, wherein:
The first fixing component is a first vacuum through hole, the first vacuum through hole is communicated with the first device limiting groove, and the first vacuum through hole is suitable for being connected with the vacuumizing assembly.
3. The jig for sintering interconnection and bonding between semiconductor devices according to claim 1, wherein:
the second fixing component is a second vacuum through hole, the second vacuum through hole is communicated with the second device limiting groove, and the second vacuum through hole is suitable for being connected with the vacuumizing assembly.
4. The jig for sintering interconnection and bonding between semiconductor devices according to claim 1, wherein:
the second fixing part is a buckle, and the buckle is arranged at the edge of the second device limiting groove.
5. The jig for sintering interconnection and bonding between semiconductor devices according to claim 1, wherein:
the outer edge of the first jig or the second jig is also provided with a frame, and the height of the frame is not more than the distance between the first jig and the second jig when the film, the chip, the sintered layer and the substrate are laminated.
6. The jig for sintering interconnection and bonding between semiconductor devices according to claim 1, wherein:
The alignment component comprises a positioning column arranged on the first jig and a positioning hole arranged at the relative position of the second jig; or (b)
The alignment part comprises a positioning column arranged on the second jig and a positioning hole arranged at the relative position of the first jig.
7. A method of chip sintering interconnection and bonding, characterized in that it is performed using a jig for sintering interconnection and bonding between semiconductor devices according to any one of claims 1-6, wherein at least a first fixture is provided with a first fixing member, the method comprising the steps of:
s1, placing a substrate provided with a sintering layer in the second device limiting groove of the second jig;
s2, arranging a chip in the first device limiting groove of the first jig, fixing the chip in the first device limiting groove through the first fixing part, and enabling the opening of the first device limiting groove of the first jig to be downward;
s3, placing the first jig above the second jig, enabling the chip to be located at a preset position of the sintering layer, and fixing the relative positions of the first jig and the second jig in the horizontal direction through the alignment part;
S4, transferring the jig for sintering interconnection and surface mounting between the semiconductor devices to sintering equipment to perform a sintering process.
8. The method of die sintering interconnects and patches of claim 7, wherein:
the first fixing component is a first vacuum through hole, the first vacuum through hole is communicated with the first device limiting groove, and the vacuum component applies negative pressure to the chip through the first vacuum through hole to fix the chip in the first device limiting groove.
9. A method of chip sintering interconnection and bonding, characterized in that it is performed using a jig for sintering interconnection and bonding between semiconductor devices according to any one of claims 1 to 6, wherein at least a second fixture is provided with a second fixing member, the method comprising the steps of:
s1, placing a chip in the first device limiting groove of the first jig;
s2, arranging a substrate provided with a sintered layer in the second device limiting groove of the second jig, and fixing the substrate in the second device limiting groove through the second fixing part, wherein the opening of the second device limiting groove of the second jig is downward;
S3, placing the second jig above the first jig, enabling the chip to be located at a preset position of the sintering layer, and fixing the relative positions of the first jig and the second jig in the horizontal direction through the alignment part;
s4, transferring the jig for sintering interconnection and surface mounting between the semiconductor devices to sintering equipment to perform a sintering process.
10. The method of die sintering interconnects and patches of claim 7 or 9, wherein:
the chip is provided with a first device limiting groove and a second device limiting groove, and a protective film is arranged between the first device limiting groove and the chip of the first jig; the protective film is used for protecting the chip, and micropores through which gas can pass are formed in the protective film.
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| CN202310504349.8A CN116564852A (en) | 2023-05-05 | 2023-05-05 | Jig for sintering interconnection and patch between semiconductor devices and method for interconnection and patch |
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| CN202310504349.8A CN116564852A (en) | 2023-05-05 | 2023-05-05 | Jig for sintering interconnection and patch between semiconductor devices and method for interconnection and patch |
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| WO2022218906A1 (en) * | 2021-04-16 | 2022-10-20 | Danfoss Silicon Power Gmbh | Electronic device and method of manufacturing it |
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| US20090039484A1 (en) * | 2007-08-06 | 2009-02-12 | Infineon Technologies Ag | Semiconductor device with semiconductor chip and method for producing it |
| CN101587858A (en) * | 2008-05-23 | 2009-11-25 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor device interconnected structure and manufacturing method thereof |
| CN103811382A (en) * | 2014-01-23 | 2014-05-21 | 株洲南车时代电气股份有限公司 | Device for corrosion of table-boards of chips of sintering semiconductor device |
| DE102021109658B3 (en) * | 2021-04-16 | 2022-10-20 | Danfoss Silicon Power Gmbh | Method of manufacturing a semiconductor power device and semiconductor power device manufactured therewith and a tool part for a sintering press and use of a sintering press |
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