CN116564392A

CN116564392A - Read voltage correction method, memory device and memory control circuit unit

Info

Publication number: CN116564392A
Application number: CN202310564246.0A
Authority: CN
Inventors: 陈思玮; 林祐弘; 黄意淞; 苏柏诚
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2023-05-18
Filing date: 2023-05-18
Publication date: 2023-08-08

Abstract

The invention provides a read voltage correction method, a memory storage device and a memory control circuit unit. The method comprises the following steps: reading the first physical unit based on a first reading voltage level according to the first reading instruction to obtain first data, wherein the first reading voltage level is a preset reading voltage level corresponding to the first physical unit, or a first voltage difference exists between the first reading voltage level and the preset reading voltage level; decoding the first data to obtain first error bit information; reading the first physical unit based on a second reading voltage level according to a second reading instruction to obtain second data, wherein a second voltage difference exists between the second reading voltage level and a preset reading voltage level; decoding the second data to obtain second error bit information; and correcting the preset reading voltage level according to the first error bit information and the second error bit information. Thus, the correction efficiency of the read voltage level can be improved.

Description

Read voltage correction method, memory device and memory control circuit unit

Technical Field

The present invention relates to memory management, and more particularly, to a read voltage correction method, a memory storage device and a memory control circuit unit.

Background

Portable electronic devices such as mobile phones and notebook computers have grown very rapidly over the years, and consumer demand for storage media has also increased rapidly. Since a rewritable non-volatile memory module (e.g., flash memory) has characteristics of non-volatility of data, power saving, small size, and no mechanical structure, it is very suitable for being built in the above-exemplified various portable electronic devices.

When the memory storage device leaves the factory, the read voltage level used for reading data from the rewritable nonvolatile memory module is at a preset voltage position. As the usage time of the rewritable nonvolatile memory module increases, the threshold voltage distribution of the memory cells in the rewritable nonvolatile memory module may shift. At this time, the data is read from the rewritable nonvolatile memory module using the read voltage level set by the factory, and a large number of error bits are read with a high probability. If the read data contains too many erroneous bits, the erroneous bits may not be completely corrected, and thus a read error occurs.

Generally, when the voltage position of the read voltage level is greatly shifted compared to the threshold voltage distribution of the memory cell, the optimum read voltage level searching operation can be used to search the optimum voltage position of the current read voltage level. However, during the optimal read level search operation, a specific physical page or physical block in the rewritable nonvolatile memory module is repeatedly read multiple times, resulting in additional power consumption of the memory storage device. In addition, if the optimum read level searching operation occurs in a general read process (e.g., after a plurality of hard decoding failures), the optimum read level searching operation may cause a significant decrease in the data read performance of the memory device.

Disclosure of Invention

The invention provides a read voltage correction method, a memory storage device and a memory control circuit unit, which can improve the correction efficiency of read voltage level.

An exemplary embodiment of the present invention provides a read voltage correction method for a rewritable nonvolatile memory module including a plurality of physical units, the read voltage correction method including: receiving a first read instruction from a host system, wherein the first read instruction indicates reading data belonging to a first logical unit, and the first logical unit is mapped to a first physical unit of the plurality of physical units; reading the first physical unit based on a first reading voltage level according to the first reading instruction to obtain first data, wherein the first reading voltage level is a preset reading voltage level corresponding to the first physical unit or a first voltage difference exists between the first reading voltage level and the preset reading voltage level; decoding the first data to obtain first error bit information corresponding to the first data; receiving a second read instruction from the host system, wherein the second read instruction indicates to read the data belonging to the first logical unit; reading the first physical unit based on a second reading voltage level according to the second reading instruction to obtain second data, wherein a second voltage difference exists between the second reading voltage level and the preset reading voltage level; decoding the second data to obtain second error bit information corresponding to the second data; and correcting the preset reading voltage level according to the first error bit information and the second error bit information.

In an example embodiment of the present invention, a voltage value of the first read voltage level is different from a voltage value of the second read voltage level.

In an exemplary embodiment of the present invention, in the case that the first voltage difference exists between the first read voltage level and the preset read voltage level, the voltage value of the preset read voltage level is between the voltage value of the first read voltage level and the voltage value of the second read voltage level.

In an example embodiment of the present invention, the first error bit information includes a first value, the first value is directly related to a bit error rate of the first data, the second error bit information includes a second value, and the second value is directly related to a bit error rate of the second data.

In an exemplary embodiment of the present invention, the step of correcting the preset read voltage level according to the first error bit information and the second error bit information includes: and adjusting the preset read voltage level by using a target voltage difference according to the first error bit information and the second error bit information to correct the preset read voltage level, wherein the target voltage difference is one of the first voltage difference and the second voltage difference.

In an exemplary embodiment of the present invention, the step of adjusting the preset read voltage level using the target voltage difference according to the first error bit information and the second error bit information includes: comparing the first error bit information with the second error bit information; and determining the one of the first voltage difference and the second voltage difference as the target voltage difference according to a comparison result.

In an example embodiment of the present invention, according to the first read command, the step of reading the first physical unit based on the first read voltage level to obtain the first data includes: in response to the first read instruction, before decoding any data read from the first physical unit, reading the first physical unit based on the first read voltage level to obtain the first data, and in accordance with the second read instruction, reading the first physical unit based on the second read voltage level to obtain the second data, comprising: in response to the second read instruction, the first physical unit is read based on the second read voltage level to obtain the second data before decoding any data read from the first physical unit.

In an exemplary embodiment of the invention, the read voltage correction method further includes: and applying the correction of the preset read voltage level to a second entity unit in the plurality of entity units to correct the preset read voltage level corresponding to the second entity unit, wherein the first entity unit and the second entity unit belong to the same die (die), the same plane or the same chip enabling area in the rewritable nonvolatile memory module.

Exemplary embodiments of the present invention provide a memory storage device including a connection interface unit, a rewritable nonvolatile memory module, and a memory control circuit unit. The connection interface unit is used for being connected to a host system. The rewritable nonvolatile memory module includes a plurality of physical units. The memory control circuit unit is connected to the connection interface unit and the rewritable nonvolatile memory module. The memory control circuit unit is used for: receiving a first read instruction from the host system, wherein the first read instruction indicates reading data belonging to a first logical unit, and the first logical unit is mapped to a first physical unit of the plurality of physical units; according to the first reading instruction, a first reading instruction sequence is sent, and the first reading instruction sequence indicates that the first entity unit is read based on a first reading voltage level to obtain first data, wherein the first reading voltage level is a preset reading voltage level corresponding to the first entity unit, or a first voltage difference exists between the first reading voltage level and the preset reading voltage level; decoding the first data to obtain first error bit information corresponding to the first data; receiving a second read instruction from the host system, wherein the second read instruction indicates to read the data belonging to the first logical unit; sending a second read command sequence according to the second read command, wherein the second read command sequence indicates that the first entity unit is read based on a second read voltage level to obtain second data, and a second voltage difference exists between the second read voltage level and the preset read voltage level; decoding the second data to obtain second error bit information corresponding to the second data; and correcting the preset reading voltage level according to the first error bit information and the second error bit information.

In an example embodiment of the present invention, the operation of the memory control circuit unit to correct the preset read voltage level according to the first error bit information and the second error bit information includes: and adjusting the preset read voltage level by using a target voltage difference according to the first error bit information and the second error bit information to correct the preset read voltage level, wherein the target voltage difference is one of the first voltage difference and the second voltage difference.

In an example embodiment of the present invention, the operation of the memory control circuit unit to adjust the preset read voltage level using the target voltage difference according to the first error bit information and the second error bit information includes: comparing the first error bit information with the second error bit information; and determining the one of the first voltage difference and the second voltage difference as the target voltage difference according to a comparison result.

In an example embodiment of the present invention, the memory control circuit unit transmitting the first read instruction sequence indicating an operation of reading the first physical unit based on the first read voltage level to obtain the first data according to the first read instruction comprises: in response to the first read instruction, before decoding any data read from the first entity unit, sending the first read instruction sequence that instructs reading the first entity unit based on the first read voltage level to obtain the first data, wherein the memory control circuit unit sends the second read instruction sequence that instructs reading the first entity unit based on the second read voltage level to obtain the second data according to the second read instruction comprises: in response to the second read instruction, the second sequence of read instructions is sent that instructs the first physical unit to be read based on the second read voltage level to obtain the second data before decoding any data read from the first physical unit.

In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to: and applying the correction of the preset read voltage level to a second entity unit in the plurality of entity units to correct the preset read voltage level corresponding to the second entity unit, wherein the first entity unit and the second entity unit belong to the same die, the same plane or the same chip enabling area in the rewritable nonvolatile memory module.

Exemplary embodiments of the present invention provide a memory control circuit unit for controlling a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module includes a plurality of physical units. The memory control circuit unit comprises a host interface, a memory interface, an error checking and correcting circuit and a memory management circuit. The host interface is configured to connect to a host system. The memory interface is configured to connect to the rewritable non-volatile memory module. The memory management circuit is connected to the host interface, the memory interface, and the error checking and correcting circuit. The memory management circuit is to: receiving a first read instruction from the host system, wherein the first read instruction indicates reading data belonging to a first logical unit, and the first logical unit is mapped to a first physical unit of the plurality of physical units; according to the first reading instruction, a first reading instruction sequence is sent, and the first reading instruction sequence indicates that the first entity unit is read based on a first reading voltage level to obtain first data, wherein the first reading voltage level is a preset reading voltage level corresponding to the first entity unit, or a first voltage difference exists between the first reading voltage level and the preset reading voltage level; decoding the first data via the error checking and correction circuit to obtain first error bit information corresponding to the first data; receiving a second read instruction from the host system, wherein the second read instruction indicates to read the data belonging to the first logical unit; sending a second read command sequence according to the second read command, wherein the second read command sequence indicates that the first entity unit is read based on a second read voltage level to obtain second data, and a second voltage difference exists between the second read voltage level and the preset read voltage level; decoding the second data via the error checking and correcting circuit to obtain second error bit information corresponding to the second data; and correcting the preset reading voltage level according to the first error bit information and the second error bit information.

In an example embodiment of the present invention, the operation of the memory management circuit to correct the preset read voltage level according to the first error bit information and the second error bit information includes: and adjusting the preset read voltage level by using a target voltage difference according to the first error bit information and the second error bit information to correct the preset read voltage level, wherein the target voltage difference is one of the first voltage difference and the second voltage difference.

In an example embodiment of the present invention, the operation of the memory management circuit to adjust the preset read voltage level using the target voltage difference according to the first error bit information and the second error bit information includes: comparing the first error bit information with the second error bit information; and determining the one of the first voltage difference and the second voltage difference as the target voltage difference according to a comparison result.

In an example embodiment of the present invention, the memory management circuit transmitting the first sequence of read instructions according to the first read instruction, which indicates an operation of reading the first physical unit based on the first read voltage level to obtain the first data, includes: in response to the first read instruction, prior to decoding any data read from the first physical unit, sending the first read instruction sequence to instruct reading the first physical unit based on the first read voltage level to obtain the first data, wherein the memory management circuit sends the second read instruction sequence in accordance with the second read instruction that instructs reading the first physical unit based on the second read voltage level to obtain the second data comprises: in response to the second read instruction, the second sequence of read instructions is sent that instructs the first physical unit to be read based on the second read voltage level to obtain the second data before decoding any data read from the first physical unit.

In an example embodiment of the present invention, the memory management circuit is further configured to: and applying the correction of the preset read voltage level to a second entity unit in the plurality of entity units to correct the preset read voltage level corresponding to the second entity unit, wherein the first entity unit and the second entity unit belong to the same die, the same plane or the same chip enabling area in the rewritable nonvolatile memory module.

Based on the above, according to the plurality of read commands from the host system and directed to the same physical unit (i.e. the first physical unit), different read voltage levels can be used to read the first physical unit, and the preset read voltage level corresponding to the first physical unit can be corrected according to the read result and/or the decoding result of the read commands. Therefore, the preset read voltage level of the physical unit can be effectively corrected on the premise of not affecting the data read performance of the memory storage device as much as possible.

Drawings

FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device, according to an example embodiment of the invention;

FIG. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to an example embodiment of the invention;

FIG. 3 is a schematic diagram of a host system and a memory storage device according to an example embodiment of the invention;

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention;

FIG. 5 is a schematic block diagram of a memory control circuit unit according to an example embodiment of the invention;

FIG. 6 is a schematic diagram illustrating managing a rewritable non-volatile memory module according to an example embodiment of the present invention;

FIG. 7 is a schematic diagram showing the threshold voltage distribution and the correction of the predetermined read voltage level of the memory cell according to an exemplary embodiment of the present invention;

FIG. 8 is a schematic diagram illustrating the threshold voltage distribution and correction of the preset read voltage level of the memory cell according to an exemplary embodiment of the present invention;

fig. 9 is a flowchart illustrating a read voltage correction method according to an exemplary embodiment of the present invention.

Detailed Description

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable nonvolatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). The memory storage device may be used with a host system such that the host system may write data to or read data from the memory storage device.

FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention. FIG. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to an example embodiment of the invention.

Referring to fig. 1 and 2, the host system 11 may include a processor 111, a random access memory (random access memory, RAM) 112, a Read Only Memory (ROM) 113, and a data transfer interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transfer interface 114 may be connected to a system bus 110.

In an example embodiment, host system 11 may be coupled to memory storage device 10 via data transfer interface 114. For example, host system 11 may store data to memory storage device 10 or read data from memory storage device 10 via data transfer interface 114. In addition, host system 11 may be connected to I/O device 12 via system bus 110. For example, host system 11 may transmit output signals to I/O device 12 or receive input signals from I/O device 12 via system bus 110.

In an exemplary embodiment, the processor 111, the ram 112, the rom 113, and the data transfer interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. The motherboard 20 may be connected to the memory storage device 10 via a wired or wireless connection via the data transmission interface 114.

In an example embodiment, the memory storage device 10 may be, for example, a usb flash disk 201, a memory card 202, a solid state disk (Solid State Drive, SSD) 203, or a wireless memory storage device 204. The wireless memory storage 204 may be, for example, a near field communication (Near Field Communication, NFC) memory storage, a wireless facsimile (WiFi) memory storage, a Bluetooth (Bluetooth) memory storage, or a Bluetooth low energy memory storage (such as iBeacon) or the like based on a wide variety of wireless communication technologies. In addition, the motherboard 20 may also be connected to various I/O devices such as a global positioning system (Global Positioning System, GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 through the system bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 through the wireless transmission device 207.

In an example embodiment, host system 11 is a computer system. In an example embodiment, host system 11 may be any system that may substantially cooperate with a memory storage device to store data. In an example embodiment, the memory storage device 10 and the host system 11 may include the memory storage device 30 and the host system 31 of fig. 3, respectively.

FIG. 3 is a schematic diagram of a host system and a memory storage device according to an example embodiment of the invention. Referring to fig. 3, the memory storage device 30 may be used with the host system 31 to store data. For example, the host system 31 may be a system such as a digital camera, video camera, communication device, audio player, video player, or tablet computer. For example, the memory storage device 30 may be a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded memory device 34 used by a host system 31. The embedded storage device 34 includes embedded storage devices of various types such as an embedded multimedia card (embedded Multi Media Card, eMMC) 341 and/or an embedded multi-chip package (embedded Multi Chip Package, eMCP) storage device 342 that directly connect the memory module to a substrate of the host system.

Fig. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention. Referring to fig. 4, the memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a rewritable nonvolatile memory module 43.

The connection interface unit 41 is used to connect the memory storage device 10 to the host system 11. The memory storage device 10 may communicate with the host system 11 via the connection interface unit 41. In an exemplary embodiment, the connection interface unit 41 is compatible with the peripheral component interconnect local bus (Peripheral Component Interconnect Express, PCI Express) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 41 may be a serial advanced technology attachment (Serial Advanced Technology Attachment, SATA) compliant standard, a parallel advanced technology attachment (Parallel Advanced Technology Attachment, PATA) standard, an institute of electrical and electronics engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 standard, a universal serial bus (Universal Serial Bus, USB) standard, an SD interface standard, a Ultra High Speed-I (UHS-I) interface standard, a Ultra High Speed-II (UHS-II) interface standard, a Memory Stick (MS) interface standard, an MCP interface standard, an MMC interface standard, an eMMC interface standard, a universal flash Memory (Universal Flash Storage, UFS) interface standard, an eMCP interface standard, a CF interface standard, an integrated drive electronics interface (Integrated Device Electronics, IDE) standard, or other suitable standard. The connection interface unit 41 may be packaged in one chip with the memory control circuit unit 42, or the connection interface unit 41 may be disposed outside a chip including the memory control circuit unit 42.

The memory control circuit unit 42 is connected to the connection interface unit 41 and the rewritable nonvolatile memory module 43. The memory control circuit unit 42 is used for executing a plurality of logic gates or control instructions implemented in hardware or firmware and performing operations of writing, reading and erasing data in the rewritable nonvolatile memory module 43 according to the instructions of the host system 11.

The rewritable nonvolatile memory module 43 is used for storing data written by the host system 11. The rewritable nonvolatile memory module 43 may include a single-Level memory Cell (Single Level Cell, SLC) NAND type flash memory module (i.e., a flash memory module that can store 1 bit in one memory Cell), a second-Level memory Cell (MLC) NAND type flash memory module (i.e., a flash memory module that can store 2 bits in one memory Cell), a third-Level memory Cell (Triple Level Cell, TLC) NAND type flash memory module (i.e., a flash memory module that can store 3 bits in one memory Cell), a fourth-Level memory Cell (QLC) NAND type flash memory module (i.e., a flash memory module that can store 4 bits in one memory Cell), other flash memory modules, or other memory modules having the same characteristics.

Each memory cell in the rewritable nonvolatile memory module 43 stores one or more bits with a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, there is a charge trapping layer between the control gate (control gate) and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming" the memory cell. As the threshold voltage changes, each memory cell in the rewritable nonvolatile memory module 43 has a plurality of memory states. By applying a read voltage, it is possible to determine which memory state a memory cell belongs to, and thereby obtain one or more bits stored in the memory cell.

In an exemplary embodiment, the memory cells of the rewritable nonvolatile memory module 43 may constitute a plurality of physical program units, and the physical program units may constitute a plurality of physical erase units. Specifically, memory cells on the same word line may constitute one or more physical programming units. If each memory cell can store more than 2 bits, the physical programming units on the same word line can be categorized into at least a lower physical programming unit and an upper physical programming unit. For example, the least significant bit (Least Significant Bit, LSB) of a memory cell is that belonging to the lower physical programming cell, and the most significant bit (Most Significant Bit, MSB) of a memory cell is that belonging to the upper physical programming cell. In general, in MLC NAND-type flash memory, the writing speed of the lower physical programming unit is greater than the writing speed of the upper physical programming unit, and/or the reliability of the lower physical programming unit is higher than the reliability of the upper physical programming unit.

In an exemplary embodiment, the physical programming unit is a minimum unit of programming. That is, the physical programming unit is the smallest unit of write data. For example, the physical programming unit may be a physical page (page) or a physical sector (sector). If the physical programming units are physical pages, the physical programming units may include data bits and redundancy bits. The data bit area includes a plurality of physical sectors for storing user data, and the redundant bit area is used for storing system data (e.g., management data such as error correction codes). In an exemplary embodiment, the data bit area includes 32 physical sectors, and a physical sector has a size of 512 bytes (B). However, in other exemplary embodiments, 8, 16 or a greater or lesser number of physical fans may be included in the data bit zone, and the size of each physical fan may be greater or lesser. On the other hand, a physical erase unit is the minimum unit of erase. That is, each physically erased cell contains a minimum number of memory cells that are erased together. For example, the physical erased cells are physical blocks (blocks).

Fig. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. Referring to fig. 5, the memory control circuit unit 42 includes a memory management circuit 51, a host interface 52, a memory interface 53, and an error checking and correcting circuit 54.

The memory management circuit 51 is used for controlling the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has a plurality of control commands, and when the memory storage device 10 is operated, the control commands are executed to perform operations such as writing, reading and erasing data. The operation of the memory management circuit 51 is explained as follows, which is equivalent to the explanation of the operation of the memory control circuit unit 42.

In an example embodiment, the control instructions of the memory management circuit 51 are implemented in firmware. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read-only memory (not shown), and the control instructions are burned into the read-only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading and erasing data.

In an exemplary embodiment, the control instructions of the memory management circuit 51 may also be stored in a program code format in a specific area of the rewritable nonvolatile memory module 43 (e.g., a system area dedicated to storing system data in the memory module). In addition, the memory management circuit 51 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the rom has a boot code (boot code), and when the memory control circuit unit 42 is enabled, the microprocessor unit executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 43 into the ram of the memory management circuit 51. Then, the microprocessor unit operates the control instructions to perform operations such as writing, reading and erasing of data.

In an exemplary embodiment, the control instructions of the memory management circuit 51 may also be implemented in a hardware type. For example, the memory management circuit 51 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, the memory write circuit, the memory read circuit, the memory erase circuit and the data processing circuit are connected to the microcontroller. The memory cell management circuit is used to manage the memory cells or groups of memory cells of the rewritable nonvolatile memory module 43. The memory write circuit is used for issuing a write instruction sequence to the rewritable nonvolatile memory module 43 to write data into the rewritable nonvolatile memory module 43. The memory read circuit is used for issuing a read instruction sequence to the rewritable nonvolatile memory module 43 to read data from the rewritable nonvolatile memory module 43. The memory erase circuit is used for issuing an erase command sequence to the rewritable nonvolatile memory module 43 to erase data from the rewritable nonvolatile memory module 43. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 43 and data read from the rewritable nonvolatile memory module 43. The write command sequence, the read command sequence, and the erase command sequence may each include one or more program codes or command codes and are used to instruct the rewritable nonvolatile memory module 43 to perform corresponding writing, reading, and erasing operations. In an example embodiment, the memory management circuit 51 may also issue other types of instruction sequences to the rewritable nonvolatile memory module 43 to instruct the corresponding operations to be performed.

The host interface 52 is connected to the memory management circuit 51. Memory management circuitry 51 may communicate with host system 11 through host interface 52. The host interface 52 is used to receive and identify the commands and data transmitted by the host system 11. For example, instructions and data transmitted by host system 11 may be transmitted to memory management circuit 51 via host interface 52. In addition, the memory management circuitry 51 may communicate data to the host system 11 through the host interface 52. In the present example embodiment, host interface 52 is compatible with the PCI Express standard. However, it should be understood that the present invention is not limited thereto, and the host interface 52 may also be compatible with SATA standards, PATA standards, IEEE 1394 standards, USB standards, SD standards, UHS-I standards, UHS-II standards, MS standards, MMC standards, eMMC standards, UFS standards, CF standards, IDE standards, or other suitable data transfer standards.

The memory interface 53 is connected to the memory management circuit 51 and is used to access the rewritable nonvolatile memory module 43. For example, the memory management circuit 51 may access the rewritable nonvolatile memory module 43 through the memory interface 53. That is, the data to be written into the rewritable nonvolatile memory module 43 is converted into a format acceptable to the rewritable nonvolatile memory module 43 through the memory interface 53. Specifically, if the memory management circuit 51 is to access the rewritable nonvolatile memory module 43, the memory interface 53 transmits the corresponding instruction sequence. For example, the instruction sequences may include a write instruction sequence that indicates write data, a read instruction sequence that indicates read data, an erase instruction sequence that indicates erase data, and corresponding instruction sequences to indicate various memory operations (e.g., changing read voltage levels or performing garbage collection operations, etc.). These sequences of instructions are, for example, generated by the memory management circuit 51 and transferred to the rewritable non-volatile memory module 43 via the memory interface 53. These instruction sequences may include one or more signals, or data, on a bus. Such signals or data may include instruction code or program code. For example, the read command sequence includes information such as the read identification code and the memory address.

The error checking and correcting circuit 54 is connected to the memory management circuit 51 and is used for performing error checking and correcting operations to ensure the correctness of the data. Specifically, when the memory management circuit 51 receives a write command from the host system 11, the error checking and correcting circuit 54 generates a corresponding error correction code (error correcting code, ECC) and/or error checking code (error detecting code, EDC) for the data corresponding to the write command, and the memory management circuit 51 writes the data corresponding to the write command and the corresponding error correction code and/or error checking code into the rewritable nonvolatile memory module 43. Then, when the memory management circuit 51 reads data from the rewritable nonvolatile memory module 43, the error correction code and/or the error check code corresponding to the data are read at the same time, and the error check and correction circuit 54 performs an error check and correction operation on the read data according to the error correction code and/or the error check code. For example, the error checking and correction circuit 54 may support various encoding/decoding algorithms such as low density parity check codes (Low Density Parity Check code, LDPC codes) or BCH.

In an exemplary embodiment, the memory control circuit unit 42 further includes a buffer memory 55 and a power management circuit 56. The buffer memory 55 is connected to the memory management circuit 51 and is used for temporarily storing data. The power management circuit 56 is connected to the memory management circuit 51 and is used to control the power of the memory storage device 10.

In an example embodiment, the rewritable non-volatile memory module 43 of fig. 4 may include a flash memory module. In an example embodiment, the memory control circuit unit 42 of fig. 4 may include a flash memory controller. In an example embodiment, the memory management circuit 51 of fig. 5 may include a flash memory management circuit.

FIG. 6 is a schematic diagram illustrating managing a rewritable non-volatile memory module according to an example embodiment of the present invention. Referring to FIG. 6, the memory management circuit 51 can logically group the physical units 610 (0) -610 (B) in the rewritable nonvolatile memory module 43 into a memory area 601 and a spare (spare) area 602.

In an exemplary embodiment, a physical unit refers to a physical address or a physical programming unit. In an exemplary embodiment, a physical unit may also be composed of a plurality of consecutive or non-consecutive physical addresses. In an exemplary embodiment, a physical unit may also be referred to as a Virtual Block (VB). A virtual block may include multiple physical addresses or multiple physical programming units.

The entity units 610 (0) -610 (a) in the storage area 601 are used to store user data (e.g., user data from the host system 11 of fig. 1). For example, the entity units 610 (0) to 610 (a) in the storage area 601 may store valid (valid) data and invalid (invalid) data. The physical units 610 (a+1) -610 (B) in the free area 602 do not store data (e.g., valid data). For example, if a physical unit does not store valid data, the physical unit may be associated (or added) to the idle area 602. In addition, the physical cells in the free area 602 (or the physical cells that do not store valid data) may be erased. When writing new data, one or more physical units may be extracted from the spare area 602 to store the new data. In an exemplary embodiment, the free area 602 is also referred to as a free pool (free pool).

The memory management circuit 51 may configure the logic units 612 (0) through 612 (C) to map the physical units 610 (0) through 610 (A) in the memory area 601. In an exemplary embodiment, each logical unit corresponds to a logical address. For example, a logical address may include one or more logical block addresses (Logical Block Address, LBAs) or other logical management units. In an exemplary embodiment, a logic unit may also correspond to a logic programming unit or be composed of a plurality of consecutive or non-consecutive logic addresses.

It should be noted that a logical unit may be mapped to one or more physical units. If a certain entity unit is mapped by a certain logic unit, the data stored in the entity unit is valid. Otherwise, if a certain entity unit is not mapped by any logic unit, the data stored in the entity unit is invalid.

The memory management circuit 51 may record management data (also referred to as logic-to-entity mapping information) describing a mapping relationship between the logic units and the entity units in at least one logic-to-entity mapping table. When the host system 11 wants to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 51 can access the rewritable nonvolatile memory module 43 according to the information in the logical-to-physical mapping table.

In an example embodiment, the memory cells in the rewritable nonvolatile memory module 43 may age and/or wear out after a period of use of the rewritable nonvolatile memory module 43 and/or when a large change in ambient temperature occurs. The threshold voltage of the memory cell may shift in response to aging and/or wear of the memory cell. The shift of the threshold voltage of the memory cell refers to the change of the threshold voltage of the memory cell, for example, shift from one voltage location to another voltage location. The offset of the threshold voltage of the memory cell may affect the accuracy of the data read from the memory cell. For example, assume that the threshold voltage of a certain memory cell that was originally programmed is greater than a predetermined read voltage level. However, due to aging and/or wear, the threshold voltage of the memory cell may shift to be less than the predetermined read voltage level. Thus, if the memory cell is read using the predetermined read voltage level, an erroneous bit may be read from the memory cell. Alternatively, it is assumed that the threshold voltage of a certain memory cell that was originally programmed is less than a predetermined read voltage level. However, due to aging and/or wear, the threshold voltage of the memory cell may shift to be greater than the predetermined read voltage level. Therefore, if the predetermined read voltage level is used to read the memory cell, the erroneous bits may also be read from the memory cell.

In an example embodiment, the error checking and correction circuit 54 may include one or more decoding circuits. This decoding circuit may be used to decode data read from the rewritable nonvolatile memory module 43. For example, the decoding circuit may attempt to correct some or all of the erroneous bits in the read data. For example, in an example embodiment, error checking and correction circuit 54 may encode and decode data using low density parity check codes (LDPC codes). However, in another exemplary embodiment, the error checking and correction circuit 54 may also support BCH codes, convolutional codes (convolutional code), turbo codes (turbo codes), etc., and the invention is not limited thereto. It should be noted that in some cases, if the offset of the threshold voltage of the memory cell is too large, the decoding capability (e.g., decoding success rate) and/or decoding speed of the decoding circuit may be reduced.

FIG. 7 is a schematic diagram illustrating the threshold voltage distribution and correction of the predetermined read voltage level of the memory cell according to an exemplary embodiment of the present invention. Referring to fig. 7, taking a certain physical cell (also referred to as a first physical cell) in the rewritable nonvolatile memory module 43 as an example, the threshold voltage distribution of the memory cell in the first physical cell includes states 701 and 702. For example, the first entity may be one of entity units 610 (0) -610 (a) of fig. 6. In addition, it is assumed that the read voltage level 70 is a preset read voltage level corresponding to the first physical cell.

Ideally, the read voltage level 70 should be located at the interface between the states 701 and 702 to correctly distinguish the memory cells belonging to the states 701 and 702 in the first physical cell. However, as the usage time and/or wear level of the rewritable nonvolatile memory module 43 increases, the threshold voltage distribution of the memory cells in the first physical unit may shift. For example, after the threshold voltage distribution of the memory cell shifts, the voltage location of the read voltage level 70 may be slightly away from the interface between states 701 and 702. Taking fig. 7 as an example, after the offset occurs, the voltage location of the read voltage level 70 is closer to the peak (peak) location of the state 702. It should be noted that the present invention does not limit the actual threshold voltage distribution of the memory cell after the offset.

After the threshold voltage distribution of the memory cell shifts, if the data is read from the first physical cell using the uncorrected read voltage level 70, the read data may contain more erroneous bits. Once the total number of error bits in the read data exceeds the upper limit of the number of error bits that can be corrected by the error checking and correction circuit 54, the error bits in the data cannot be corrected completely.

In an example embodiment, the memory management circuit 51 may perform an optimal read level finding (optimal read level search) operation to find the optimal voltage location for the current read voltage level 70. However, during the optimal read level finding operation, the first physical unit is repeatedly read a plurality of times, resulting in additional power consumption of the memory storage device 10. In addition, generally, after performing multiple re-reads on a specific physical unit and multiple decoding on the read data, if the read data cannot be successfully decoded (i.e. all errors in the data cannot be corrected), the optimal read level search operation is performed. In this case, although the optimum read level search operation can be used to correct the preset read voltage level, the data read performance of the memory device 10 is greatly reduced.

In an exemplary embodiment, the memory management circuit 51 may apply trimming and correction to the predetermined read voltage level (e.g., the read voltage level 70) corresponding to the first physical unit to the conventional data read operation for the first physical unit. For example, when a conventional data read operation is performed according to a read instruction from the host system 11, the memory management circuit 51 may gradually correct the preset read voltage level according to the read result. Therefore, even if the threshold voltage distribution of the memory cells in the first physical unit continuously changes, the voltage position corresponding to the preset reading voltage level of the first physical unit can be always kept at a relatively better voltage position, so that the data accuracy of the read data is improved.

In an exemplary embodiment, compared to the conventional optimum read level searching operation, the trimming and correction of the predetermined read voltage level is applied to the conventional data read operation of the first physical unit, so that the first predetermined read voltage level can be effectively corrected without affecting the data read performance of the memory storage device 10 as much as possible. In addition, applying the fine adjustment or correction of the first preset read voltage level to the conventional data read operation of the first physical unit can also reduce the execution times of the optimal read level searching operation, and may even completely avoid executing the conventional optimal read level searching operation, thereby effectively saving the energy consumption of the memory storage device 10.

In an example embodiment, at a certain point in time (also referred to as a first point in time), the memory management circuit 51 may receive a read instruction (also referred to as a first read instruction) from the host system 11. The first read instruction may instruct to read data belonging to a particular logical unit (also referred to as a first logical unit), and the first logical unit may be mapped to a first physical unit.

In an example embodiment, according to the first read command, the memory management circuit 51 may send a read command sequence (also referred to as a first read command sequence) to the rewritable nonvolatile memory module 43 based on a specific read voltage level (also referred to as a first read voltage level). The first read command sequence may be used to instruct the rewritable nonvolatile memory module 43 to read the first physical cell based on the first read voltage level to obtain data (also referred to as first data). In an exemplary embodiment, the first read voltage level may be a predetermined read voltage level (e.g., read voltage level 70) corresponding to the first physical cell. Alternatively, in an exemplary embodiment, there may be a voltage difference (also referred to as a first voltage difference) between the first read voltage level and the predetermined read voltage level.

In an example embodiment, after obtaining the first data, the memory management circuit 51 may decode the first data via the error checking and correcting circuit 54 to obtain error bit information (also referred to as first error bit information) corresponding to the first data. For example, the first error bit information may include a value (also referred to as a first value). The first value may reflect or be related to a Bit Error Rate (BER) of the first data. That is, the higher the bit error rate of the first data (i.e., the more the total number of error bits in the first data), the larger the first value may be.

In an example embodiment, the error checking and correction circuit 54 may successfully decode the first data. That is, the error checking and correcting circuit 54 can successfully correct all error bits in the first data. The memory management circuit 51 may obtain the first error bit information based on information about the bit error rate of the first data, such as the total number of error bits in the first data recorded by the error checking and correcting circuit 54 during decoding of the first data. The successfully decoded first data may be transmitted back to the host system 11 in response to the first read command.

In an example embodiment, at another point in time (also referred to as a second point in time), the memory management circuit 51 may receive another read instruction (also referred to as a second read instruction) from the host system 11. The first point in time may be different from the second point in time. For example, the first point in time may be earlier or later than the second point in time. Similar to the first read instruction, the second read instruction may instruct to read data belonging to the first logical unit, and the first logical unit may be mapped to the first physical unit.

In an example embodiment, according to the second read command, the memory management circuit 51 may send a read command sequence (also referred to as a second read command sequence) to the rewritable nonvolatile memory module 43 based on another read voltage level (also referred to as a second read voltage level). The second read command sequence may be used to instruct the rewritable nonvolatile memory module 43 to read the first physical cell based on the second read voltage level to obtain data (also referred to as second data). For example, there is also a voltage difference (also referred to as a second voltage difference) between the second read voltage level and the predetermined read voltage level.

In an example embodiment, the voltage value of the first read voltage level may be different from the voltage value of the second read voltage level. For example, the voltage value of the first read voltage level may be less than or greater than the voltage value of the second read voltage level. Alternatively, in an exemplary embodiment, in the case that the first voltage difference exists between the first read voltage level and the preset read voltage level, the voltage value of the preset read voltage level may be between the voltage value of the first read voltage level and the voltage value of the second read voltage level.

In an exemplary embodiment, after the second data is obtained, the memory management circuit 51 may decode the second data through the error checking and correcting circuit 54 to obtain error bit information (also referred to as second error bit information) corresponding to the second data. For example, the second error bit information may include a value (also referred to as a second value). The second value may reflect or be related to a bit error rate of the second data. That is, the second value may be greater the higher the bit error rate of the second data (i.e., the more the total number of error bits in the second data).

In an exemplary embodiment, the error checking and correction circuit 54 may also successfully decode the second data. That is, the error checking and correcting circuit 54 can successfully correct all error bits in the second data. The memory management circuit 51 may obtain the second error bit information based on information about the bit error rate of the second data such as the total number of error bits in the second data recorded by the error checking and correcting circuit 54 during decoding of the second data. The successfully decoded second data may also be returned to the host system 11 in response to the second read command.

In an exemplary embodiment, the memory management circuit 51 may correct the predetermined read voltage level according to the first error bit information and the second error bit information. In an exemplary embodiment, the memory management circuit 51 may adjust the predetermined read voltage level using a voltage difference (also referred to as a target voltage difference) according to the first error bit information and the second error bit information to correct the predetermined read voltage level. For example, the target voltage difference may be one of the first voltage difference and the second voltage difference. For example, the memory management circuit 51 may compare the first error bit information with the second error bit information and determine one of the first voltage difference and the second voltage difference as the target voltage difference according to the comparison result. Then, the memory management circuit 51 may add the target voltage difference to the predetermined read voltage level to correct the predetermined read voltage level.

It should be noted that, in an exemplary embodiment, in response to the first read command, the memory management circuit 51 may send a first read command sequence before decoding any data read from the first physical unit to instruct the rewritable nonvolatile memory module 43 to read the first physical unit based on the first read voltage level to obtain the first data. Similarly, in an example embodiment, in response to the second read instruction, the memory management circuit 51 may send a second sequence of read instructions to instruct the rewritable nonvolatile memory module 43 to read the first physical unit based on the second read voltage level to obtain the second data before decoding any data read from the first physical unit.

In other words, the operations of the rewritable nonvolatile memory module 43 for reading the first physical unit to obtain the first data and the second data based on the first read voltage level and the second read voltage level are conventional data reading operations, and are not re-reading operations or other error handling procedures after decoding failure of specific data occurs.

Taking fig. 7 as an example, in an exemplary embodiment, it is assumed that the first read voltage level is the read voltage level 70 (i.e., the preset read voltage level corresponding to the first physical cell) and the second read voltage level is the read voltage level 71. The read voltage levels 70 and 71 have a voltage difference-DeltaV between them. After receiving the first read instruction from the host system 11, the memory management circuit 51 may perform a normal read operation (also referred to as a first normal read operation) according to the first read instruction. In a first conventional read operation, the memory management circuit 51 may instruct the rewritable non-volatile memory module 43 to read the first physical cell using the read voltage level 70 to obtain the first data. The error checking and correction circuit 54 may then decode the first data. The memory management circuit 51 may obtain the first error bit information according to the decoding result of the first data. In addition, the memory management circuit 51 may transmit the decoded first data back to the host system 11 in response to the first read command.

On the other hand, after receiving the second read instruction from the host system 11, the memory management circuit 51 may perform another normal read operation (also referred to as a second normal read operation) according to the second read instruction. In a second conventional read operation, the memory management circuit 51 may instruct the rewritable non-volatile memory module 43 to read the first physical cell using the read voltage level 71 to obtain the second data. The error checking and correction circuit 54 may then decode the second data. The memory management circuit 51 may obtain the second error bit information according to the decoding result of the second data. In addition, the memory management circuit 51 may transmit the decoded second data back to the host system 11 in response to the second read command.

According to the first error bit information and the second error bit information, the memory management circuit 51 may set the target voltage difference to- ΔV and correct the predetermined read voltage level according to the target voltage difference. For example, the memory management circuit 51 may compare the first value with the second value. It should be noted that in the exemplary embodiment of fig. 7, it is assumed that the second value is smaller than the first value. Therefore, according to the comparison result of the first value and the second value (i.e. the second value is smaller than the first value), the memory management circuit 51 can know that the bit error rate of the second data is lower than that of the first data. In response to the bit error rate of the second data being lower than the bit error rate of the first data (or the result of the comparison of the first value and the second value), the memory management circuit 51 may update the voltage value of the preset read voltage level to be the same as or closer to the voltage value of the read voltage level 71 (e.g., add- ΔV to the voltage value of the read voltage level 70 to obtain a corrected preset read voltage level). Thereafter, reading data from the first physical unit using the corrected preset read voltage level may reduce the bit error rate of the read data. In addition, in an exemplary embodiment, if the comparison result of the first value and the second value reflects that the bit error rate of the first data is lower than the bit error rate of the second data (i.e. the first value is smaller than the second value), the memory management circuit 51 may maintain the voltage value of the predetermined read voltage level to be the same as the voltage value of the read voltage level 70.

FIG. 8 is a schematic diagram illustrating the threshold voltage distribution and correction of the predetermined read voltage level of the memory cell according to an exemplary embodiment of the present invention. Referring to fig. 8, in an exemplary embodiment, it is assumed that the read voltage level 80 is a preset read voltage level corresponding to the first physical cell, the first read voltage level is a read voltage level 81, and the second read voltage level is a read voltage level 82. There is a voltage difference +DeltaV between read voltage levels 80 and 81. The read voltage levels 80 and 82 have a voltage difference-DeltaV therebetween. The voltage value of the read voltage level 80 is between the voltage value of the read voltage level 81 and the voltage value of the read voltage level 82. It should be noted that in an exemplary embodiment, the first read voltage level may also be the read voltage level 82, and the second read voltage level may also be the read voltage level 81.

In the example embodiment of fig. 8, after receiving the first read command from the host system 11, the memory management circuit 51 may perform a normal read operation (i.e., a first normal read operation) according to the first read command. In a first conventional read operation, the memory management circuit 51 may instruct the rewritable non-volatile memory module 43 to read the first physical cell using the read voltage level 81 to obtain the first data. The error checking and correction circuit 54 may then decode the first data. The memory management circuit 51 may obtain the first error bit information according to the decoding result of the first data. In addition, the memory management circuit 51 may transmit the decoded first data back to the host system 11 in response to the first read command.

On the other hand, after receiving the second read instruction from the host system 11, the memory management circuit 51 may perform another normal read operation (i.e., a second normal read operation) according to the second read instruction. In a second conventional read operation, the memory management circuit 51 may instruct the rewritable non-volatile memory module 43 to read the first physical cell using the read voltage level 82 to obtain the second data. The error checking and correction circuit 54 may then decode the second data. The memory management circuit 51 may obtain the second error bit information according to the decoding result of the second data. In addition, the memory management circuit 51 may transmit the decoded second data back to the host system 11 in response to the second read command.

According to the first error bit information and the second error bit information, the memory management circuit 51 may set the target voltage difference to- ΔV and correct the predetermined read voltage level according to the target voltage difference. For example, the memory management circuit 51 may compare the first value with the second value. It should be noted that in the exemplary embodiment of fig. 8, it is assumed that the second value is smaller than the first value. Therefore, according to the comparison result of the first value and the second value (i.e. the second value is smaller than the first value), the memory management circuit 51 can know that the bit error rate of the second data is lower than that of the first data. In response to the bit error rate of the second data being lower than the bit error rate of the first data (or the result of the comparison of the first value and the second value), the memory management circuit 51 may update the voltage value of the preset read voltage level to be the same as or closer to the voltage value of the read voltage level 82 (e.g., add- ΔV to the voltage value of the read voltage level 80 to obtain a corrected preset read voltage level). Thereafter, reading data from the first physical unit using the corrected preset read voltage level may reduce the bit error rate of the read data. In addition, in an exemplary embodiment, if the comparison result of the first value and the second value reflects that the bit error rate of the first data is lower than the bit error rate of the second data (i.e. the first value is smaller than the second value), the memory management circuit 51 may update the voltage value of the predetermined read voltage level to be the same as or more similar to the voltage value of the read voltage level 81 (e.g. add +Δv to the voltage value of the read voltage level 80 to obtain the corrected predetermined read voltage level).

It should be noted that in the exemplary embodiment of fig. 7, the operations for reading data from the first physical unit using the read voltage levels 70 and 71 are performed in response to the first read command and the second read command from the host system 11, respectively. Similarly, in the example embodiment of FIG. 8, the operations for reading data from the first physical unit using the read voltage levels 81 and 82, respectively, are performed in response to the first read command and the second read command from the host system 11, respectively. In other words, the above operations for reading data from the first physical unit using the read voltage levels 70, 71, 81, 82, respectively, are all conventional data reading operations, and are not re-reading operations or other error handling procedures after a decoding failure of specific data occurs.

In an exemplary embodiment, the first read voltage level and the second read voltage level are determined according to a predetermined read voltage level corresponding to the first physical cell. For example, the first read voltage level may be set to be the same as the predetermined read voltage level or have a first voltage difference (e.g., +Δv of fig. 8) from the predetermined read voltage level, and the second read voltage level may be set to have a second voltage difference (e.g., - Δv of fig. 7 and 8) from the predetermined read voltage level. In an exemplary embodiment, both the positive and negative values and the absolute value of the first voltage difference and the second voltage difference can be adjusted according to the practical requirements, which is not limited by the present invention.

In an exemplary embodiment, both the first voltage difference and the second voltage difference may be limited to a predetermined voltage offset range. As long as the first voltage difference and the second voltage difference are both within the voltage offset range, the data read by using the offset first read voltage level (i.e. the first data) and the data read by using the offset second read voltage level (i.e. the second data) can be successfully decoded. Thus, correction of the preset read voltage level corresponding to the first physical cell can be continuously performed along with the conventional data read operation without entering re-reading or performing the optimal read level finding operation. In an exemplary embodiment, it may also be configured to correct the preset read voltage level according to the averaged first error bit information and the averaged second error bit information after performing the conventional read operation repeatedly a plurality of times, so as to avoid excessively frequent adjustment of the preset read voltage level.

In an exemplary embodiment, the memory management circuit 51 may apply the correction of the predetermined read voltage level corresponding to the first physical unit to another physical unit (also referred to as a second physical unit) in the rewritable nonvolatile memory module 43 to correct the predetermined read voltage level corresponding to the second physical unit. For example, when it is determined to use the target voltage difference (e.g., - Δv of fig. 7 or 8) to correct the preset read voltage level corresponding to the first physical unit, the target voltage difference may also be used to correct the preset read voltage level corresponding to the second physical unit.

In an exemplary embodiment, the first entity unit and the second entity unit may belong to the same die (die), the same plane, or the same Chip Enabled (CE) area in the rewritable nonvolatile memory module 43. In addition, the second entity unit may further include other entity units with the same or similar usage status (e.g., P/E cycle) as the first entity unit in the rewritable nonvolatile memory module 43, which is not limited by the present invention. Therefore, the correction efficiency of the preset read voltage level corresponding to the entity units with the same or similar use conditions can be accelerated.

Fig. 9 is a flowchart illustrating a read voltage correction method according to an exemplary embodiment of the present invention. Referring to fig. 9, in step S901, a first read command is received from a host system, wherein the first read command indicates to read data belonging to a first logical unit, and the first logical unit is mapped to a first physical unit. In step S902, according to a first reading instruction, a first physical unit is read based on a first reading voltage level to obtain first data, wherein the first reading voltage level is a preset reading voltage level corresponding to the first physical unit, or a first voltage difference exists between the first reading voltage level and the preset reading voltage level. In step S903, the first data is decoded to obtain first error bit information corresponding to the first data. In step S904, a second read instruction is received from the host system, wherein the second read instruction instructs to read data belonging to the first logical unit. In step S905, according to a second reading command, the first physical unit is read based on a second reading voltage level to obtain second data, wherein the second reading voltage level has a second voltage difference from the preset reading voltage level. In step S906, the second data is decoded to obtain second error bit information corresponding to the second data. In step S907, the preset read voltage level is corrected according to the first error bit information and the second error bit information.

However, the steps in fig. 9 are described in detail above, and will not be described again here. It should be noted that each step in fig. 9 may be implemented as a plurality of program codes or circuits, which is not limited by the present invention. In addition, the method of fig. 9 may be used with the above exemplary embodiment, or may be used alone, and the present invention is not limited thereto.

In summary, the read voltage correction method, the memory storage device and the memory control circuit unit according to the exemplary embodiments of the present invention can apply the fine adjustment and correction of the preset read voltage level of the specific physical cell to the conventional data read operation of the specific physical cell. Therefore, even if the threshold voltage distribution of the memory cells in the specific physical cell continuously changes, the voltage position corresponding to the preset read voltage level of the specific physical cell can be always kept at a relatively better voltage position, so that the data quality of the read data is improved. In addition, compared to the conventional optimum read level searching operation, the calibration operation of the preset read voltage level according to the exemplary embodiment of the present invention can effectively calibrate the preset read voltage level of the specific physical cell without affecting the data reading performance of the memory storage device as much as possible and without greatly increasing the power consumption.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims

1. A read voltage correction method for a rewritable non-volatile memory module, the rewritable non-volatile memory module comprising a plurality of physical cells, the read voltage correction method comprising:

receiving a first read instruction from a host system, wherein the first read instruction indicates reading data belonging to a first logical unit, and the first logical unit is mapped to a first physical unit of the plurality of physical units;

reading the first physical unit based on a first reading voltage level according to the first reading instruction to obtain first data, wherein the first reading voltage level is a preset reading voltage level corresponding to the first physical unit or a first voltage difference exists between the first reading voltage level and the preset reading voltage level;

Decoding the first data to obtain first error bit information corresponding to the first data;

receiving a second read instruction from the host system, wherein the second read instruction indicates to read the data belonging to the first logical unit;

reading the first physical unit based on a second reading voltage level according to the second reading instruction to obtain second data, wherein a second voltage difference exists between the second reading voltage level and the preset reading voltage level;

decoding the second data to obtain second error bit information corresponding to the second data; and

correcting the preset reading voltage level according to the first error bit information and the second error bit information.

2. The read voltage correction method of claim 1 wherein a voltage value of the first read voltage level is different from a voltage value of the second read voltage level.

3. The method of claim 1, wherein a voltage value of the preset read voltage level is between a voltage value of the first read voltage level and a voltage value of the second read voltage level with the first voltage difference between the first read voltage level and the preset read voltage level.

4. The method of claim 1, wherein the first error bit information comprises a first value that is positively correlated to a bit error rate of the first data, the second error bit information comprises a second value that is positively correlated to a bit error rate of the second data.

5. The read voltage correction method of claim 1, wherein correcting the preset read voltage level according to the first and second erroneous-bit information comprises:

adjusting the preset read voltage level using a target voltage difference to correct the preset read voltage level according to the first error bit information and the second error bit information,

wherein the target voltage difference is one of the first voltage difference and the second voltage difference.

6. The read voltage correction method of claim 5, wherein adjusting the preset read voltage level using the target voltage difference according to the first and second error bit information comprises:

comparing the first error bit information with the second error bit information; and

And determining the one of the first voltage difference and the second voltage difference as the target voltage difference according to a comparison result.

7. The read voltage correction method of claim 1, wherein reading the first physical unit based on the first read voltage level to obtain the first data according to the first read command comprises:

in response to the first read instruction, prior to decoding any data read from the first physical unit, reading the first physical unit based on the first read voltage level to obtain the first data,

wherein reading the first physical unit based on the second read voltage level to obtain the second data according to the second read command comprises:

in response to the second read instruction, the first physical unit is read based on the second read voltage level to obtain the second data before decoding any data read from the first physical unit.

8. The read voltage correction method of claim 1, further comprising:

applying the correction of the preset read voltage level to a second physical unit of the plurality of physical units to correct the preset read voltage level corresponding to the second physical unit,

Wherein the first entity unit and the second entity unit belong to the same die, the same plane or the same chip enabling area in the rewritable nonvolatile memory module.

9. A memory storage device, comprising:

a connection interface unit for connecting to a host system;

a rewritable non-volatile memory module including a plurality of physical units; and

a memory control circuit unit connected to the connection interface unit and the rewritable nonvolatile memory module,

wherein the memory control circuit unit is configured to:

receiving a first read instruction from the host system, wherein the first read instruction indicates reading data belonging to a first logical unit, and the first logical unit is mapped to a first physical unit of the plurality of physical units;

according to the first reading instruction, a first reading instruction sequence is sent, and the first reading instruction sequence indicates that the first entity unit is read based on a first reading voltage level to obtain first data, wherein the first reading voltage level is a preset reading voltage level corresponding to the first entity unit, or a first voltage difference exists between the first reading voltage level and the preset reading voltage level;

sending a second read command sequence according to the second read command, wherein the second read command sequence indicates that the first entity unit is read based on a second read voltage level to obtain second data, and a second voltage difference exists between the second read voltage level and the preset read voltage level;

10. The memory storage device of claim 9, wherein a voltage value of the first read voltage level is different than a voltage value of the second read voltage level.

11. The memory storage device of claim 9, wherein a voltage value of the preset read voltage level is between a voltage value of the first read voltage level and a voltage value of the second read voltage level with the first voltage difference between the first read voltage level and the preset read voltage level.

12. The memory storage device of claim 9, wherein the first error bit information comprises a first value that is positively correlated to a bit error rate of the first data, the second error bit information comprises a second value, and the second value is positively correlated to a bit error rate of the second data.

13. The memory storage device of claim 9, wherein the operation of the memory control circuit unit correcting the preset read voltage level according to the first error bit information and the second error bit information comprises:

14. The memory storage device of claim 13, wherein the operation of the memory control circuit unit to adjust the preset read voltage level using the target voltage difference according to the first error bit information and the second error bit information comprises:

15. The memory storage device of claim 9, wherein the memory control circuit unit to send the first sequence of read instructions in accordance with the first read instruction, which indicates that reading the first physical unit based on the first read voltage level to obtain the first data comprises:

in response to the first read instruction, before decoding any data read from the first physical unit, sending the first read instruction sequence, which instructs to read the first physical unit based on the first read voltage level to obtain the first data,

wherein the memory control circuit unit sends the second read instruction sequence indicating that the operation of reading the first physical unit based on the second read voltage level to obtain the second data includes:

in response to the second read instruction, the second sequence of read instructions is sent that instructs the first physical unit to be read based on the second read voltage level to obtain the second data before decoding any data read from the first physical unit.

16. The memory storage device of claim 9, wherein the memory control circuit unit is further to:

17. A memory control circuit unit for controlling a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module includes a plurality of physical units, and the memory control circuit unit comprises:

a host interface for connecting to a host system;

a memory interface to connect to the rewritable non-volatile memory module;

an error checking and correcting circuit; and

a memory management circuit coupled to the host interface, the memory interface, and the error checking and correction circuit,

wherein the memory management circuit is to:

decoding the first data via the error checking and correction circuit to obtain first error bit information corresponding to the first data;

decoding the second data via the error checking and correcting circuit to obtain second error bit information corresponding to the second data; and

18. The memory control circuit unit of claim 17, wherein a voltage value of the first read voltage level is different from a voltage value of the second read voltage level.

19. The memory control circuit unit of claim 17, wherein a voltage value of the preset read voltage level is between a voltage value of the first read voltage level and a voltage value of the second read voltage level with the first voltage difference between the first read voltage level and the preset read voltage level.

20. The memory control circuit unit of claim 17, wherein the first error bit information comprises a first value that is positively correlated to a bit error rate of the first data, the second error bit information comprises a second value that is positively correlated to a bit error rate of the second data.

21. The memory control circuit unit of claim 17, wherein the operation of the memory management circuit to correct the preset read voltage level based on the first error bit information and the second error bit information comprises:

22. The memory control circuit unit of claim 21, wherein the operation of the memory management circuit to adjust the preset read voltage level using the target voltage difference according to the first error bit information and the second error bit information comprises:

23. The memory control circuit unit of claim 17, wherein the memory management circuit, in accordance with the first read instruction, sends the first sequence of read instructions that indicates that reading the first physical unit based on the first read voltage level to obtain the first data comprises:

Wherein the memory management circuit sends the second sequence of read instructions according to the second read instruction, which indicates that the operation of reading the first physical unit based on the second read voltage level to obtain the second data comprises:

24. The memory control circuit unit of claim 17, wherein the memory management circuit is further to: