CN116530228A - Three-dimensional dynamic random access memory and forming method thereof - Google Patents

Three-dimensional dynamic random access memory and forming method thereof Download PDF

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Publication number
CN116530228A
CN116530228A CN202180071909.4A CN202180071909A CN116530228A CN 116530228 A CN116530228 A CN 116530228A CN 202180071909 A CN202180071909 A CN 202180071909A CN 116530228 A CN116530228 A CN 116530228A
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China
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layer
opening
lateral recess
dielectric
semiconductor
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Inventor
姜昌錫
知彦北島
康宋坤
弗雷德里克·费什伯恩
李吉镛
妮琴·K·英吉
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Applied Materials Inc
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Applied Materials Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Thin Film Transistor (AREA)

Abstract

Examples herein relate to three-dimensional (3D) Dynamic Random Access Memory (DRAM) and corresponding methods. In one example, a film stack is formed on a substrate. The film stack includes a plurality of unit stacks, and each unit stack has a first dielectric layer, a semiconductor layer, and a second dielectric layer in sequence. A first opening is formed through the film stack. The second dielectric layer is etched back from the first opening to form a first lateral recess. A gate structure is formed in the first lateral recess and disposed on a portion of the semiconductor layer. A second opening is formed through the film stack, the second opening being laterally disposed from where the first opening is formed. The portion of the semiconductor layer is etched back from the second opening to form a second lateral recess. The capacitor is formed in the region where the second lateral recess is provided and contacts the portion of the semiconductor layer.

Description

Three-dimensional dynamic random access memory and forming method thereof
Background
Technical Field
Examples described herein relate generally to the field of semiconductor processing, and more particularly, to three-dimensional (3D) Dynamic Random Access Memory (DRAM) and methods of forming 3D DRAM.
Background
Technological advances in semiconductor processing have brought integrated circuits to the physical limits of moore's law. These advances have brought new models to devices and structures in integrated circuits. For example, various three-dimensional (3D) devices have been developed for integrated circuits. However, such 3D devices may present a new set of challenges for processing and manufacturing.
Disclosure of Invention
Embodiments of the present disclosure include a method for semiconductor processing. A film stack is formed on a substrate. The film stack includes a plurality of cell stacks, and each cell stack has a first dielectric layer, a semiconductor layer disposed on the first dielectric layer, and a second dielectric layer disposed on the semiconductor layer. A first opening is formed through the film stack. The second dielectric layer is etched back (pull back) from the first opening to form a first lateral recess. A gate structure is formed in the first lateral recess and disposed on a portion of the semiconductor layer. A second opening is formed through the film stack. The second opening is laterally disposed from where the first opening is formed. The grid structure is laterally arranged between the second opening and the first opening. The portion of the semiconductor layer is etched back from the second opening to form a second lateral recess. A capacitor is formed in the region where the second lateral recess is provided. The capacitor contacts the portion of the semiconductor layer.
Embodiments of the present disclosure include a method for semiconductor processing. A film stack is formed on a substrate. The film stack includes a plurality of cell stacks, and each cell stack has a first layer and a second layer disposed on the first layer. A first opening is formed through the film stack. The first layer is etched back from the first opening to form a first lateral recess. A first conformal (conformal) layer is formed in the first lateral recess. A first filler material is formed on the first conformal layer and in the first lateral recess. The first conformal layer is etched back from the first opening to form a second lateral recess. A gate structure is formed in the second lateral recess and disposed on and under the semiconductor layer. The semiconductor layer is horizontally aligned with the second layer. A second opening is formed through the film stack. The second opening is laterally disposed from where the first opening is formed. The grid structure is laterally arranged between the second opening and the first opening. The second layer is etched back from the second opening to form a third lateral recess to the semiconductor layer. A capacitor is formed in the region where the third lateral recess is provided. The capacitor contacts the semiconductor layer.
Embodiments of the present disclosure include a method for semiconductor processing. A film stack is formed on a substrate. The film stack includes at least five layers. Each of the at least five layers is formed from a material selected from the group of materials comprising no more than three different materials. Using the film stack as a mold, a vertically stacked mirrored (mirrored) DRAM pair is formed on the substrate. Each of these vertically stacked mirrored DRAM pairs includes a contact (contact), a first transistor, a second transistor, a first capacitor, and a second capacitor. The first transistor includes a first gate structure, a first source/drain region, and a second source/drain region. The first source/drain region contacts the contact. The second transistor includes a second gate structure, a third source/drain region, and a fourth source/drain region. The third source/drain region contacts the contact. The second transistor mirrors the first transistor around the contact. The first capacitor has a first outer plate, a first capacitor dielectric layer, and a first inner plate. The first outer plate contacts the second source/drain region. The second capacitor has a second outer plate, a second capacitor dielectric layer, and a second inner plate. The second outer plate contacts the fourth source/drain region.
Drawings
So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only some examples and are therefore not to be considered limiting of the scope of the disclosure, for the disclosure may admit to other equally effective examples.
Fig. 1 is a circuit schematic of a Dynamic Random Access Memory (DRAM) cell according to some examples of the present disclosure.
FIG. 2 is a perspective view of a mirrored DRAM pair according to some examples of the present disclosure.
FIG. 3 is a perspective view of a mirrored DRAM pair according to some examples of the present disclosure.
Fig. 4-12 are cross-sectional views of intermediate structures during a first method to form a 3D DRAM cell, according to some examples of the present disclosure.
Fig. 13-27 are cross-sectional views of intermediate structures during a second method to form a 3D DRAM cell, according to some examples of the present disclosure.
Fig. 28-40 are cross-sectional views of intermediate structures during a second method to form a 3D DRAM cell, according to some examples of the present disclosure.
To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures.
Detailed Description
The examples described herein relate generally to semiconductor processing, and more particularly, to three-dimensional (3D) Dynamic Random Access Memory (DRAM) and methods of forming 3D DRAM. According to various examples, a film stack is formed on a substrate. The film stack includes, for example, five or more layers, wherein each of the five or more layers is formed from a material selected from the group of no more than three different materials, and further, in some examples, the material is selected from the group of no more than two different materials. The film stack is formed from one or more cell stacks, each of which is formed from no more than two or three different materials. The film stack is used as a mold to form a 3D DRAM device. In particular, the mold is used to form two or more vertically stacked mirror DRAM pairs. When using a mold process, an increase in the number of different materials for the layers of the mold can result in increased processing costs, including the use of additional deposition and etching processes. Reducing the number of different materials for the layers (such as by the various examples described herein) can reduce processing costs (such as by having fewer deposition processes and etching processes), thus can result in a more cost-effective device. Furthermore, various numbers of vertically stacked mirrored DRAM pairs can be achieved without adding additional different materials. The different examples herein are also capable of implementing single or dual gate transistors for 3D DRAM.
Various examples are described below. Although the various features of the different examples may be described together in a process flow or system, each of the various features can be implemented separately or individually and/or in a different process flow or a different system. In addition, various process flows are described as being performed in sequence; other examples may implement the process flows in a different order and/or with more or less operations. Further, while source and drain nodes and source and drain regions are described in various examples, such descriptions can be more generally directed to source/drain nodes or source/drain regions. Again, in some examples, n-type transistors are described, and more generally, any type of transistor can be implemented.
Fig. 1 is a circuit schematic of a Dynamic Random Access Memory (DRAM) cell according to some examples of the present disclosure. The DRAM cell comprises an n-type transistor 2 and a capacitor 4. The drain node 6 of the n-type transistor 2 is electrically connected to a Bit Line (BL) node 8. The source node 10 of the n-type transistor 2 is electrically connected to a first terminal of the capacitor 4, and a second terminal of the capacitor 4 (opposite the first terminal) is electrically connected to a power supply node (e.g., a ground node). The gate node 12 of the n-type transistor 2 is electrically connected to a Word Line (WL) node.
FIG. 2 is a perspective view of a mirrored DRAM pair according to some examples of the present disclosure. FIG. 2 depicts two DRMA cells, which are mirror images along the vertical axis, and for convenience, two DRAM cells mirror images along the vertical axis may be referred to herein as a mirrored DRAM pair. As will be apparent from the description below, multiple pairs of mirrored DRAM pairs (e.g., two pairs, three pairs, etc.) may be vertically stacked in a DRAM structure. To avoid unnecessarily obscuring the various aspects of the drawings, one DRAM cell of a mirrored DRAM pair is designated with a reference numeral, and one skilled in the art will readily understand the mirroring components in the other DRAM cell of the mirrored DRAM pair.
The DRAM cell includes an n-type transistor 22 and a capacitor 24. The n-type transistor 22 includes a semiconductor material 26 that forms an active region of the n-type transistor 22. For example, semiconductor material 26 may generally be p-doped. A drain region 28 and a source region 30 are disposed in semiconductor material 26, while a channel region is located in semiconductor material 26 between drain region 28 and source region 30. In this example, the drain region 28 and the source region 30 are n-doped. A gate dielectric layer 32 is disposed on semiconductor material 26 (e.g., on a top surface of semiconductor material 26), and a gate electrode 34 is disposed on gate dielectric layer 32.
The capacitor 24 includes an outer plate 36, a capacitor dielectric layer 38, and an inner plate 40. The outer plate 36 is a conductive material such as a metal or metal-containing material. The outer plates 36 generally have the shape of a single-capped cylinder, a single-capped rectangular prism, or the like. The outer plate 36 generally extends laterally from the n-type transistor 22 and has a capped end that contacts the source region 30 of the n-type transistor 22 to electrically connect the source region 30 to the capacitor 24. The end of the outer plate 36 opposite the n-type transistor 22 is open. The capacitor dielectric layer 38 is a dielectric material that is conformally disposed along the interior surfaces of the outer plates 36. The dielectric material of the capacitor dielectric layer 38 can be a high-k dielectric material (e.g., having a k value greater than 4.0). The inner plate 40 is a conductive material, such as a metal or metal-containing material, and is disposed on the capacitor dielectric layer 38 and fills the remaining interior portion of the outer plate 36.
Bit line contact 42 is provided to laterally contact drain region 28 of n-type transistor 22. The bit line contacts 42 extend vertically and a vertical axis (along which the mirror DRAM pair mirrors) extends along the bit line contacts 42. A power contact 44 (e.g., a ground contact) is provided to laterally contact the inner plate 40 of the capacitor 24.
FIG. 3 is a perspective view of a mirrored DRAM pair according to some examples of the present disclosure. The 3D DRAM cell of fig. 3 is similar to the 3D DRAM cell of fig. 2, and common descriptions are omitted for brevity. The DRAM cell includes an n-type transistor 52 and a capacitor 24. The n-type transistor 52 includes a semiconductor material 54, the semiconductor material 54 forming an active region of the n-type transistor 52. For example, semiconductor material 54 may generally be p-doped. A drain region 56 and a source region 58 are disposed in the semiconductor material 54, with a channel region in the semiconductor material 54 between the drain region 56 and the source region 58. In this example, the drain region 56 and the source region 58 are n-doped. A top gate dielectric layer 60 is disposed on semiconductor material 54 (e.g., on a top surface of semiconductor material 54) and a bottom gate dielectric layer 62 is disposed on semiconductor material 54 on a side opposite top gate dielectric layer 60 (e.g., on a bottom surface of semiconductor material 54). A top gate electrode 64 is disposed on top gate dielectric layer 60 (e.g., above) and a bottom gate electrode 66 is disposed on bottom gate dielectric layer 62 (e.g., below).
The capped end of the outer plate 36 contacts the source region 58 of the n-type transistor 52 to electrically connect the source region 58 to the capacitor 24. Bit line contact 42 is provided to laterally contact drain region 56 of n-type transistor 52.
Fig. 4-12 are cross-sectional views of intermediate structures during a first method to form a 3D DRAM cell according to some examples of the present disclosure. The 3D DRAM cell formed according to the first method of fig. 4-12 can be similar to that shown in fig. 2.
Referring to fig. 4, a film stack is deposited on a substrate 100. The film stack includes a plurality of cell stacks (e.g., two cell stacks in the example shown) that are partially sacrificed to form a 3D DRAM cell. It can be appreciated that this method forms a two-layered 3D DRAM cell. In other examples, the cell stack of the repeating film stack can form additional layers of 3D DRAM cells. Also, one example of using a cell stack in a film stack (instance) can form a layer of 3D DRAM cells.
The substrate 100 comprises any suitable semiconductor substrate, such as a bulk substrate, a semiconductor-on-insulator (SOI) substrate, or the like. In some examples, the semiconductor substrate is a bulk silicon wafer. Examples of substrate dimensions include 200mm diameter, 350mm diameter, 400mm diameter, 450mm diameter, and the like. The substrate 100 can further include any layer (e.g., any number of other dielectric layers) or structure on the semiconductor substrate.
The film stack includes a plurality of cell stacks, wherein the cell stacks include a first dielectric layer 102, a semiconductor layer 104, and a second dielectric layer 106. The cell stack of the film stack is, or consists of, the first dielectric layer 102, the semiconductor layer 104 on the first dielectric layer 102, and the second dielectric layer 106 on the semiconductor layer 104. In fig. 4, two examples of such cell stacks are stacked on the substrate 100. The first dielectric layers 102 can each be the same dielectric material, and the second dielectric layers 106 can each be the same dielectric material that is different from the dielectric material of the first dielectric layers 102 and has an etch selectivity between the dielectric materials of the first dielectric layers 102. The semiconductor layers 104 can each be the same semiconductor material. It will be appreciated that the materials of the different layers generally allow for selective etching of the target layer during processing. The film stack is used as a mold for forming the DRAM cell. In some examples, the first dielectric layer 102 is silicon oxide; the second dielectric layer 106 is silicon nitride; and the semiconductor layer 104 is silicon (e.g., amorphous or polycrystalline, which may be p-doped) or InGaZnO. Each of the first dielectric layer 102, the semiconductor layer 104, and the second dielectric layer 106 can be deposited by any suitable deposition technique, such as Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), and the like.
In fig. 5, an opening 108 is formed through the film stack (e.g., through the first dielectric layer 102, the semiconductor layer 104, and the second dielectric layer 106). The opening 108 can be formed by using an anisotropic (anisotropic) etch, such as a Reactive Ion Etch (RIE) or the like.
In fig. 6, the second dielectric layer 106 is etched back from the opening 108 to form lateral recesses 110 from the opening 108. The etch-back process can be any suitable isotropic etch that selectively etches the second dielectric layer 106. For example, when the second dielectric layer 106 is silicon nitride, a hot phosphoric acid etch process can be used to etch back the second dielectric layer 106. Multiple layers in the film stack (e.g., the first dielectric layer 102 and the semiconductor layer 104) can reduce the likelihood of collapse when the second dielectric layer 106 is etched back.
Fig. 7 illustrates a gate dielectric layer 112, a gate blocking and/or work function adjustment ("blocking/adjusting") layer 114, a gate electrode fill material 116, and a dielectric fill material 118. A gate dielectric layer 112 is formed on surfaces of the respective semiconductor layers 104 that are exposed through the openings 108 and the lateral recesses 110. Gate dielectric layer 112 can be any suitable dielectric material formed by any suitable process. In some examples, gate dielectric layer 112 is an oxide formed by an oxidation process (e.g., by oxidizing the exposed surface of semiconductor layer 104). In some examples, gate dielectric layer 112 can be another material formed by a conformal deposition process, such as Atomic Layer Deposition (ALD).
Then, a gate blocking/adjusting layer 114 is formed conformally along the surface of the lateral recess 110, and a gate electrode filling material 116 is formed on the gate blocking/adjusting layer 114. In some examples, the gate blocking/adjustment layer 114 is formed using a conformal deposition process (such as ALD). The conformal deposition process can form a conformal layer on surfaces defining the openings 108 and the lateral recesses 110 (e.g., including the gate dielectric layer 112). The conductive material of gate electrode fill material 116 can then be deposited over the conformal layer by any suitable deposition process. A node separation process is performed to remove some of the conductive material of the gate electrode fill material 116 and some of the conformal layer of the gate blocking/adjusting layer 114 to form the gate blocking/adjusting layer 114 and the gate electrode fill material 116 in the respective lateral recesses 110. The node separation process can include: an anisotropic etch (such as RIE) is performed followed by an isotropic etch selective to the material of the gate barrier/trim layer 114 and the gate electrode fill material 116. The anisotropic etch may remove the conductive material of the gate electrode fill material 116 and the conformal layer of the gate stop/trim layer 114 between the second dielectric layer 106 and the vertical sidewalls of the first dielectric layer 102 defining the opening 108. The isotropic etch laterally recesses the gate electrode fill material 116 and the gate stop/trim layer 114 to have a plurality of vertical sidewalls that are offset from the vertical sidewall surfaces of the semiconductor layer 104 and the first dielectric layer 102 that define the opening 108. In some examples, the gate blocking/tuning layer 114 can be any suitable diffusion blocking material and/or can be any work function tuning material to tune the threshold voltage of the transistor, such as TiN or the like. In some examples, the gate electrode fill material 116 can be any conductive material, such as a metal, for example tungsten.
Dielectric fill material 118 is then formed in the openings 108 and the remaining unfilled portions of the lateral recesses 110. Dielectric fill material 118 can be any suitable dielectric material deposited by any suitable deposition process. In some examples, dielectric fill material 118 is an oxide deposited by a conformal deposition, such as ALD, or a flowable deposition process, such as Flowable CVD (FCVD).
In fig. 8, an opening 120 is formed through the film stack (e.g., through the first dielectric layer 102, the semiconductor layer 104, and the second dielectric layer 106). It can be appreciated that each opening 120 is used for the formation of a capacitor that will electrically connect to a corresponding transistor of which the gate electrode fill material 116 and the gate blocking/adjustment layer 114 are a part. Each opening 120 is disposed a lateral distance from a corresponding gate electrode fill material 116 and gate blocking/adjustment layer 114, and the corresponding gate electrode fill material 116 and gate blocking/adjustment layer 114 are laterally disposed between the respective opening 120 and the location where the opening 108 is formed (e.g., it is filled with dielectric fill material 118). The opening 120 can be formed using an anisotropic etch, such as a Reactive Ion Etch (RIE) or the like.
In fig. 9, semiconductor layer 104 is etched back from the respective openings 120 to form lateral recesses 122 from the respective openings 120. The etch-back process can be any suitable isotropic etch that selectively etches the semiconductor layer 104. For example, when the semiconductor layer 104 is silicon, a tetramethylammonium hydroxide (TMAH) etching process or a dry plasma isotropic etch can be used to etch back the semiconductor layer 104.
At the corresponding lateral recess 122, the semiconductor layer 104 is doped at the vertical sidewall surface of the semiconductor layer 104 to form a source region 124. The source region 124 can be doped with an n-type dopant. Doping can be performed by using a gas phase dopant and/or a plasma-assisted doping process.
In fig. 10, lateral recess 122 is expanded to form an enlarged lateral recess 126. The extension can include an isotropic etch that selectively etches the second dielectric layer 106 and an isotropic etch that selectively etches the first dielectric layer 102. The isotropic etching may be a wet or dry process. In some examples where the first dielectric layer 102 is silicon oxide and the second dielectric layer 106 is silicon nitride, the second dielectric layer 106 can be etched using a hot phosphoric acid etching process or a dry plasma etching process, and the first dielectric layer 102 can be etched using a hydrofluoric acid-based process (e.g., a wet dilute hydrofluoric acid (dHF) or a dry HF process).
Fig. 11 shows the formation of a capacitor in an enlarged lateral recess 126. Each capacitor includes an outer plate 130, a capacitor dielectric layer 132, and an inner plate 134. Outer plate 130 is conformally formed along the surface of enlarged lateral recess 126. In some examples, outer plate 130 is formed using a conformal deposition process (such as ALD). The conformal deposition process can form a conformal layer on surfaces defining the opening 120 and the enlarged lateral recess 126 (e.g., including respective sidewall surfaces of the semiconductor layer 104 where the corresponding source regions 124 are disposed). A node-separation process is performed to remove some of the conformal layer on the vertical sidewalls defining opening 120 to form outer plate 130 in the corresponding enlarged lateral recess 126. The node separation process can include: the opening 120 and the enlarged lateral recesses 126 are filled with a fill material, and suitable anisotropic and isotropic etching processes are performed to remove portions of the conformal layer from the vertical sidewalls defining the opening 120 (e.g., the vertical sidewalls of the first dielectric layer 102 and the second dielectric layer 106) and to remove the fill material.
Then, a capacitor dielectric layer 132 is formed on the inner surface of the corresponding outer plate 130. The capacitor dielectric layer 132 can be formed by a conformal deposition (such as ALD) that forms the conformal capacitor dielectric layer 132 in the respective openings 120 (e.g., along the vertical sidewalls of the second dielectric layer 106 and the first dielectric layer 102 that define the openings 120) and the interior surfaces of the respective outer plates 130.
Then, an inner plate 134 is formed on the outer plate 130. The inner plate 134 can be formed by a conformal deposition (such as ALD) that forms the inner plate 134 over the capacitor dielectric layer 132. In the example shown, the inner plate 134 fills the remaining unfilled portion of the enlarged lateral recess 126, however, in some examples, the inner plate 134 may not fill the remaining unfilled portion of the enlarged lateral recess 126. As shown, the inner plate 134 can be formed from a continuous material deposited in the respective openings 120 and enlarged lateral recesses 126. Since the inner plates 134 form terminals of the respective DRAM cells and these terminals are electrically connected to a power supply node (e.g., a ground node) (as described with respect to FIG. 1), the inner plates 134 can be electrically connected together by a continuous material forming the inner plates 134. In the example shown, the material of the inner plate 134 does not fill the opening 120, and a conductive fill material 136 is formed in the unfilled portion of the opening 120. In some examples, the material of the inner plate 134 fills the remaining unfilled portion of the opening 120. The inner plates 134 and/or the conductive filler material 136, which are electrically connected together, for example, by the material of the inner plates 134, form a power supply node (e.g., a ground node) that is connected between the plurality of DRAM cells. In examples where conductive fill material 136 is used, conductive fill material 136 can be deposited by any suitable deposition process (such as CVD, PVD, etc.).
In some examples, the material of the outer plate 130 and the material of the inner plate 134 can be any conductive material, such as a metal or metal-containing material (such as TiN). In some examples, the material of the capacitor dielectric layer 132 can be any dielectric material, and further can be any high-k dielectric material (e.g., having a k value greater than 4.0). In some examples, the conductive fill material 136 can be any conductive material, such as silicon germanium (e.g., doped silicon germanium).
In fig. 12, a drain region 138, a barrier layer 140, and a conductive fill material 142 are formed. An opening is formed through dielectric fill material 118. The openings expose vertical sidewalls of the semiconductor layer 104. An etching process can be used to form the opening and expose the vertical sidewalls of the semiconductor layer 104. For example, the etching process can include anisotropic etching and/or isotropic etching. The gate dielectric layer 112 previously formed on the vertical sidewalls of the semiconductor layer 104 is removed by an etching process to expose the vertical sidewalls of the semiconductor layer 104.
Lateral portions of the semiconductor layer 104 at the respective vertical sidewalls exposed by the openings are doped to form drain regions 138. Drain region 138 can be doped with an n-type dopant. The doping can be performed by using a gas phase dopant and/or a plasma assisted doping process. With the drain region 138 formed, a corresponding transistor is formed for the DRAM cell. For each DRAM cell, the transistor includes a source region 124 in the semiconductor layer 104, a drain region 138 in the semiconductor layer 104, a channel region in the semiconductor layer 104 between the source region 124 and the drain region 138, and a gate structure disposed on the semiconductor layer 104 that is aligned with respect to the channel region. The gate structure includes a gate dielectric layer 112 and a gate electrode fill material 116. This approach can allow very thin portions of the semiconductor layer 104 to be implemented for the channel region of the transistor.
Then, a barrier layer 140 is formed in the opening. The barrier layer 140 is conformally formed along the surfaces of the opening, including along the exposed vertical sidewalls of the semiconductor layer 104 where the drain region 138 is disposed. In some examples, barrier layer 140 is formed using a conformal deposition process (such as ALD). Conductive fill material 142 can then be deposited over barrier layer 140 by any suitable deposition process. In some examples, the barrier layer 140 can be any suitable diffusion barrier material, such as TiN or the like. In some examples, the conductive filler material 142 can be any conductive material, such as a metal, for example tungsten. Barrier layer 140 and conductive fill material 142 generally form a contact that may be a bit line node of a DRAM cell. The contact is along a vertical axis about which the mirrored DRAM pair mirrors.
Fig. 13-27 are cross-sectional views of intermediate structures during a second method to form a 3D DRAM cell, according to some examples of the present disclosure. The 3D DRAM cell formed according to the second method of fig. 13 to 27 can be similar to that shown in fig. 3.
Referring to fig. 13, a film stack is deposited on a substrate 100. The film stack includes a plurality of cell stacks (e.g., two cell stacks in the example shown) that are partially sacrificed to form a 3D DRAM cell. It can be appreciated that this method forms a two-layered 3D DRAM cell. In other examples, the cell stack of the repeating film stack can form additional layers of 3D DRAM cells. Also, one example of using a cell stack in a film stack can form a layer of 3D DRAM cells.
The film stack includes a plurality of cell stacks, wherein the cell stacks include a sacrificial layer 202 and a dielectric layer 204. The unit stack of the film stack is, or consists of, the sacrificial layer 202 and the dielectric layer 204 on the sacrificial layer 202. Two examples of this cell stack are stacked on the substrate 100 in fig. 13. The sacrificial layers 202 can each be the same material, and the dielectric layers 204 can each be the same dielectric material that is different from the material of the sacrificial layers 202 and has an etch selectivity between the materials of the sacrificial layers. It will be appreciated that the materials of the different layers generally allow for selective etching of the target layer during processing. The film stack is used as a mold for forming the DRAM cell. In some examples, sacrificial layer 202 is silicon, silicon germanium, doped silicon oxide, borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), or silicon nitride, and dielectric layer 204 is silicon oxide. Each of the sacrificial layer 202 and the dielectric layer 204 can be deposited by any suitable deposition technique, such as CVD, PVD, and the like.
In fig. 14, an opening 206 is formed through the film stack (e.g., through the sacrificial layer 202 and the dielectric layer 204). The opening 206 can be formed by using an anisotropic etch (such as RIE or the like).
In fig. 15, dielectric layer 204 is etched back from opening 206 to form lateral recess 208 from opening 206. The etch-back process can be any suitable isotropic etch that selectively etches the dielectric layer 204. For example, when the dielectric layer 204 is silicon oxide, the dielectric layer 204 can be etched using a hydrofluoric acid based process (e.g., a wet dHF or dry HF process).
In fig. 16, a semiconductor layer 210 is formed to fill the lateral recess 208. Semiconductor layer 210 can be formed using a conformal deposition (such as ALD) that conformally deposits the material of semiconductor layer 210 along the surfaces defining opening 206 and lateral recess 208. The material of semiconductor layer 210 can be removed from between the sidewalls of sacrificial layer 202 defining opening 206 using an anisotropic etch. Semiconductor layer 210 can be any semiconductor material. In some examples, the semiconductor layer 210 is silicon (e.g., may be amorphous or polycrystalline, which may be p-doped) or InGaZnO.
In fig. 17, sacrificial layer 202 is etched back from opening 206 to form lateral recess 212 from opening 206. In some examples, sacrificial layer 202 is etched back to or beyond the corresponding vertical sidewalls of semiconductor layer 210 away from opening 206. The etch-back process can be any suitable isotropic etch that selectively etches the sacrificial layer 202. For example, when the sacrificial layer 202 is silicon nitride, the sacrificial layer 202 can be etched back using a hot phosphoric acid etching process.
Fig. 18 depicts a conformal sacrificial material 214 and a dielectric fill material 216. The conformal sacrificial material 214 can be formed by using a conformal deposition (such as ALD) that conformally deposits the material of the conformal sacrificial material 214 along surfaces defining the openings 206 and the lateral recesses 212 (e.g., the vertical sidewalls of the sacrificial layer 202 and the exposed surfaces of the semiconductor layer 210). The dielectric fill material 216 can be deposited on the conformally deposited material of the conformal sacrificial material 214 by any suitable deposition (such as by ALD, FCV, etc.) to fill the openings 206 and the remaining unfilled portions of the lateral recesses 212. An anisotropic etch can be used to remove material of the conformal sacrificial material 214 and the dielectric fill material 216 from between sidewalls of the semiconductor layer 210, such as defining the opening 206. The conformal sacrificial material 214 can be any sacrificial material, such as a sacrificial dielectric material, and the dielectric fill material 216 can be any dielectric material. In some examples, the conformal sacrificial material 214 is silicon nitride and the dielectric fill material 216 is silicon oxide.
In fig. 19, lateral portions of the conformal sacrificial material 214 are etched back from the opening 206 to form lateral recesses 218 from the opening 206. The dielectric fill material 216 formed on the respective conformal sacrificial material 214 can remain vertically disposed between the lateral recesses 218 formed by etching back the respective conformal sacrificial material 214. The etch-back process can be any suitable isotropic etch that selectively etches the conformal sacrificial material 214. For example, when the conformal sacrificial material 214 is silicon nitride, a hot phosphoric acid etch process can be used to etch back the conformal sacrificial material 214.
Fig. 20 shows a gate dielectric layer 220, a gate blocking/adjusting layer 222, a gate electrode fill material 224, and a dielectric fill material 226. A gate dielectric layer 220 is formed on the surface of the corresponding semiconductor layer 210 exposed by the opening 206 and the lateral recess 218. Gate dielectric layer 220 can be any suitable dielectric material formed by any suitable process. In some examples, gate dielectric layer 220 is an oxide formed by an oxidation process (e.g., by oxidizing an exposed surface of semiconductor layer 210). In some examples, the gate dielectric layer 220 can be another material formed by a conformal deposition process (such as ALD).
Then, a gate blocking/adjusting layer 222 is formed conformally along the surface of the lateral recess 218, and a gate electrode filling material 224 is formed on the gate blocking/adjusting layer 222. In some examples, the gate blocking/adjustment layer 222 is formed using a conformal deposition process (such as ALD). The conformal deposition process can form a conformal layer on surfaces defining the openings 206 and the lateral recesses 218 (e.g., including the gate dielectric layer 220). The conductive material of gate electrode fill material 224 can then be deposited over the conformal layer by any suitable deposition process. A node separation process is performed to remove some of the conductive material of the gate electrode fill material 224 and some of the conformal layer of the gate blocking/adjusting layer 222 to form the gate blocking/adjusting layer 222 and the gate electrode fill material 224 in the respective lateral recesses 208. The node separation process can include: an anisotropic etch (such as RIE) is performed followed by an isotropic etch selective to the material of the gate blocking/adjustment layer 222 and the gate electrode fill material 224. The anisotropic etch may remove conductive material such as the conformal layer of gate blocking/adjusting layer 222 and gate electrode fill material 224 between the semiconductor layer 210 and the vertical sidewall surfaces of dielectric fill material 216 defining opening 206. The isotropic etch laterally recesses the gate electrode fill material 224 and the gate blocking/adjusting layer 222 to have a plurality of vertical sidewalls that are offset from the vertical surfaces of the semiconductor layer 210 and the dielectric fill material 216 that define the opening 206. In some examples, the gate blocking/tuning layer 222 can be any suitable diffusion blocking material and/or can be any work function tuning material to tune the threshold voltage of the transistor, such as TiN or the like. In some examples, the gate electrode fill material 224 can be any conductive material, such as a metal, for example tungsten.
Dielectric fill material 226 is then formed in the lateral recess 208 and the remaining unfilled portions of the opening 206. The dielectric fill material 226 can be any suitable dielectric material deposited by any suitable deposition process. In some examples, the dielectric fill material 226 is an oxide deposited by a conformal deposition (such as ALD) or a flowable deposition process (such as FCVD).
In fig. 21, an opening 228 is formed through the film stack (e.g., through the sacrificial layer 202 and the dielectric layer 204). It will be appreciated that each opening 228 is used for the formation of a capacitor that will be electrically connected to a corresponding transistor of which the gate electrode fill material 224 and the gate blocking/adjustment layer 222 are a part. Each opening 228 is disposed a lateral distance from the corresponding gate electrode fill material 224 and gate blocking/adjustment layer 222, with the corresponding gate electrode fill material 224 and gate blocking/adjustment layer 222 being laterally disposed between the corresponding opening 228 and where the opening 206 is formed (e.g., filled with dielectric fill material 226). The opening 228 can be formed by using anisotropic etching (e.g., RIE, etc.).
In fig. 22, the sacrificial layer 202 is etched back from the respective openings 228 to form lateral recesses 230 from the respective openings 228. In some examples, the sacrificial layer 202 is removed by an etch back process. In some examples, such as that depicted, the etchback process can also remove the conformal sacrificial material 214, such as when the sacrificial layer 202 and the conformal sacrificial material 214 are the same material. The etch-back process can be any suitable isotropic etch that selectively etches the sacrificial layer 202. For example, when the sacrificial layer 202 is silicon nitride, the sacrificial layer 202, and possibly the conformal sacrificial material 214, can be etched back using a hot phosphoric acid etch process.
Figure 23 illustrates conformal dielectric material 232 and dielectric fill material 234. The conformal dielectric material 232 can be formed by using a conformal deposition (such as ALD) that conformally deposits material of the conformal dielectric material 232 along surfaces defining the openings 228 and the lateral recesses 230 (e.g., exposed surfaces of the dielectric layer 204, the dielectric fill material 216, and the gate blocking/adjustment layer 222). Dielectric fill material 234 can be deposited on the conformally deposited material of conformal dielectric material 232 by any suitable deposition (e.g., by ALD, FCV, etc.) to fill the openings 228 and the remaining unfilled portions of lateral recesses 230. The material of the conformal dielectric material 232 and the dielectric fill material 234 can be removed from between sidewalls of the dielectric layer 204, such as defining the openings 228, using an anisotropic etch. The conformal dielectric material 232 and dielectric fill material 234 can be any dielectric material as described below: can be selectively etched with respect to each other (e.g., the material of the conformal dielectric material 232 is different from the material of the dielectric fill material 234). In some examples, the conformal dielectric material 232 is silicon nitride and the dielectric fill material 234 is silicon oxide.
In fig. 24, dielectric layer 204 is etched back from opening 228 to the corresponding semiconductor layer 210, and lateral recess 236 is formed from opening 228. The etch-back process may be any suitable isotropic etch that selectively etches the dielectric layer 204. For example, when the dielectric layer 204 is silicon oxide, a hydrofluoric acid based process (e.g., a wet dHF or dry HF process) may be used to etch the dielectric layer 204.
At the corresponding lateral recess 236, the semiconductor layer 210 is doped at the vertical sidewall surface of the semiconductor layer 210 to form a source region 238. The source region 238 can be doped with an n-type dopant. The doping can be performed by using a gas phase dopant and/or a plasma assisted doping process.
In fig. 25, lateral recess 236 is expanded to form an enlarged lateral recess 240. The expansion can include an isotropic etch that selectively etches the conformal dielectric material 232. The isotropic etching can be a wet or dry process. In some examples where conformal dielectric material 232 is silicon nitride, conformal dielectric material 232 can be etched using a hot phosphoric acid etching process or a dry plasma etching process.
Fig. 26 shows the formation of a capacitor in an enlarged lateral recess 240. Each capacitor includes an outer plate 130, a capacitor dielectric layer 132, and an inner plate 134, as described above with respect to fig. 11.
In fig. 27, a drain region 242, a barrier layer 140, and a conductive fill material 142 are formed. An opening is formed through dielectric fill material 226. The opening exposes the vertical sidewalls of the semiconductor layer 210. An etching process can be used to form the opening and expose the vertical sidewalls of the semiconductor layer 210. For example, the etching process can include anisotropic etching and/or isotropic etching. The gate dielectric layer 220 previously formed on the vertical sidewalls of the semiconductor layer 210 is removed by an etching process to expose the vertical sidewalls of the semiconductor layer 210.
Lateral portions of semiconductor layer 210 at the respective vertical sidewalls exposed by the openings are doped to form drain regions 242. Drain region 242 may be doped with an n-type dopant. The doping can be performed by using a gas phase dopant and/or a plasma assisted doping process. With the drain region 242 formed, a corresponding transistor is formed for the DRAM cell. For each DRAM cell, the transistor includes a source region 238 in the semiconductor layer 210, a drain region 242 in the semiconductor layer 210, a channel region in the semiconductor layer 210 between the source region 238 and the drain region 242, a first (e.g., top) gate structure disposed on the semiconductor layer 210 and aligned with respect to the channel region, and a second (e.g., bottom) gate structure disposed on the semiconductor layer 210 and aligned with respect to the channel region. Each of the first gate structure and the second gate structure includes a respective gate dielectric layer 220 and a respective gate electrode fill material 224.
Then, a barrier layer 140 and a conductive fill material 142 are formed in the opening, as described with respect to fig. 12. Barrier layer 140 and conductive fill material 142 generally form a contact that may be a bit line node of a DRAM cell. The contact is along a vertical axis about which the mirrored DRAM pair mirrors.
Fig. 28-40 are cross-sectional views of intermediate structures during a second method to form a 3D DRAM cell according to some examples of the present disclosure. The 3D DRAM cell formed according to the third method of fig. 28 to 40 can be as shown in fig. 3.
Referring to fig. 28, a film stack is deposited on a substrate 100. The film stack includes a plurality of cell stacks (e.g., two cell stacks in the example shown) that are partially sacrificed to form a 3D DRAM cell. It can be appreciated that this method forms a two-layered 3D DRAM cell. In other examples, the cell stack of the repeating film stack can form additional layers of 3D DRAM cells. Also, one example of using a cell stack in a film stack can form a layer of 3D DRAM cells.
The film stack includes a plurality of cell stacks, wherein the cell stacks include a sacrificial layer 302 and a semiconductor layer 304. The cell stack of the film stack is, or consists of, a sacrificial layer 302 and a semiconductor layer 304 on the sacrificial layer 302. Two examples of this cell stack are stacked on the substrate 100 in fig. 28. The sacrificial layers 302 can each be the same material, and the semiconductor layers 304 can each be the same material, which is different from the material of the sacrificial layers 302 and has an etch selectivity between the materials of the sacrificial layers 302. In general, it is clear that the materials of the different layers allow selective etching of the target layer during processing. The film stack is used as a mold for forming the DRAM cell. In some examples, the sacrificial layer 302 is silicon germanium, silicon oxide, doped silicon oxide, BPSG, (BSG), PSG, or silicon nitride, and the semiconductor layer 304 is silicon (e.g., amorphous, polycrystalline, or single crystal, which may be doped) or InGaZnO. In some specific examples, sacrificial layer 302 is amorphous or crystalline silicon germanium and semiconductor layer 304 is amorphous or crystalline silicon. Each of the sacrificial layer 302 and the semiconductor layer 304 can be deposited by any suitable deposition technique, such as CVD, PVD, and the like.
In some examples, the sacrificial layer 302 and the semiconductor layer 304 are semiconductor materials, and further, are epitaxial or crystalline (e.g., monocrystalline) semiconductor materials. In some examples, the film stack can be formed by: a sacrificial layer 302 is epitaxially grown on the substrate 100, a semiconductor layer 304 is epitaxially grown on the sacrificial layer, and the epitaxial growth of the sacrificial layer 302 and the semiconductor layer 304 is repeated to achieve the target number of layers in the film stack. Using an epitaxial or crystalline (e.g., single crystal) material such as silicon germanium as the sacrificial layer 302 can allow the sacrificial layer 302 and the semiconductor layer 304 to be deposited by epitaxial growth, which allows the semiconductor layer 304 (and as can be appreciated, the active regions including the source/drain regions and the channel regions of the transistor) to be crystalline (e.g., single crystal). In some specific examples, the sacrificial layer 302 is epitaxial or crystalline (e.g., monocrystalline) silicon germanium and the semiconductor layer 304 is epitaxial or crystalline (e.g., monocrystalline) silicon.
In fig. 29, an opening 306 is formed through the film stack (e.g., through the sacrificial layer 302 and the semiconductor layer 304). The opening 306 can be formed by using an anisotropic etch (e.g., RIE, etc.).
In fig. 30, sacrificial layer 302 is etched back from opening 306 to form lateral recess 308 from opening 306. The etch-back process can be any suitable isotropic for selectively etching the sacrificial layer 302 And etching in the same polarity. For example, when the sacrificial layer 302 is silicon germanium, hydrofluoric acid (HF), hydrogen peroxide (H 2 O 2 ) And acetic acid (CH) 3 COOH) at 1:2:3 (HF: H) 2 O 2 :CH 3 COOH) etches the sacrificial layer 302.
Fig. 31 shows conformal sacrificial material 310 and dielectric fill material 312. Conformal sacrificial material 310 can be formed by using a conformal deposition (such as ALD) that conformally deposits material of conformal sacrificial material 310 along surfaces defining opening 306 and lateral recess 308 (e.g., vertical sidewalls of sacrificial layer 302 and exposed surfaces of semiconductor layer 304). Dielectric fill material 312 can be deposited on the conformally deposited material of conformal sacrificial material 310 by any suitable deposition (such as by ALD, FCV, etc.) to fill the openings 306 and the remaining unfilled portions of lateral recesses 308. An anisotropic etch can be used to remove material of the conformal sacrificial material 310 and the dielectric fill material 312 from between sidewalls of the semiconductor layer 304, such as defining the opening 306. Conformal sacrificial material 310 can be any sacrificial material, such as a sacrificial dielectric material, and dielectric fill material 312 can be any dielectric material. In some examples, conformal sacrificial material 310 is silicon nitride and dielectric fill material 312 is silicon oxide.
In fig. 32, lateral portions of conformal sacrificial material 310 are etched back from openings 306 to form lateral recesses 314 from openings 306. The dielectric fill material 312 formed on the respective conformal sacrificial material 310 can remain vertically disposed between the lateral recesses 314 formed by etching back the respective conformal sacrificial material 310. The etch-back process can be any suitable isotropic etch that selectively etches the conformal sacrificial material 310. For example, when conformal sacrificial material 310 is silicon nitride, a hot phosphoric acid etch process may be used to etch back conformal sacrificial material 310.
Fig. 33 illustrates a gate dielectric layer 220, a gate blocking/adjusting layer 222, a gate electrode fill material 224, and a dielectric fill material 226. The gate dielectric layer 220, the gate blocking/adjusting layer 222, and the gate electrode fill material 224 are formed in the lateral recesses 314 as described above with respect to fig. 20, and the dielectric fill material 226 is formed in the openings 306 as described above with respect to fig. 20.
In fig. 34, an opening 315 is formed through the film stack (e.g., through the sacrificial layer 302 and the semiconductor layer 304), as described above with respect to fig. 21. It will be appreciated that each opening 315 is used in the formation of a capacitor that will be electrically connected to a corresponding transistor of which the gate electrode fill material 224 and the gate blocking/adjustment layer 222 are a part. Each opening 315 is disposed a lateral distance from the corresponding gate electrode fill material 224 and gate blocking/adjustment layer 222, with the corresponding gate electrode fill material 224 and gate blocking/adjustment layer 222 being laterally disposed between the corresponding opening 315 and the formation of the opening 206 (e.g., where the formation of the opening 206 is filled with dielectric fill material 226).
In fig. 35, the sacrificial layer 302 is etched back from the corresponding opening 315, and lateral recesses 316 are formed from the corresponding opening 315. In some examples, sacrificial layer 302 is removed by an etch back process. In some examples, such as depicted, the back-etching process can also remove the conformal sacrificial material 310, such as when the sacrificial layer 302 and the conformal sacrificial material 310 are the same material. The etch-back process can be any suitable isotropic etch that selectively etches the sacrificial layer 302. For example, when the sacrificial layer 302 is silicon germanium, HF, H can be used 2 O 2 And CH (CH) 3 The ratio of COOH was 1:2:3 (HF: H) 2 O 2 :CH 3 COOH) to etch back the sacrificial layer 302.
Fig. 36 illustrates conformal dielectric material 232 and dielectric fill material 234 formed in lateral recess 316. The conformal dielectric material 232 and dielectric fill material 234 can be formed as described above with respect to fig. 23.
In fig. 37, semiconductor layer 304 is etched back from opening 315 to form lateral recess 318 from opening 315. The etch-back process can be any suitable isotropic etch that selectively etches the semiconductor layer 304. For example, when the semiconductor layer 304 is silicon, a TMAH etching process or dry plasma isotropic etching can be used to etch back the semiconductor layer 304.
At the respective lateral recesses 318, the semiconductor layer 304 is doped at the vertical sidewall surfaces of the semiconductor layer 304 to form source regions 238, as described with respect to fig. 24.
In fig. 38, lateral recess 318 is expanded to form an enlarged lateral recess 240, as described with respect to fig. 25. Fig. 39 shows the formation of a capacitor in an enlarged lateral recess 240. Each capacitor includes an outer plate 130, a capacitor dielectric layer 132, and an inner plate 134, as described above with respect to fig. 11. In fig. 40, a drain region 242, a barrier layer 140, and a conductive fill material 142 are formed, as described with respect to fig. 27.
With the drain region 242 formed, a corresponding transistor is formed for the DRAM cell. For each DRAM cell, the transistor includes a source region 238 in the semiconductor layer 304, a drain region 242 in the semiconductor layer 304, a channel region in the semiconductor layer 304 between the source region 238 and the drain region 242, a first (e.g., top) gate structure disposed on the semiconductor layer 304 and aligned with respect to the channel region, and a second (e.g., bottom) gate structure disposed on the semiconductor layer 304 and aligned with respect to the channel region. Each of the first and second gate structures includes a gate dielectric layer 220 and a gate electrode fill material 224. Barrier layer 140 and conductive fill material 142 generally form a contact that may be a bit line node of a DRAM cell. The contact is along a vertical axis about which the mirrored DRAM pair mirrors.
While the foregoing is directed to various examples of the present disclosure, other and further examples may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims (20)

1. A method for semiconductor processing, the method comprising:
forming a film stack on a substrate, the film stack comprising a plurality of cell stacks, each cell stack having a first dielectric layer, a semiconductor layer disposed on the first dielectric layer, and a second dielectric layer disposed on the semiconductor layer;
forming a first opening through the film stack;
etching back the second dielectric layer from the first opening to form a first lateral recess;
forming a gate structure in the first lateral recess and disposed on a portion of the semiconductor layer;
forming a second opening through the film stack, the second opening being laterally disposed from where the first opening is formed, the gate structure being laterally disposed between the second opening and where the first opening is formed;
etching back the portion of the semiconductor layer from the second opening to form a second lateral recess; and
A capacitor is formed in the region provided with the second lateral recess, the capacitor contacting the portion of the semiconductor layer.
2. The method of claim 1, further comprising:
expanding the second lateral recess, comprising: at least some of the first dielectric layer below the second lateral recess and at least some of the second dielectric layer above the second lateral recess are removed, the capacitor being formed in the extended second lateral recess.
3. The method of claim 2, wherein forming the capacitor comprises:
conformally depositing a first plate along a plurality of surfaces of the extended second lateral recess;
conformally depositing a capacitor dielectric layer along the first plate; and
a second plate is deposited over the capacitor dielectric layer.
4. The method of claim 1, further comprising forming source/drain regions in the portion of the semiconductor layer, comprising: the portion of the semiconductor layer is doped by the second lateral recess, wherein a plate of the capacitor forms the source/drain region in contact with the portion of the semiconductor layer.
5. The method of claim 1, further comprising:
Forming source/drain regions in the portion of the semiconductor layer, comprising: doping the portion of the semiconductor layer; and
contacts are formed that extend through the film stack, the contacts contacting the source/drain regions.
6. A method for semiconductor processing, the method comprising:
forming a film stack on a substrate, the film stack comprising a plurality of cell stacks, each cell stack having a first layer and a second layer disposed on the first layer;
forming a first opening through the film stack;
etching back the first layer from the first opening to form a first lateral recess;
forming a first conformal layer in the first lateral recess;
forming a first filler material on the first conformal layer and in the first lateral recess;
etching back the first conformal layer from the first opening to form a second lateral recess;
forming a gate structure in the second lateral recess and disposed on and below a semiconductor layer, the semiconductor layer being horizontally aligned with the second layer;
forming a second opening through the film stack, the second opening being laterally disposed from where the first opening is formed, the gate structure being laterally disposed between the second opening and where the first opening is formed;
Etching back the second layer from the second opening to form a third lateral recess to the semiconductor layer; and
a capacitor is formed in a region provided with the third lateral recess, the capacitor contacting the semiconductor layer.
7. The method of claim 6, further comprising:
etching back the second layer from the first opening to form a fourth lateral recess; and
the semiconductor layer is formed in the fourth lateral recess.
8. The method of claim 6, wherein the second layer is a semiconductor material, the semiconductor layer being a portion of the second layer.
9. The method of claim 6, wherein the first layer is a first dielectric material and the second layer is a second dielectric material, the first and second dielectric materials being selectively removable relative to each other.
10. The method of claim 6, wherein the first layer is a first dielectric material and the second layer is a second dielectric material different from the first dielectric material, each of the first dielectric material and the second dielectric material selected from the group consisting of: silicon nitride, silicon oxide, doped silicon oxide, borophosphosilicate glass (BPSG), and phosphosilicate glass (PSG).
11. The method of claim 6, wherein the first layer is a first semiconductor material and the second layer is a second semiconductor material different from the first semiconductor material.
12. The method of claim 11, wherein the first semiconductor material and the second semiconductor material are amorphous.
13. The method of claim 11, wherein the first semiconductor material and the second semiconductor material are epitaxial or monocrystalline.
14. The method of claim 6, wherein forming the film stack comprises:
epitaxially growing the first layer; and
the second layer is epitaxially grown on the first layer.
15. The method of claim 6, wherein the first layer is silicon germanium and the second layer is silicon.
16. The method of claim 6, wherein the first layer is epitaxial silicon germanium and the second layer is epitaxial silicon.
17. The method of claim 6, wherein the first layer is amorphous silicon germanium and the second layer is amorphous silicon.
18. The method of claim 6, further comprising:
etching back the first layer from the second opening to form a fourth lateral recess;
Forming a second conformal layer in the fourth lateral recess; and
a second fill material is formed on the second conformal layer and in the fourth lateral recess.
19. The method of claim 18, further comprising expanding the third lateral recess, comprising: at least some of the second conformal layer is removed, the capacitor is formed in the extended third lateral recess.
20. A method for semiconductor processing, the method comprising:
forming a film stack on a substrate, the film stack comprising at least five layers, each of the at least five layers being formed of a material selected from the group of a plurality of materials, the plurality of materials comprising no more than three different materials; and
forming a vertical stack of mirrored DRAM pairs on the substrate using the film stack as a mold, each mirrored DRAM pair of the vertical stack of mirrored DRAM pairs comprising:
a contact;
a first transistor including a first gate structure, a first source/drain region, and a second source/drain region, the first source/drain region contacting the contact;
a second transistor comprising a second gate structure, a third source/drain region and a fourth source/drain region, the third source/drain region contacting the contact, the second transistor mirroring the first transistor around the contact;
A first capacitor having a first outer plate, a first capacitor dielectric layer, and a first inner plate, the first outer plate contacting the second source/drain region; and
a second capacitor having a second outer plate, a second capacitor dielectric layer, and a second inner plate, the second outer plate contacting the fourth source/drain region.
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