CN116527039A - Four-order pulse amplitude modulation baud rate phase discrimination method, CDR circuit and receiver - Google Patents

Four-order pulse amplitude modulation baud rate phase discrimination method, CDR circuit and receiver Download PDF

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CN116527039A
CN116527039A CN202310319344.8A CN202310319344A CN116527039A CN 116527039 A CN116527039 A CN 116527039A CN 202310319344 A CN202310319344 A CN 202310319344A CN 116527039 A CN116527039 A CN 116527039A
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error type
phase
phase discrimination
sampling data
discrimination result
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Inventor
刘勇聪
吕方旭
王强
欧洋
许超龙
赖明澈
庞征斌
罗章
齐星云
徐佳庆
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National University of Defense Technology
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National University of Defense Technology
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/16—Circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0002—Serial port, e.g. RS232C
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H03M1/1245—Details of sampling arrangements or methods
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/50—Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate

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  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

The invention discloses a phase discrimination method of a fourth-order pulse amplitude modulation baud rate, a CDR circuit and a receiver, wherein the phase discrimination method comprises the following steps: determining slope information from 3 adjacent sampling data D (n-1), D (n), and D (n+1); determining 3 adjacent error types E (n-1), E (n) and E (n+1), and if E (n) is an effective error type, obtaining a phase discrimination result of n-th sampling data D (n) according to E (n) and combined inclination information; otherwise, the phase discrimination result of the nth sampling data D (n) is obtained according to E (n-1) or E (n+1) combined slope information which is the effective error type. The invention can obtain phase information for all monotone changes, realize BRPD high gain, and enable CDR circuit to have higher conversion density and lower jitter, and be easily realized by digital circuit.

Description

Four-order pulse amplitude modulation baud rate phase discrimination method, CDR circuit and receiver
Technical Field
The invention relates to the field of high-speed serial data communication, in particular to a four-order pulse amplitude modulation (PAM 4) baud rate phase demodulation method, a CDR circuit and a receiver.
Background
Serializer/Deserializer (SerDes) is one of the mainstream technologies of high-speed serial data communication at present, and is widely applied to the application fields of ethernet, optical fiber communication, wireless communication and the like due to the characteristics of low cost, high speed, strong anti-interference capability and the like. The clock data recovery circuit (Clock and Data Recovery, CDR) is an important component in SerDes, whose main function is to extract clock information from the input data with amplitude noise and phase noise, and then retime the data. The CDRs can be divided into baud rate sampled CDRs and oversampled CDRs according to sampling frequency division. Baud rate sampling CDR means that the CDR sampling frequency is equal to the baud rate of the input data. It calculates the phase error of the local clock and the input data by subsequent digital processing. An oversampled CDR refers to a number of samples within one UI being two or more.
Compared with the traditional oversampling technology, the baud rate phase discriminator is quite suitable for a high-speed CDR circuit based on an ADC structure because only one sampling clock is needed for each unit interval and only half of the sampling clock rate is needed. In the structure of the CDR circuit, the gain (BRPD gain) of the fourth-order pulse amplitude modulation baud rate phase discriminator (PAM 4 BRPD) is critical to the PAM4 clock recovery loop, and the performance of the PAM4 clock recovery loop is greatly weakened due to insufficient BRPD gain. However, for the existing BRPD at present, there are mainly two problems: (1) the gain is generally very small; (2) the lack of linearized modeling of PAM4BRPD gain results in a lack of visual analysis in the design of key parameters of the clock recovery loop. Aiming at the 2 problems, how to effectively improve the gain of the PAM4BRPD and establish a PAM4BRPD gain parameter model become key technical problems to be solved urgently.
Disclosure of Invention
The invention aims to solve the technical problems: aiming at the problems in the prior art, the invention provides a four-order pulse amplitude modulation baud rate phase discrimination method, a CDR circuit and a receiver, which can obtain phase information for all monotone changes, realize BRPD high gain, enable the CDR circuit to have higher conversion density and lower jitter, and be easily realized by a digital circuit.
In order to solve the technical problems, the invention adopts the following technical scheme:
a fourth order pulse amplitude modulation baud rate phase discrimination method, comprising:
s101, determining inclination information according to 3 adjacent sampling data D (n-1), D (n) and D (n+1);
s102, determining 3 adjacent error types E (n-1), E (n) and E (n+1) according to a sampling point area of sampling data, and obtaining a phase discrimination result of nth sampling data D (n) according to E (n) and combined inclination information if E (n) is an effective error type; if E (n) is an invalid error type and E (n-1) or E (n+1) is an effective error type, the phase discrimination result of the nth sampling data D (n) is obtained according to E (n-1) or E (n+1) combined with the inclination information which is the effective error type.
Optionally, in step S102, when determining 3 adjacent error types E (n-1), E (n), and E (n+1) according to the sampling point area of the sampled data, the sampling point area is divided into I-VII areas continuously distributed according to the order from small to large according to the voltage, if the sampling point area of the sampled data is located in IV area, the corresponding error type is the first error type, if the sampling point area of the sampled data is located in I area, VII area, III area, or V area, the corresponding error type is the second error type, and if the sampling point area of the sampled data is located in II area or VI area, the corresponding error type is the third error type, the effective error type refers to the first error type and the third error type, and the ineffective error type refers to the second error type.
Optionally, the coding of the error types includes three of 00, 11 and 01, wherein 00 represents a first error type, 11 represents a third error type and 01 represents a second error type.
Optionally, the slope information determined in step S102 is composed of a combination of the size comparison result of both the sampling data D (n-1), D (n) and the size comparison result of both the D (n), D (n+1).
Optionally, the step S102 of obtaining the phase discrimination result for phase advance or retard according to E (n) and the combined slope information includes: when the determined inclination information is D (n-1) < D (n) < D (n+1) or D (n-1) < D (n) < D (n+1), and the n-th error type E (n) is 00, if the value of the n-th sampling data D (n) is +3, the phase discrimination result is no information, if the value of the n-th sampling data D (n) is +1, the phase discrimination result is advanced, if the value of the n-th sampling data D (n) is-1, the phase discrimination result is lagged, and if the value of the n-th sampling data D (n) is-3, the phase discrimination result is no information; when the determined inclination information is D (n-1) < D (n) < D (n+1) or D (n-1) < D (n) < D (n+1), and the n-th error type E (n) is 11, if the value of the n-th sampling data D (n) is +3, the phase discrimination result is advanced, if the value of the n-th sampling data D (n) is +1, the phase discrimination result is retarded, if the value of the n-th sampling data D (n) is-1, the phase discrimination result is advanced, and if the value of the n-th sampling data D (n) is-3, the phase discrimination result is retarded; when the determined inclination information is D (n-1) not less than D (n) > D (n+1) or D (n-1) not less than D (n) > D (n+1), and the n-th error type E (n) is 00, if the value of the n-th sampling data D (n) is +3, the phase discrimination result is no information, if the value of the n-th sampling data D (n) is +1, the phase discrimination result is hysteresis, if the value of the n-th sampling data D (n) is-1, the phase discrimination result is advanced, and if the value of the n-th sampling data D (n) is-3, the phase discrimination result is no information; when the determined inclination information is D (n-1) > D (n) > D (n+1) or D (n-1) > D (n) > D (n+1), and the n-th error type E (n) is 11, if the value of the n-th sampling data D (n) is +3, the phase discrimination result is lagged, if the value of the n-th sampling data D (n) is +1, the phase discrimination result is advanced, if the value of the n-th sampling data D (n) is-1, the phase discrimination result is lagged, and if the value of the n-th sampling data D (n) is-3, the phase discrimination result is advanced.
Optionally, the step S102 of obtaining the phase discrimination result of the nth sampling data D (n) according to the E (n-1) or E (n+1) combined slope information which is the effective error type includes: when the determined inclination information is D (n-1) < D (n). Ltoreq.D (n+1) and the n-th error type E (n) is 01, if the n-1-th error type E (n-1) is not 01, the value of the n-th sampling data D (n) is +1, and the phase discrimination result is hysteresis; when the determined inclination information is D (n-1). Ltoreq.D (n) < D (n+1) and the n-th error type E (n) is 01, if the n+1th error type E (n+1) is not 01, the value of the n-th sampling data D (n) is +1, and the phase discrimination result is advanced; when the determined inclination information is D (n-1) > D (n) > D (n+1) and the n-th error type E (n) is 01, if the n+1th error type E (n+1) is not 01, the value of the n-th sampling data D (n) is +1, and the phase discrimination result is advanced; when the determined inclination information is D (n-1) > D (n) > D (n+1) and the n-th error type E (n) is 01, if the n-1-th error type E (n-1) is not 01, the value of the n-th sampling data D (n) is +1, and the phase discrimination result is hysteresis.
In addition, the invention also provides a CDR circuit for the high-speed serial interface, which comprises an ADC sampler, a feedforward equalizer FFE, a baud rate phase discriminator, a voter, a low-pass digital filter and a phase interpolator, wherein the ADC sampler, the feedforward equalizer FFE, the baud rate phase discriminator, the voter and the low-pass digital filter are sequentially connected, the phase interpolator is used for carrying out phase calibration on an externally input PPL clock according to phase information output by the low-pass digital filter and then serving as a clock signal of the ADC sampler, and the baud rate phase discriminator is programmed or configured to execute the four-order pulse amplitude modulation baud rate phase discrimination method.
Optionally, the low-pass digital filter is a 2-order low-pass digital filter.
Optionally, the feedforward equalizer FFE is a 4-tap feedforward equalizer FFE.
In addition, the invention also provides a SerDes receiver, which comprises an analog front-end circuit AFE, a phase-locked loop PPL, a clock sampling data recovery circuit and a sampling data channel, wherein the clock sampling data recovery circuit is the CDR circuit for the high-speed serial interface, sampling data output by the analog front-end circuit AFE is sent to an ADC sampler in the CDR circuit, a PPL clock output by the phase-locked loop PPL is connected with an input end of a phase interpolator in the CDR circuit, the sampling data channel comprises a feedforward equalizer FFE and a decision feedback equalizer DFE which are sequentially connected, an output end of the ADC sampler is connected with an input end of the feedforward equalizer FFE in the sampling data channel, and an output end of the decision feedback equalizer DFE is used as a sampling data output end of the SerDes receiver.
Compared with the prior art, the invention has the following advantages:
1. the four-order pulse amplitude modulation baud rate phase discrimination method can obtain phase information for all monotone changes through 3 adjacent data and 3 error types, realize BRPD high gain of a four-order pulse amplitude modulation baud rate phase discriminator (PAM 4 BRPD), and enable a CDR circuit adopting the four-order pulse amplitude modulation baud rate phase discrimination method to have higher conversion density and lower jitter compared with the existing CDR circuit.
2. The phase discrimination method of the fourth-order pulse amplitude modulation baud rate is simple to realize and can be easily realized by a digital circuit.
Drawings
FIG. 1 is a schematic diagram of a basic flow of a method according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of error types and sampling regions in PAM4 eye patterns according to an embodiment of the present invention.
Fig. 3 shows phase detection waveforms and phase detection analysis when E (n) is an effective error type in an embodiment of the present invention.
Fig. 4 shows a phase detection analysis when E (n) is an invalid error type in the embodiment of the present invention.
Fig. 5 is a schematic diagram of smoothing phase discrimination characteristics by gaussian jitter according to an embodiment of the present invention.
FIG. 6 is a gain simulation curve of the Gaussian jitter phase-discrimination small phase difference added in the embodiment of the invention.
FIG. 7 is a schematic diagram of a SerDes receiver and CDR circuit according to an embodiment of the present invention.
FIG. 8 is a graph showing the results of performance simulation of a PAM4 baud rate CDR circuit according to an embodiment of the present invention.
Detailed Description
As shown in fig. 1, the fourth-order pulse amplitude modulation baud rate phase discrimination method of the present embodiment includes:
s101, determining inclination information according to 3 adjacent sampling data D (n-1), D (n) and D (n+1);
s102, determining 3 adjacent error types E (n-1), E (n) and E (n+1) according to a sampling point area of sampling data, and obtaining a phase discrimination result of nth sampling data D (n) according to E (n) and combined inclination information if E (n) is an effective error type; if E (n) is an invalid error type and E (n-1) or E (n+1) is an effective error type, the phase discrimination result of the nth sampling data D (n) is obtained according to E (n-1) or E (n+1) combined with the inclination information which is the effective error type.
Referring to fig. 2, in step S102 of the present embodiment, when determining 3 adjacent error types E (n-1), E (n), and E (n+1) according to the sampling point area of the sampled data, the sampling point area is divided into I-VII areas continuously distributed according to the order from small to large, the corresponding error type is the first error type if the sampling point area of the sampled data is located in IV area, the corresponding error type is the second error type if the sampling point area of the sampled data is located in I area, VII area, III area, or V area, the corresponding error type is the third error type if the sampling point area of the sampled data is located in II area or VI area, the effective error type is the first error type and the third error type, and the ineffective error type is the second error type. The four-order pulse amplitude modulated signal has four levels, "+3, +1, -1, and-3", each of which can be determined by 3 data decision voltages, namely, upper Eye (UE), middle Eye (ME), and Lower Eye (LE), as shown in fig. 2, in the middle of the three eyes, respectively. The high level and the low level inside each eye can also be represented by two levels, so 6 voltages shown on both sides of the 3 data decision voltages in fig. 2 represent the high level and the low level of the three eyes, respectively, including the upper eye high level (ue_u), the upper eye low level (ue_l), the middle eye high level (me_u), the middle eye low level (me_l), the lower eye high level (le_u), and the lower eye low level (le_l). In this embodiment, these 6 voltages are defined as error decision voltages, and thus, the vertical region of the eye diagram is divided into I to VII regions which are continuously distributed as shown in fig. 2. For ease of calculation, as an alternative implementation, the codes of the error types in this embodiment include three types of 00, 11, and 01, where 00 represents the first error type, 11 represents the third error type, 01 represents the second error type, 00 represents the sampling point in the IV region, 11 represents the sampling point in the II and VI regions, and 01 represents the sampling point in the I, III, V, and VII regions, as shown in fig. 2.
In this embodiment, the slope information determined in step S102 is composed of the combination of the size comparison results of both the sampled data D (n-1), D (n) and the size comparison results of both D (n), D (n+1), for example, "D (n-1) < D (n)" and "D (n). Ltoreq.D (n+1)" are combined to form "D (n-1) < D (n). Ltoreq.D (n+1)". When slope information is determined from 3 adjacent sampling data D (n-1), D (n), and D (n+1), the 3 adjacent signals have 64 kinds of variations in total, and can be classified into two types of monotone and non-monotone, wherein 32 kinds of monotone variations can be further classified into 3 types: pure monotonous, before single and after single. As shown in (a-1) and (a-2) in fig. 3, pure monotonous means that the comparison result of the magnitudes of both the sampling data D (n-1) and D (n) is the same as the comparison result of the magnitudes of both D (n) and D (n+1), for example, (a-1) is both upward (D (n-1) < D (n) and D (n) < D (n+1)), and (a-2) is both downward (D (n-1) > D (n) and D (n) > D (n+1)). As shown in (b-1) and (b-2) in fig. 3, the former monotonous means that the magnitudes of both the sampling data D (n-1) and D (n) are different, and the magnitudes of both D (n) and D (n+1) are the same, for example, (b-1) is both up-inclined (D (n-1) < D (n) and D (n) =d (n+1)), (b-2) is both down-inclined (D (n-1) > D (n) and D (n) =d (n+1)). As shown in (c-1) and (c-2) in fig. 3, the latter monotonous means that the sampled data D (n-1) and D (n) are the same in size, and D (n) and D (n+1) are different in size, for example, (c-1) is both up-inclined (D (n-1) =d (n) and D (n) > D (n+1)), (c-2) is both down-inclined (D (n-1) =d (n) and D (n) > D (n+1)). All of these 32 monotonic changes can be used to extract the phase information.
After the slope information is acquired in this embodiment, lead/lag phase information is generated by 3 error types and D (n). When E (n) is 00 or 11 (effective error type), the phase results can be obtained directly under different D (n) conditions when the sampling point is in the II, IV, or VI region, table 1 shows the phase result truth table when E (n) is the effective error type, for example, when three adjacent data are input of "-1, +1, +3", the slope information is monotonically rising, and if E (n) is 00, the local clock phase advances from the input data phase in combination with D (n) = +1. Whereas if E (n) is 11, the sampling point is in region VI, the local clock phase lags the input data phase.
Table 1: e (n) is the true table of the algorithm for the valid error type.
Specifically, referring to table 1, the phase discrimination result for phase lead or lag according to E (n) and the combined slope information in step S102 includes: when the determined inclination information is D (n-1) < D (n) < D (n+1) or D (n-1) < D (n) < D (n+1), and the n-th error type E (n) is 00, if the value of the n-th sampling data D (n) is +3, the phase discrimination result is no information, if the value of the n-th sampling data D (n) is +1, the phase discrimination result is advanced, if the value of the n-th sampling data D (n) is-1, the phase discrimination result is lagged, and if the value of the n-th sampling data D (n) is-3, the phase discrimination result is no information; when the determined inclination information is D (n-1) < D (n) < D (n+1) or D (n-1) < D (n) < D (n+1), and the n-th error type E (n) is 11, if the value of the n-th sampling data D (n) is +3, the phase discrimination result is advanced, if the value of the n-th sampling data D (n) is +1, the phase discrimination result is retarded, if the value of the n-th sampling data D (n) is-1, the phase discrimination result is advanced, and if the value of the n-th sampling data D (n) is-3, the phase discrimination result is retarded; when the determined inclination information is D (n-1) not less than D (n) > D (n+1) or D (n-1) not less than D (n) > D (n+1), and the n-th error type E (n) is 00, if the value of the n-th sampling data D (n) is +3, the phase discrimination result is no information, if the value of the n-th sampling data D (n) is +1, the phase discrimination result is hysteresis, if the value of the n-th sampling data D (n) is-1, the phase discrimination result is advanced, and if the value of the n-th sampling data D (n) is-3, the phase discrimination result is no information; when the determined inclination information is D (n-1) > D (n) > D (n+1) or D (n-1) > D (n) > D (n+1), and the n-th error type E (n) is 11, if the value of the n-th sampling data D (n) is +3, the phase discrimination result is lagged, if the value of the n-th sampling data D (n) is +1, the phase discrimination result is advanced, if the value of the n-th sampling data D (n) is-1, the phase discrimination result is lagged, and if the value of the n-th sampling data D (n) is-3, the phase discrimination result is advanced.
However, when E (n) is of the effective error type, this method still loses part of the phase information, as in (b-1) and (b-2) of FIG. 3, it can be seen from Table 1 that only the advance phase information can be extracted; similarly, in fig. 3 (c-1) and (c-2), only the retard phase information can be obtained. In order to further increase the gain of the fourth order pwm baud rate phase discrimination, the slope information and the 3 adjacent error types E (n-1), E (n), and E (n+1) are used to provide additional phase information when E (n) is not an effective error type. After the slope information is acquired, if the current sampling point is located in the area I, III, V or VII, the E (n) is indicated to be of an invalid error type, and if E (n-1) or E (n+1) is of an valid error type, the phase identification result can still be obtained. That is, when E (n) is an invalid error type, the algorithm will obtain the phase information through E (n-1) or E (n+1), as shown in FIG. 4. Table 2 is a truth table corresponding to the phase detection method.
SL[1:0] E(n) E(n-1) E(n+1) Information processing system
D(n-1)<D(n)≤D(n+1) 01 ≠01 X Hysteresis of
D(n-1)≤D(n)<D(n+1) 01 X ≠01 Advancing
D(n-1)≥D(n)>D(n+1) 01 X ≠01 Advancing
D(n-1)>D(n)≥D(n+1) 01 ≠01 X Hysteresis of
In table 2, "X" means that any value can be obtained. Specifically, referring to table 2, the phase discrimination result of the nth sampling data D (n) according to E (n-1) or E (n+1) combined with the slope information, which is the effective error type, in step S102 includes: when the determined inclination information is D (n-1) < D (n). Ltoreq.D (n+1) and the n-th error type E (n) is 01, if the n-1-th error type E (n-1) is not 01, the value of the n-th sampling data D (n) is +1, and the phase discrimination result is hysteresis; when the determined inclination information is D (n-1). Ltoreq.D (n) < D (n+1) and the n-th error type E (n) is 01, if the n+1th error type E (n+1) is not 01, the value of the n-th sampling data D (n) is +1, and the phase discrimination result is advanced; when the determined inclination information is D (n-1) > D (n) > D (n+1) and the n-th error type E (n) is 01, if the n+1th error type E (n+1) is not 01, the value of the n-th sampling data D (n) is +1, and the phase discrimination result is advanced; when the determined inclination information is D (n-1) > D (n) > D (n+1) and the n-th error type E (n) is 01, if the n-1-th error type E (n-1) is not 01, the value of the n-th sampling data D (n) is +1, and the phase discrimination result is hysteresis. It is noted that if E (n-1), E (n), and E (n+1) are all of the invalid error types, the sampling point is close to the optimal sampling point, and PAM4BRPD at this time does not generate phase information. For example, 3 adjacent data are input as "+1, +3", the slope information is monotonically increasing before, and E (n) is 01, if E (n-1) is not 01, the previous sampling point is not located in VI region, the local clock phase is behind the input data phase, and if E (n-1) is 01, the sampling point is located in V region, the optimal sampling point is approached, and the fourth-order pwm baud rate phase does not generate phase information.
In summary, the conventional phase discrimination of the fourth-order pulse amplitude modulation baud rate based on the Bang-Bang detection algorithm mainly determines the optimal sampling point of the input data through the intersection of the reference potential (ME), however, the method obviously reduces the gain of the phase discrimination of the fourth-order pulse amplitude modulation baud rate and the tracking bandwidth of the clock data recovery circuit CDR. In contrast, the fourth-order pulse amplitude modulation baud rate phase discrimination method in the present embodiment can obtain phase information for all monotone changes by 3 adjacent data and 3 error types, and the method can be easily implemented with digital circuits.
In order to accurately calculate the gain of the fourth-order pulse amplitude modulation baud rate phase discrimination and describe the characteristics of a clock data recovery circuit CRD loop, a fourth-order pulse amplitude modulation baud rate phase discrimination linear model is first proposed in the embodiment. Assuming that the random phase error (phase difference between the input data and the recovered clock) is a gaussian distribution with an average value of 0 and a standard deviation of σ, the input-inherent jitter smoothes the four-order pulse amplitude modulation baud rate phase-discriminating binary output characteristic, as shown in fig. 5. By combining the four-order pulse amplitude modulation baud rate phase discrimination flow, we use '1' to represent phase delay and '1' to represent phase advance, then add weights to positive and negative samples according to the occurrence probability, thus knowing that the four-order pulse amplitude modulation baud rate phase discrimination average output u is:
u＝(1) r (|φ)+(-1) r (|)，(1)
in the above, P r (|phi) is the lag phase probability density, P r (|) is the advance phase probability density and φ is the phase. In FIG. 5, φ is the average phase error between the input data and the recovered clock, 2 m Then this represents the drift bit bandwidth without phase information generated. In practice, since the drift bit bandwidth varies with different phase changes, we use the maximum drift bit bandwidth as an estimate. When the average phase error is phi, the drift bit bandwidth is 2 m The lag phase probability density is:
in the above, sigma is the standard deviation of Gaussian distribution, phi is the average phase error between the input data and the recovered clock m Then it represents half the drift bit bandwidth without phase information generation when the average phase error is phi and the drift bit bandwidth is 2 m The lead phase density function is:
substituting (2) and (3) into (1) can be deduced:
since equation (4) does not consider the detector density of the fourth-order pulse amplitude modulation baud rate phase discrimination (1/2), the gain based on gaussian jitter BRPD is 1/(2*u), and according to the existing research analysis results, the fourth-order pulse amplitude modulation baud rate phase discrimination gain is inversely proportional to the input jitter, and the higher the jitter, the lower the gain.
In order to verify the correctness of the phase discrimination linear model of the fourth-order pulse amplitude modulation baud rate, gaussian jitter is added to a recovered clock, the phase difference phi is scanned at an input end, the average output of the fourth-order pulse amplitude modulation baud rate discrimination phase variation along with different phi is measured and is shown as (b) in fig. 6, a comparison curve is generated through the phase discrimination linear model of the fourth-order pulse amplitude modulation baud rate, the tracks of the two curves are almost completely consistent, and therefore the correctness of the phase discrimination linear model of the fourth-order pulse amplitude modulation baud rate is verified. The phase discrimination gain of the fourth-order pulse amplitude modulation wave rate can be calculated by the measured inclination information or the inclination information in the linear model. The (a) of FIG. 6 depicts 3 average outputs obtained by the 3 four-order pulse amplitude modulation baud rate phase discrimination algorithm under different phi, and according to the simulation results, the four-order pulse amplitude modulation baud rate phase discrimination method of this embodiment has a higher gain than the existing method [3] (N.Qi et al., "A51Gb/s,320mW,PAM4 CDR with baud-rate sampling for high-speed optical interconnects," in 2017IEEE Asian Solid-State Circuits Conference (A-SSCC), seoul, korea (South), nov.2017, pp.89-92.) and [9] (Z.Zhang, G.Zhu, C.Wang, L.Wang, and C.P.Yue., "A32-Gb/s 0.46-pJ/bit PAM4CDR Using a Quarter-Rate Linear Phase Detector and a Self-Biased PLL-Based Multiphase Clock Generator," IEEE Journal of Solid-State Circuits, vol.55, no.10, pp.34-2746,2020.).
As shown in fig. 7, the present embodiment further provides a CDR circuit for a high-speed serial interface, which includes an ADC sampler, a feedforward equalizer FFE, a baud rate phase discriminator (PAM 4 BRPD), a voter, a low-pass digital filter (low-pass digital filter, LPDF), and a phase interpolator (phase interpolator, PI), wherein the ADC sampler, the feedforward equalizer FFE, the baud rate phase discriminator, the voter, and the low-pass digital filter are sequentially connected, the phase interpolator is configured to perform phase calibration on an externally input PPL clock according to phase information output by the low-pass digital filter, and then to be used as a clock signal of the ADC sampler, and the baud rate phase discriminator is programmed or configured to perform the fourth-order pulse amplitude modulation baud rate phase discrimination method described in the present time. As an alternative implementation manner, in this embodiment, the low-pass digital filter is a 2-order low-pass digital filter, and the feedforward equalizer FFE is a 4-tap feedforward equalizer FFE. The operation process of the CDR circuit is as follows: (1) serial input data is first ADC sampled (analog to digital adopted) by an 8-bit ADC sampler and converted into parallel data. (2) Equalization is performed through a feedforward equalizer FFE to obtain equalized data so as to reduce inter-path crosstalk. (3) The equalized data is compared to a decision voltage in a baud rate phase detector (PAM 4 BRPD) to obtain a lead/lag phase decision result. (4) The phase decision result passes through a voter, a low-pass digital filter and a phase interpolator, and the ADC clock phase is calibrated by the CDR so as to ensure the accuracy of sampling. It should be noted that the improvement of the CDR circuit in this embodiment is only that the baud rate phase detector (PAM 4 BRPD) is programmed or configured to perform the fourth-order pulse amplitude modulation baud rate phase detection method described earlier.
As shown in fig. 7, this embodiment further provides a SerDes receiver, including an analog front-end circuit AFE, a phase-locked loop PPL, a clock sampling data recovery circuit and a sampling data channel, where the clock sampling data recovery circuit is the CDR circuit for the high-speed serial interface, the sampling data output by the analog front-end circuit AFE is sent to an ADC sampler in the CDR circuit, the PPL clock output by the phase-locked loop PPL is connected to an input end of a phase interpolator in the CDR circuit, the sampling data channel includes a feedforward equalizer FFE and a decision feedback equalizer DFE that are sequentially connected, and an output end of the ADC sampler is connected to an input end of the feedforward equalizer FFE in the sampling data channel, and an output end of the decision feedback equalizer DFE is used as a sampling data output end of the SerDes receiver. The analog front-end circuit AFE includes a T-coil (T-coil), a linear equalizer CTLE, and a Variable Gain Amplifier (VGA), and it should be noted that the improvement of the SerDes receiver in this embodiment is only a CDR circuit, so the other relevant components will not be described in detail here.
As an optional implementation manner, the design of the SerDes receiver is completed based on a 12nm CMOS process in the embodiment, the working speed of the CDR circuit is 112Gb/s, PAM4 signal modulation is adopted, and in order to reduce jitter and error rate, a jitter model is established by using the fourth-order pulse amplitude modulation baud rate phase discrimination gain equation to accurately set parameters so as to reduce clock jitter. When the CDR circuit loop converges, the simulation result of the transistor level is 523fs when the recovered clock jitter is 14GHz RMS And 2.95ps pp As shown in fig. 8 (a). 10 -12 The jitter tolerance simulation result of the magnitude error rate is shown in (b) of fig. 8, and the jitter tolerance can completely meet the CEI-112G-LR-PAM4 mask requirement. The CDR circuit performance pairs of the SerDes receiver of this embodiment and the CDR circuit performance pairs of other fourth-order pulse amplitude modulation baud rate phase demodulation methods in recent years are shown in table 3.
Table 3: comparison tables of different CDR circuit performances.
In Table 3, silicon [3] is a conventional CDR circuit described in literature (N.Qi et al., "A51Gb/s,320mW,PAM4CDR with baud-rate sampling for high-speed optical interconnects," in 2017IEEE Asian Solid-State Circuits Conference (A-SSCC), seoul, korea (South), nov.2017, pp.89-92.), "Silicon [10] is a conventional CDR circuit described in literature (B.Dehlaghi et al.," A1.41-pJ/b 56-Gb/s PAM-4Receiver Using Enhanced Transition Utilization CDR and Genetic Adaptation Algorithms in 7-nm CMOS, "IEEE Solid-State Circuits Letters, vol.2, no.11, pp.248-251,2019,"), silicon [11] is a conventional CDR circuit described in literature (P.Peng, J.Li, L.Chen, and J.Lee, "6.1A 56Gb/s PAM-4/NRZ transceiver in nm CMOS," in 2017IEEE International Solid-State Circuits Conference (ISSCC), pp.110-111, feb.2017.). Referring to table 3, the CDR circuit of this embodiment has higher conversion density and lower jitter, so that the design efficiency of each parameter of the CDR loop can be improved, and the clock recovery jitter can be reduced, and the CDR circuit can be applied to the ADC-based high-speed digital clock recovery circuit of the super-speed SerDes receiver in the fields of electrical communication and optical communication.
The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above examples, and all technical solutions belonging to the concept of the present invention belong to the protection scope of the present invention. It should be noted that modifications and adaptations to the present invention may occur to one skilled in the art without departing from the principles of the present invention and are intended to be within the scope of the present invention.

Claims (10)

1. A four-order pulse amplitude modulation baud rate phase discrimination method, comprising:
s101, determining inclination information according to 3 adjacent sampling data D (n-1), D (n) and D (n+1);
s102, determining 3 adjacent error types E (n-1), E (n) and E (n+1) according to a sampling point area of sampling data, and obtaining a phase discrimination result of nth sampling data D (n) according to E (n) and combined inclination information if E (n) is an effective error type; if E (n) is an invalid error type and E (n-1) or E (n+1) is an effective error type, the phase discrimination result of the nth sampling data D (n) is obtained according to E (n-1) or E (n+1) combined with the inclination information which is the effective error type.
2. The method according to claim 1, wherein in step S102, when determining 3 adjacent error types E (n-1), E (n), and E (n+1) according to the sampling point area of the sampled data, the sampling point area is divided into continuously distributed I-VII areas according to the order of the voltages from small to large, the corresponding error type is the first error type if the sampling point area of the sampled data is located in IV area, the corresponding error type is the second error type if the sampling point area of the sampled data is located in I area, VII area, III area, or V area, the corresponding error type is the third error type if the sampling point area of the sampled data is located in II area or VI area, and the valid error type is the first error type and the third error type, and the invalid error type is the second error type.
3. The four-order pulse amplitude modulation baud rate phase discrimination method according to claim 2, wherein said error type codes include three of 00, 11, 01, where 00 represents a first error type, 11 represents a third error type, and 01 represents a second error type.
4. A fourth order pulse amplitude modulation baud rate phase discrimination method according to claim 3, wherein the slope information determined in step S102 is composed of a combination of the size comparison result of both the sampling data D (n-1), D (n) and the size comparison result of both D (n), D (n+1).
5. The method of phase discrimination according to claim 4, wherein the step S102 of obtaining the phase discrimination result for phase lead or lag based on E (n) and the combined slope information includes: when the determined inclination information is D (n-1) < D (n) < D (n+1) or D (n-1) < D (n) < D (n+1), and the n-th error type E (n) is 00, if the value of the n-th sampling data D (n) is +3, the phase discrimination result is no information, if the value of the n-th sampling data D (n) is +1, the phase discrimination result is advanced, if the value of the n-th sampling data D (n) is-1, the phase discrimination result is lagged, and if the value of the n-th sampling data D (n) is-3, the phase discrimination result is no information; when the determined inclination information is D (n-1) < D (n) < D (n+1) or D (n-1) < D (n) < D (n+1), and the n-th error type E (n) is 11, if the value of the n-th sampling data D (n) is +3, the phase discrimination result is advanced, if the value of the n-th sampling data D (n) is +1, the phase discrimination result is retarded, if the value of the n-th sampling data D (n) is-1, the phase discrimination result is advanced, and if the value of the n-th sampling data D (n) is-3, the phase discrimination result is retarded; when the determined inclination information is D (n-1) not less than D (n) > D (n+1) or D (n-1) not less than D (n) > D (n+1), and the n-th error type E (n) is 00, if the value of the n-th sampling data D (n) is +3, the phase discrimination result is no information, if the value of the n-th sampling data D (n) is +1, the phase discrimination result is hysteresis, if the value of the n-th sampling data D (n) is-1, the phase discrimination result is advanced, and if the value of the n-th sampling data D (n) is-3, the phase discrimination result is no information; when the determined inclination information is D (n-1) > D (n) > D (n+1) or D (n-1) > D (n) > D (n+1), and the n-th error type E (n) is 11, if the value of the n-th sampling data D (n) is +3, the phase discrimination result is lagged, if the value of the n-th sampling data D (n) is +1, the phase discrimination result is advanced, if the value of the n-th sampling data D (n) is-1, the phase discrimination result is lagged, and if the value of the n-th sampling data D (n) is-3, the phase discrimination result is advanced.
6. The method of phase discrimination according to claim 4, wherein the step S102 of obtaining the phase discrimination result of the nth sampled data D (n) based on E (n-1) or E (n+1) combined with the slope information, which is the effective error type, includes: when the determined inclination information is D (n-1) < D (n). Ltoreq.D (n+1) and the n-th error type E (n) is 01, if the n-1-th error type E (n-1) is not 01, the value of the n-th sampling data D (n) is +1, and the phase discrimination result is hysteresis; when the determined inclination information is D (n-1). Ltoreq.D (n) < D (n+1) and the n-th error type E (n) is 01, if the n+1th error type E (n+1) is not 01, the value of the n-th sampling data D (n) is +1, and the phase discrimination result is advanced; when the determined inclination information is D (n-1) > D (n) > D (n+1) and the n-th error type E (n) is 01, if the n+1th error type E (n+1) is not 01, the value of the n-th sampling data D (n) is +1, and the phase discrimination result is advanced; when the determined inclination information is D (n-1) > D (n) > D (n+1) and the n-th error type E (n) is 01, if the n-1-th error type E (n-1) is not 01, the value of the n-th sampling data D (n) is +1, and the phase discrimination result is hysteresis.
7. A CDR circuit for a high-speed serial interface, comprising an ADC sampler, a feedforward equalizer FFE, a baud rate phase discriminator, a voter, a low-pass digital filter, and a phase interpolator, wherein the ADC sampler, the feedforward equalizer FFE, the voter, and the low-pass digital filter are sequentially connected, the phase interpolator is configured to perform phase calibration on an externally input PPL clock according to phase information output from the low-pass digital filter, and then to use the phase calibrated PPL clock as a clock signal for the ADC sampler, and the baud rate phase discriminator is programmed or configured to perform the fourth-order pulse amplitude modulation baud rate phase discrimination method according to any one of claims 1 to 6.
8. The CDR circuit for a high-speed serial interface of claim 7, wherein the low-pass digital filter is a 2-order low-pass digital filter.
9. The CDR circuit for a high-speed serial interface of claim 8, wherein the feedforward equalizer FFE is a 4-tap feedforward equalizer FFE.
10. A SerDes receiver comprising an analog front-end circuit AFE, a phase-locked loop PPL, a clock-sampled data recovery circuit and a sampled data channel, wherein the clock-sampled data recovery circuit is a CDR circuit for a high-speed serial interface according to any one of claims 7 to 9, sampled data output by the analog front-end circuit AFE is sent to an ADC sampler in the CDR circuit, a PPL clock output by the phase-locked loop PPL is connected to an input of a phase interpolator in the CDR circuit, the sampled data channel comprises a feedforward equalizer FFE and a decision feedback equalizer DFE which are sequentially connected, and an output of the ADC sampler is connected to an input of the feedforward equalizer FFE in the sampled data channel, and an output of the decision feedback equalizer DFE is used as a sampled data output of the SerDes receiver.
CN202310319344.8A 2023-03-28 2023-03-28 Four-order pulse amplitude modulation baud rate phase discrimination method, CDR circuit and receiver Pending CN116527039A (en)

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