CN116525672A - Semiconductor device, manufacturing method thereof and electronic equipment - Google Patents
Semiconductor device, manufacturing method thereof and electronic equipment Download PDFInfo
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- CN116525672A CN116525672A CN202210080586.1A CN202210080586A CN116525672A CN 116525672 A CN116525672 A CN 116525672A CN 202210080586 A CN202210080586 A CN 202210080586A CN 116525672 A CN116525672 A CN 116525672A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 72
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 43
- 238000002955 isolation Methods 0.000 claims abstract description 96
- 239000000758 substrate Substances 0.000 claims abstract description 60
- 230000005669 field effect Effects 0.000 claims abstract description 37
- 239000010410 layer Substances 0.000 claims description 539
- 239000003989 dielectric material Substances 0.000 claims description 43
- 239000011229 interlayer Substances 0.000 claims description 35
- 229910052751 metal Inorganic materials 0.000 claims description 33
- 239000002184 metal Substances 0.000 claims description 33
- 238000000034 method Methods 0.000 claims description 23
- 239000000463 material Substances 0.000 claims description 16
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 12
- 230000004888 barrier function Effects 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 10
- 230000008859 change Effects 0.000 claims description 9
- 238000005137 deposition process Methods 0.000 claims description 2
- 230000005684 electric field Effects 0.000 description 73
- 230000015556 catabolic process Effects 0.000 description 32
- 238000010586 diagram Methods 0.000 description 26
- 238000009826 distribution Methods 0.000 description 26
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 24
- 229920005591 polysilicon Polymers 0.000 description 23
- 230000000694 effects Effects 0.000 description 14
- 238000005229 chemical vapour deposition Methods 0.000 description 10
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 230000002902 bimodal effect Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 230000003071 parasitic effect Effects 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 230000008021 deposition Effects 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- IYYIVELXUANFED-UHFFFAOYSA-N bromo(trimethyl)silane Chemical compound C[Si](C)(C)Br IYYIVELXUANFED-UHFFFAOYSA-N 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 230000003313 weakening effect Effects 0.000 description 1
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/404—Multiple field plate structures
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
- H01L29/8725—Schottky diodes of the trench MOS barrier type [TMBS]
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Abstract
The application provides a semiconductor device, a manufacturing method thereof and electronic equipment, and relates to the technical field of semiconductors. The split gate trench field effect transistor in the semiconductor device includes: substrate, epitaxial layer, field plate, isolation dielectric layer. The epitaxial layer is arranged on the substrate, and a groove is formed in one side, far away from the substrate, of the epitaxial layer. The field plate is positioned in the groove, and the isolation medium layer at least covers the side face of the field plate; the isolation dielectric layer comprises a first dielectric layer and a second dielectric layer which cover the side face of the field plate, the first dielectric layer is close to the bottom of the groove relative to the second dielectric layer, and the dielectric coefficient of the second dielectric layer is larger than that of the first dielectric layer.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a semiconductor device, a method for manufacturing the semiconductor device, and an electronic device.
Background
Split gate trench MOSFET (split gate trench metal oxide semiconductor field effect) Transistor, SGT MOS) is widely used in the field of power semiconductors. For SGT MOS, the breakdown voltage (breakdown voltage, VBR) tends to be a relationship with a series of parameters that are trade off. By increasing the breakdown voltage capability of the device, a lower specific on-resistance (specific on resistance, RSP) and lower gate-drain capacitance C can be obtained at the same voltage gd Etc., thereby enabling higher switching speeds and lower power consumption and improving device reliability.
FIG. 1 (a) is a schematic diagram of the structure of an SGT MOS provided in the related art, and FIG. 1 (b) is an electric field distribution curve of the SGT MOS along the dotted line in FIG. 1 (a). Referring to FIGS. 1 (a) and (b), in SGT MOS, the gate-drain capacitance C is reduced by introducing a field plate FP (field plate) under trench gate G to shield most of the electric field from drain D to gate G gd The switching speed of the device is improved; meanwhile, due to the introduction of the field plate FP, the breakdown electric field of the device is converted from a unimodal electric field of a parallel plane junction to a bimodal electric field. In a bimodal electric field, one electric field is located at the PN junction between the P-well (P-well) region and the N-drift region, and the other electric field is located at the bottom of the trench. Thus, the device electric field is changed from triangular distribution to bimodal electric field distribution by introducing horizontal depletion based on vertical depletion (PN junction) through the arrangement of the field plates. With the same doping concentration of the epitaxial specification, the device can achieve a higher breakdown voltage. However, a bimodal electric field is formed by modulating a field plate, and a large gap is formed between the field plate and an ideal high breakdown voltage (corresponding to a rectangular electric field in fig. 2), so that the breakdown voltage of a device is improved by further modulating the electric field, which has been a pursuit target of industry.
Disclosure of Invention
The application provides a semiconductor device, a manufacturing method thereof and electronic equipment, and breakdown voltage of the device can be improved.
The present application provides a semiconductor device in which a split gate trench type field effect transistor (which may be simply referred to as a transistor) is provided. The transistor comprises a substrate, an epitaxial layer, a field plate and an isolation medium layer, wherein the epitaxial layer, the field plate and the isolation medium layer are arranged on the substrate. The epitaxial layer is provided with a groove at one side far away from the substrate, and a field plate is arranged in the groove. The isolation medium layer at least covers the side face of the field plate, the isolation medium layer comprises a first medium layer and a second medium layer which cover the side face of the field plate, the first medium layer is close to the bottom of the groove relative to the second medium layer, and the dielectric coefficient of the second medium layer is larger than that of the first medium layer.
Illustratively, in some possible implementations, the split-gate trench field effect transistor may further include: the first metal layer, the second metal layer and the insulating medium layer; the first metal layer is arranged on one side of the substrate far away from the epitaxial layer, and the insulating medium layer is arranged between the epitaxial layer and the second metal layer; the substrate is made of an N-type lightly doped semiconductor material; the epitaxial layer is divided into from bottom to top: an N-type lightly doped layer (N-), a P-type doped layer (P), an N-type heavily doped layer (N+); the field plate is located in the region where the N-type lightly doped layer is located (i.e., the drift region). The first metal layer is used as a drain electrode of the transistor, and the second metal layer is used as a source electrode of the transistor. In the epitaxial layer, an N-type lightly doped layer (N-), a P-type doped layer (P) form PN junctions in the transistor, and an N-type heavily doped layer (N+) is used as a drift region of the transistor; an isolation dielectric layer is filled between the field plate and the drift region. Of course, as another possible implementation, the substrate is made of P-type lightly doped semiconductor material; the epitaxial layer is divided into from bottom to top: a P-type lightly doped layer, an N-type doped layer and a P-type heavily doped layer.
Compared with the prior art, in the embodiment of the application, the isolation dielectric layer on the side surface of the field plate is made of two or more dielectric materials, so that the dielectric coefficient of the isolation dielectric layer is increased from bottom to top. Under the condition, the dielectric coefficient of the isolation medium layer is increased from bottom to top, so that the purpose of changing the capacitance of a unit area between the field plate and the epitaxial layer (drift region) is achieved, the modulation effect of the field plate on the electric field is further changed, the charge electric field lines of the epitaxial layer (drift region) are gathered at the position of the dielectric constant change of the isolation medium layer, a new peak electric field is introduced, the electric field peak at the bottom of the electric field is weakened, the multi-peak distribution of the breakdown electric field is realized,the breakdown voltage of the device is improved, and thus lower specific on-Resistance (RSP) and lower grid-drain capacitance C are obtained gd And the like, the figure of merit of the device is improved, higher switching speed and lower power consumption are realized, and the reliability of the device is improved.
It should be further understood that, in this application, by setting the dielectric coefficient near the top of the near-field plate in the isolation dielectric layer to be greater than the dielectric coefficient near the bottom of the field plate, in this case, on one hand, the capacitance per unit area is larger at the PN junction near the transistor, and the electric field lines of charges of the epitaxial layer (drift region) gather toward the top of the field plate, so as to weaken the electric field at the PN junction position, thereby playing a better role in protecting the PN junction; on the other hand, the capacitance per unit area at the position close to the bottom of the field plate is smaller, so that the electric field at the bottom of the field plate is weakened, and the probability that the field plate breaks down an epitaxial layer (drift region) at the bottom of the groove is reduced.
In some possible implementations, the split-gate trench field effect transistor is a double-gate structure, and the transistor is provided with a first gate and a second gate in a trench. The first grid electrode and the second grid electrode are positioned on two sides of the top end of the field plate, and an interlayer dielectric layer is arranged among the first grid electrode, the second grid electrode and the field plate; the interlayer dielectric layer is positioned on one side of the isolation dielectric layer far away from the bottom of the groove. Namely, the split gate trench type field effect transistor is a double gate trench type field effect transistor.
In some possible implementations, the split-gate trench field effect transistor is in a single gate structure, and a gate is arranged in the trench; the grid electrode is positioned on one side of the field plate far away from the substrate, and an interlayer dielectric layer is arranged between the grid electrode and the field plate. That is, the split gate trench type field effect transistor is a single gate trench type field effect transistor.
In some possible implementations, the isolation dielectric layer further includes a third dielectric layer overlying the sides of the field plate. The third dielectric layer is far away from the bottom of the groove relative to the second dielectric layer; the dielectric coefficient of the third dielectric layer is larger than that of the second dielectric layer. By arranging the dielectric layers with three dielectric coefficients, the four-peak electric field distribution can be obtained, and the breakdown voltage and the reliability of the device are further improved.
In some possible implementations, at least one of the first dielectric layer or the second dielectric layer has a graded dielectric coefficient; the graded dielectric constant gradually increases in the direction from the bottom of the trench to the notch. In this case, the larger the number of peaks of the electric field that can be obtained, the closer the breakdown electric field distribution is to the rectangular distribution.
In some possible implementations, the first dielectric layer is a first dielectric material; the second dielectric layer is made of a multi-compound dielectric material, and the atomic or molecular components of the multi-compound dielectric material gradually change along the direction from the bottom of the groove to the notch. I.e. the first dielectric layer has a fixed dielectric constant and the second dielectric layer has a graded dielectric constant. Illustratively, the second dielectric layer may be SiO x N y 、HfO x N y Etc.
In some possible implementations, an isolation buffer layer is disposed between the isolation dielectric layer and the sidewall of the trench in a side region near the top of the field plate; in this case, a good interface is formed between the isolation buffer layer and the sidewall of the trench, so that reliability problems such as leakage current caused by direct contact between the second dielectric layer and the sidewall of the trench are avoided.
In some possible implementations, the isolation buffer layer employs SiO 2 。
In some possible implementations, the isolation dielectric layer extends and covers to the top surface of the field plate. In this case, the second dielectric layer may be formed at the same time as forming at least part of the interlayer dielectric layer, that is, all or part of the interlayer dielectric layer is made of the same material as the second dielectric layer.
In some possible implementations, the interlayer dielectric layer includes an intermediate dielectric layer; the dielectric coefficient of the intermediate dielectric layer is smaller than that of the second dielectric layer. In this way, parasitic capacitance between the gate and the field plate can be reduced by reducing the dielectric coefficient of the interlayer dielectric layer.
In some possible implementations, the intermediate dielectric layer covers the top surface of the field plate. In this case, the whole interlayer dielectric layer can be made of a dielectric material with a smaller dielectric coefficient, so that parasitic capacitance between the gate and the field plate is further reduced.
In some possible implementations, the sides of the field plate are provided with at least one stepped structure; of the two stepped surfaces of the stepped structure, the stepped surface on the side close to the notch of the groove protrudes from the stepped surface on the side close to the bottom of the groove. Therefore, by arranging the step structure on the side surface of the field plate, the electric field spike can be restrained in the vertical direction, the breakdown voltage of the device is improved, and the reliability of the device is improved.
The embodiment of the application also provides a semiconductor device, and the semiconductor device is provided with the groove type electronic element. The trench type electronic component comprises: the device comprises a substrate, an epitaxial layer, a field plate and an isolation medium layer, wherein the epitaxial layer, the field plate and the isolation medium layer are arranged on the substrate. The epitaxial layer is provided with a first trench on a side remote from the substrate. A field plate is arranged in the first groove. The isolation dielectric layer covers at least the sides of the field plate. The isolation medium layer comprises a first medium layer and a second medium layer, and the first medium layer is close to the bottom of the first groove relative to the second medium; the dielectric coefficient of the second dielectric layer is greater than that of the first dielectric layer.
In the trench type electronic component adopted by the semiconductor device, two or more dielectric materials are adopted by arranging the isolation dielectric layer on the side surface of the field plate, so that the dielectric coefficient of the isolation dielectric layer is increased from bottom to top. Under the condition, the dielectric coefficient which is changed based on the increase of the isolating dielectric layer from bottom to top can play a role in changing the capacitance of a unit area, changing the modulation effect of a field plate on an electric field, and then playing a role in changing the capacitance of the unit area between the field plate and an epitaxial layer (drift region), so as to change the modulation effect of the field plate on the electric field, leading the charge electric field lines of the epitaxial layer (drift region) to gather at the abrupt position of the dielectric layer (namely the position with the changed dielectric constant) to introduce a new peak electric field, weakening the electric field peak at the bottom of the electric field, realizing the multi-peak distribution of breakdown electric field, improving the breakdown voltage of a device, and further obtaining lower specific on-Resistance (RSP) and lower grid-drain capacitance C gd And the like, the figure of merit of the device is improved, higher switching speed and lower power consumption are realized, and the reliability of the device is improved.
In some possible implementations, the trench-type electronic component may be a non-split gate trench-type field effect transistor; the trench type field effect transistor further comprises a grid electrode positioned in the first trench, and the grid electrode is connected with the top of the field plate.
In some possible implementations, the trench-type electronic component is a double trench-type field effect transistor; in the double-groove type field effect transistor, a second groove is further formed in one side, far away from a substrate, of an epitaxial layer, and the second groove and the first groove are arranged in parallel; the grid electrode is positioned in the second groove; the depth of the second trench is less than the depth of the first trench.
In some possible implementations, the trench electronic component is a trench MOS barrier schottky diode; the trench MOS barrier Schottky diode further comprises a first metal layer and a second metal layer; the first metal layer is positioned on one side of the substrate far away from the epitaxial layer, and the second metal layer is positioned on one side of the epitaxial layer far away from the substrate; the top of the field plate is connected with the second metal layer.
In some possible implementations, the trench-type electronic component is an insulated gate bipolar transistor; the substrate is made of an N-type semiconductor material; the insulated gate bipolar transistor further comprises a gate electrode and a P-type semiconductor layer. The grid is positioned in the first groove, the grid is positioned at one side of the field plate far away from the bottom of the first groove, and an interlayer dielectric layer is arranged between the grid and the field plate. The P-type semiconductor layer is positioned on one side of the substrate away from the epitaxial layer. The epitaxial layer is sequentially an N-type doped region, a P-type doped region and an N-type heavily doped region along the direction far away from the substrate.
The embodiment of the application also provides electronic equipment, which comprises a printed circuit board and a semiconductor device provided in any one of the possible modes; the semiconductor device is electrically connected to the printed wiring board.
The embodiment of the application also provides a manufacturing method of the semiconductor device, which comprises the following steps: a substrate is provided and an epitaxial layer is grown on the surface of the substrate. And forming a groove on the surface of the epitaxial layer, and forming a first dielectric layer in the inner wall of the groove. And forming a field plate in the groove with the first dielectric layer, and etching the first dielectric layer back to a depth below the top of the field plate. And forming a second dielectric layer on the side surface of the field plate and the surface of the first dielectric layer, wherein the dielectric coefficient of the second dielectric layer is larger than that of the first dielectric layer.
In some possible implementations, the forming a second dielectric layer on a surface of the first dielectric layer, which is located on a side surface of the field plate may include: and depositing a multi-compound dielectric material on the side surface of the field plate and the surface of the first dielectric layer, and controlling atomic or molecular components in the multi-compound dielectric material in the deposition process to form a second dielectric layer with gradually increased dielectric coefficient.
In some possible implementations, after forming the isolation dielectric layer including the first dielectric layer and the second dielectric layer on the side surface of the field plate, the manufacturing method may further include: an intermediate dielectric layer is formed on top of the field plate and has a dielectric constant less than that of the second dielectric layer.
Drawings
FIG. 1 is a schematic diagram of SGT MOS and breakdown field distribution thereof according to the related art of the present application;
FIG. 2 is a schematic diagram of an ideal electric field distribution of SGT MOS;
FIG. 3 is a schematic diagram of SGT MOS and breakdown field distribution thereof according to an embodiment of the present application;
FIG. 4 is a schematic structural diagram of an SGT MOS according to an embodiment of the present application;
FIG. 5 is a schematic structural diagram of an SGT MOS according to an embodiment of the present application;
FIG. 6 is a schematic structural diagram of an SGT MOS according to an embodiment of the present application;
FIG. 7 is a schematic structural diagram of an SGT MOS according to an embodiment of the present application;
FIG. 8 is a schematic structural diagram of an SGT MOS according to an embodiment of the present application;
FIG. 9 is a schematic structural diagram of an SGT MOS according to an embodiment of the present application;
FIG. 10 is a schematic structural diagram of an SGT MOS according to an embodiment of the present application;
FIG. 11 is a flowchart of a method for fabricating an SGT MOS according to an embodiment of the present application;
FIG. 12 is a schematic diagram of a manufacturing process of an SGT MOS according to an embodiment of the present disclosure;
FIG. 13 is a schematic diagram of a manufacturing process of an SGT MOS according to an embodiment of the present disclosure;
FIG. 14 is a schematic structural diagram of an SGT MOS according to an embodiment of the present application;
FIG. 15 is a flowchart of a method for fabricating an SGT MOS according to an embodiment of the present application;
FIG. 16 is a schematic diagram illustrating a manufacturing process of an SGT MOS according to an embodiment of the present disclosure;
FIG. 17 is a schematic diagram of a manufacturing process of an SGT MOS according to an embodiment of the present disclosure;
FIG. 18 is a schematic diagram of a structure of a non-SGT MOS according to an embodiment of the present application;
FIG. 19 is a flowchart of a method for fabricating a non-SGT MOS according to an embodiment of the present application;
FIG. 20 is a schematic diagram of a process for fabricating a non-SGT MOS according to an embodiment of the present application;
FIG. 21 is a schematic diagram of a process for fabricating a non-SGT MOS according to an embodiment of the present application;
FIG. 22 is a schematic diagram of a dual trench SGT MOS structure according to embodiments of the present application;
fig. 23 is a schematic structural diagram of an IGBT according to an embodiment of the present application;
fig. 24 is a schematic structural diagram of a trench MOS barrier schottky diode according to an embodiment of the present application.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the present application more apparent, the technical solutions in the present application will be clearly and completely described below with reference to the drawings in the present application, and it is apparent that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
The terms "first," "second," and the like in the description and in the claims and drawings are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or order. "and/or" for describing the association relationship of the association object, the representation may have three relationships, for example, "a and/or B" may represent: only a, only B and both a and B are present, wherein a, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one" means one or more, and "a plurality" means two or more. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b or c may represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", wherein a, b, c may be single or plural. "mounted," "connected," and the like are to be construed broadly and may be, for example, fixedly connected, detachably connected, or integrally connected; either directly or indirectly through intermediaries, or through communication between two elements. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion, such as a series of steps or elements. The method, system, article, or apparatus is not necessarily limited to those explicitly listed but may include other steps or elements not explicitly listed or inherent to such process, method, article, or apparatus. "upper", "lower", "left", "right", "top", "bottom", etc. are used merely with respect to the orientation of the components in the drawings, these directional terms are relative concepts which are used for descriptive and clarity with respect thereto and which may be varied accordingly with respect to the orientation in which the components are placed in the drawings.
An embodiment of the present application provides an electronic apparatus including a printed wiring board (printed circuit board, PCB) and a semiconductor device electrically connected to the printed wiring board, in which a trench type electronic element is provided.
The present application is not limited to the arrangement form of the semiconductor device described above. Illustratively, the semiconductor device may be a central processing unit (central processing unit, CPU), a graphics processor (graphics processing unit, GPU), a micro control unit (microcontroller unit; MCU), a motor drive, an uninterruptible (uninterrupted power supply, UPS) power supply, or the like.
The present application does not limit the setting form of the electronic device. The electronic equipment can be electronic products such as mobile phones, tablet computers, notebooks, vehicle-mounted computers, intelligent watches, intelligent bracelets and the like.
In the electronic device provided in the embodiment of the present application, the semiconductor device employs a trench type electronic element provided with a field plate (field plate), that is, a trench is provided in the trench type electronic element, and the field plate is provided in the trench. The present application is not limited to the specific form of the trench type electronic component. For example, the trench type electronic component may be a trench type field effect transistor (such as split gate structure, non-split gate structure, double trench structure, etc.), a trench type MOS barrier schottky diode, an insulated gate bipolar transistor, etc.
In this embodiment, the dielectric layer (i.e. isolation dielectric layer) on the side of the field plate is arranged in the trench of the trench-type electronic component to have two or more dielectric coefficients (i.e. dielectric constants) along the depth direction of the trench, so as to modulate the electric field outside the field plate, stabilize (weaken) the original bimodal electric field (as shown in fig. 1), obtain the three-peak electric field distribution (as shown in fig. 3) or the multi-peak electric field distribution, and even achieve the approximately ideal rectangular electric field distribution (as shown in fig. 2), thereby improving the breakdown voltage of the device, and further obtaining the lower specific on-Resistance (RSP) and the lower gate-drain capacitance C gd And the like, the figure of merit of the device is improved, and the reliability of the device is improved.
The arrangement of the isolation medium layer on the side of the field plate in the present application will be specifically described below by means of specific embodiments in combination with specific arrangement forms of the trench type electronic component.
Example 1
The first embodiment provides a semiconductor device employing a split gate (single gate) trench type field effect transistor (hereinafter may be simply referred to as a transistor).
FIG. 3 (a) is a schematic diagram of the structure of two SGT MOSs (i.e., two cells) in parallel in a semiconductor device; FIG. 3 (b) shows the electric field distribution curve of the SGT MOS in (a) along the dotted line. The following is only a schematic illustration of a single SGT MOS.
Referring to fig. 3 (a), the SGT MOS may include a substrate 1 and an epitaxial layer 2 and an insulating dielectric layer 3 sequentially disposed on the substrate.
Illustratively, the substrate 1 may employ an N-type heavily doped semiconductor material, i.e., an n+ substrate, which serves as the drain region of the transistor. The epitaxial layer 2 can be sequentially divided into an N-type lightly doped layer (N-), a P-type doped layer (P) and an N-type heavily doped layer (N+), wherein in the epitaxial layer 2, the N-type lightly doped layer (N-) is used as a drift region (N-drift) of a transistor, the P-type doped layer (P) is used as a well region (namely P-well) of the transistor, and the N-type heavily doped layer (N+) is used as a source region of the transistor; PN junctions are formed between the P-well (P-well) region and the drift region (N-drift). In addition, the substrate 1 and the epitaxial layer 2 can be made of silicon (Si) material, and the insulating dielectric layer 3 can be made of SiO 2 The method comprises the steps of carrying out a first treatment on the surface of the But is not limited thereto.
In fig. 3, an N-type transistor is illustrated as an example, and in other possible implementations, the transistor may be a P-type transistor, in which case, a p+ substrate may be used as the substrate 1, and the epitaxial layer 2 may be sequentially divided into a P-type lightly doped layer (P-), an N-type doped layer (N), and a P-type heavily doped layer (p+), from bottom to top. The following examples are given by way of example of N-type transistors.
In addition, a first metal layer M1 is provided on the lower surface of the substrate 1 as a drain D of the transistor; the upper surface of the insulating dielectric layer 3 is provided with a second metal layer M2 as the source S of the transistor. The second metal layer M2 is connected to the well region (P-well) through a metal plug M. Illustratively, the metal plug m may be a tungsten plug (wplug), but is not limited thereto. In order to reduce the contact resistance of the metal plug m and the well region (P-well), and the parasitic resistance of the P-well region related to the latch-up resistance of the device, heavy doping (p+) may be performed at the well region (P-well) at a position corresponding to the metal plug m.
As shown in fig. 3, a trench T is provided in the upper surface of the epitaxial layer 2 (i.e., the surface on the side away from the substrate 1), and a field plate FP and a gate G are provided in the trench T, the gate G being located above the field plate FP. Illustratively, the gate G and the field plate FP may be made of polysilicon material (polycrystalline silicon), but are not limited thereto. Typically the depth of the gate G is substantially coincident with the lower surface of the well region (P-well) and the field plate FP is entirely located within the drift region (N-drift). Dielectric materials are filled between the gate G and the groove wall of the groove T, between the field plate FP and the groove wall of the groove T and between the gate G and the field plate FP so as to isolate the gate G, the field plate FP and the epitaxial layer 2.
Compared to the prior art, in the embodiment of the present application, two or more dielectric materials are used for the isolation dielectric layer 10 on the side of the field plate FP, so that the dielectric coefficient of the isolation dielectric layer 10 increases from bottom to top. In this case, based on the dielectric constant of the isolation dielectric layer 10, the dielectric constant of the isolation dielectric layer 10 is increased from bottom to top, so as to change the capacitance per unit area between the field plate and the drift region (N-drift), change the modulation effect of the field plate on the electric field, make the charge electric field lines of the drift region (N-drift) gather at the position where the dielectric constant of the isolation dielectric layer 10 changes, introduce a new peak electric field, weaken the electric field peak at the bottom of the electric field, realize the trimodal (as shown in fig. 3) or multimodal distribution of the breakdown electric field, improve the breakdown voltage of the device, and obtain lower specific on-Resistance (RSP) and lower gate-drain capacitance C gd And the like, the figure of merit of the device is improved, higher switching speed and lower power consumption are realized, and the reliability of the device is improved.
In addition, it should be further understood that, in this application, by setting the dielectric coefficient near the top of the field plate FP in the isolation dielectric layer 10 to be greater than the dielectric coefficient near the bottom of the field plate FP, in this case, on one hand, the capacitance per unit area is larger near the PN junction (between P-well and N-drift), and the electric field line of the electric charge of the drift region (N-drift) is concentrated toward the top of the field plate FP, so that the electric field at the PN junction position can be weakened, and a better protection effect is achieved for the PN junction; on the other hand, the capacitance per unit area at a position close to the bottom of the field plate can be made smaller, so that the electric field at the bottom of the field plate FP is weakened, and the probability that the field plate FP breaks down a drift region (N-drift) at the bottom of the trench T is reduced. Of course, the dielectric constant of the isolation dielectric layer 10 may be increased stepwise or gradually, and this may be not limited according to the specific arrangement of the isolation dielectric layer 10.
For example, in some possible implementations, as shown in fig. 3, the isolation dielectric layer 10 may include a first dielectric layer a1 and a second dielectric layer a2 that cover sides of the field plate FP. The first dielectric layer a1 is positioned below, and the second dielectric layer a2 is positioned above; i.e. the first dielectric layer a1 is close to the bottom of the trench T with respect to the second dielectric layer a2. The first dielectric layer a1 adopts a first dielectric material, the second dielectric layer a2 adopts a second dielectric material, and the dielectric coefficient k2 of the second dielectric material is larger than the dielectric coefficient k1 of the first dielectric material, namely k2 > k1. Illustratively, the first dielectric material may be SiO 2 (dielectric constant of about 3.9); the second dielectric material may be Si 3 N 4 (dielectric constant of about 7.9), hfO 2 (dielectric constant of about 25), al 2 O 3 (dielectric constant of about 9), etc.; but is not limited thereto.
For another example, in some possible implementations, as shown in fig. 4, the isolation dielectric layer 10 may include a first dielectric layer a1, a second dielectric layer a2, and a third dielectric layer a3 that sequentially cover the sides of the field plate FP from bottom to top. The first dielectric layer a1 adopts a first dielectric material, the second dielectric layer a2 adopts a second dielectric material, the third dielectric layer a3 adopts a third dielectric material, the dielectric coefficient k2 of the second dielectric material is larger than the dielectric coefficient k1 of the first dielectric material, and the dielectric coefficient k3 of the third dielectric material is larger than the dielectric coefficient k2 of the second dielectric material, namely k 3 > k2 > k1. Illustratively, the first dielectric material may be SiO 2 (dielectric constant of about 3.9); the second dielectric material may be Si 3 N 4 (dielectric constant of about 7.9), the third dielectric material may be HfO 2 (dielectric constant of about 25); but is not limited thereto.
In the case that the insulating dielectric layer 10 in fig. 3 contains two dielectric layers with different dielectric coefficients on the side surface of the field plate FP, the modulation effect of the field plate on the electric field is changed based on the arrangement of the dielectric layers (a 1, a 2) with two different dielectric coefficients, and a new spike electric field is introduced at the position where the dielectric layers are abrupt (i.e., the position where the dielectric constant is changed), so as to obtain the three spike electric field distribution. In the case of fig. 4, where the isolating dielectric layer 10 contains three dielectric layers (a 1, a2, a 3) of different dielectric coefficients on the side of the field plate FP, a four-peak electric field distribution can be obtained.
The "first dielectric layer", "second dielectric layer" and "third dielectric layer" referred to in the present application refer to only the relative concepts of the isolation dielectric layer 10 satisfying the above design requirements, and do not refer to any fixed dielectric layer(s) in the isolation dielectric layer 10; for example, in the case where the isolation dielectric layer 10 includes 5 dielectric layers, any two dielectric layers (e.g., a sub-top layer and a top layer) disposed from bottom to top may be considered as a first dielectric layer and a second dielectric layer, respectively.
It should be noted that, in the present application, the "side surface of the field plate" refers to a side surface of the field plate FP in a lateral direction, as illustrated in a schematic cross-sectional view of the field plate FP illustrated in fig. 3 (a), and the side surfaces of the field plate FP are surfaces on both sides of the field plate FP; the field plate FP is planar in the longitudinal direction. Similarly, the gate G above the field plate extends in the longitudinal direction in the same direction as the field plate FP, and the lengths of the two are also substantially the same.
It will be appreciated that the more dielectric layers of different dielectric coefficients are employed in the isolation dielectric layer 10, the greater the number of spikes in the electric field that can be achieved, the closer the breakdown field distribution is to a rectangular distribution. Fig. 3 and 4 are only schematic illustrations of the case where the insulating dielectric layer 10 includes two or three dielectric layers having different dielectric constants, but the present application is not limited thereto, and the insulating dielectric layer 10 may be provided with 4 or more dielectric layers having different dielectric constants. The following is a schematic illustration of two dielectric layers included in the isolation dielectric layer 10.
Based on this, compared to the foregoing isolation dielectric layers 10, each dielectric layer (a 1, a2, a 3) is made of a single dielectric material, that is, each dielectric layer has a fixed dielectric constant, the dielectric constant of the isolation dielectric layer 10 increases stepwise from bottom to top. In other embodiments, some or all of the dielectric layers 10 have a graded dielectric constant, i.e., the dielectric constant varies continuously along the depth of the trench. The change rule of the gradual change dielectric coefficient can be one or combination of various forms such as linear, nonlinear, piecewise function and the like, and by adopting the technical scheme, the approximately ideal electric field modulation effect, namely that the breakdown electric field is approximately rectangular distribution can be obtained by reasonably optimizing the structure and the technological parameters of the isolation medium layer 10.
For example, in some possible implementations, as shown in fig. 5, the isolation dielectric layer 10 may include a first dielectric layer a1 and a second dielectric layer a2. The first dielectric layer a1 is positioned below, and the second dielectric layer a2 is positioned above; i.e. the first dielectric layer a1 is close to the bottom of the trench T with respect to the second dielectric layer a2. The first dielectric layer a1 is made of a first dielectric material and has a fixed dielectric coefficient k1; the second dielectric layer a2 has a graded dielectric coefficient k2, where the graded dielectric coefficient k2 gradually increases from bottom to top (i.e., along the direction from the bottom of the trench to the notch), such as k2=k1+ax, i.e., the second dielectric layer a2 has an X-coordinate origin at the point where it is connected to the first dielectric layer a1, i.e., where the dielectric coefficient is the same as the dielectric coefficient k1 of the first dielectric layer a2, and gradually increases upward.
For the second dielectric layer a2 having the graded dielectric coefficient k2, in some possible implementations, the second dielectric layer a2 may be made of a multi-compound dielectric material whose atomic or molecular composition gradually changes from bottom to top, so as to ensure that the graded dielectric coefficient k2 gradually increases from bottom to top. The multi-compound dielectric material is not limited in this application, such as SiO x N y 、HfO x N y Etc. In practice, the multi-component dielectric material and the atomic or molecular composition thereof used for the second dielectric layer a2 may be selected according to the dielectric material used for the first dielectric layer a 1.
Illustratively, in some embodiments, the first dielectric material may be SiO 2 (dielectric constant of about 3.9), the second dielectric layer a2 is made of SiO x N y . For example, in the second dielectric layer a2, the lower end is SiO 2 (dielectric constant of about 3.9), i.e., x=2, y=0; the upper end is Si 3 N 4 (dielectric constant of about 7.5), i.e. x=0, y=4/3; the values of x and y can be effectively controlled by changing the flow rate, reaction temperature, pressure, etc. of various gases in the middle region where the second dielectric layer a2 is formed, thereby realizing continuous modulation of the dielectric coefficient k2 of the second dielectric layer a2 from 3.9 to 7.5.
Similarly, in other embodiments, the second dielectric layer a2 may be HfO x N y The dielectric coefficient k2 may achieve a modulation variation in the range from 4 to 24.
In addition, the present application does not limit the manner of manufacturing the second dielectric layer a2 having the graded dielectric constant k2, and in practice, a suitable manufacturing method may be selected as needed. For example, in some possible implementations, anisotropic deposition may be achieved using a process of HDP-CVD (high density plasma chemical vapor deposition ) using deposition while etching; that is, etching the material deposited horizontally to the sidewalls while depositing in the vertical direction; thus, a dielectric layer with a dielectric constant gradually changing along the vertical direction (i.e., from bottom to top) is obtained.
It should be noted that, in fig. 5, the second dielectric layer a2 has a graded dielectric coefficient is only illustrated as an example, but the application is not limited thereto, for example, in some embodiments, the first dielectric layer a1 may also be provided to have a graded dielectric coefficient; for another example, in some embodiments, the isolation dielectric layer 10 may also be provided as a single dielectric layer having a graded dielectric constant. Of course, as shown in fig. 4, in the case of using three dielectric layers (a 1, a2, a 3) for the isolation dielectric layer 10, one or more of the three dielectric layers (a 1, a2, a 3) may be provided to have a graded dielectric coefficient.
In addition, in order to avoid the problem of reliability such as leakage current caused by too poor quality of the interface formed between the isolation dielectric layer 10 located on the top side of the field plate FP and the sidewall of the trench T, as shown in fig. 6, in some possible implementations, an isolation buffer layer 11 may be disposed between the second dielectric layer a2 and the sidewall of the trench T, and a good interface is formed between the isolation buffer layer 11 and the sidewall of the trench T, so that the problem of reliability such as leakage current caused by direct contact between the second dielectric layer a2 and the sidewall of the trench T is avoided.
The specific material of the isolation buffer layer 11 is not limited in this application, as long as a good interface is ensured between the isolation buffer layer 11 and the sidewall of the trench T. Illustratively, in some embodiments, the epitaxial layer 2 is a silicon (Si) material and the second dielectric layer a2 is Si 3 N 4 、HfO 2 、Al 2 O 3 And dielectric materials having a high dielectric constant, which form an interface with silicon of poor quality, in which case the isolation buffer layer 11 may be provided with SiO 2 ，SiO 2 A good interface can be formed with Si. Of course, in other embodiments, the isolation buffer layer 11 may also be made of silicon oxynitride (SiO x N y ) Etc., and this application is not limited thereto.
It should be noted that, for the above-mentioned fabrication of the isolation buffer layer 11, in some embodiments, the isolation buffer layer 11 may be fabricated separately; in some embodiments, as shown in fig. 6, the isolation buffer layer 11 and the gate oxide layer 12 (i.e., between the gate G and the sidewall of the trench T) may be fabricated by one process.
In addition, referring to fig. 3, for the interlayer dielectric layer 20 between the gate electrode G and the field plate FP, in some possible implementations, a second dielectric layer a2 may be provided to extend from the side surface of the field plate FP and cover the upper surface (top surface) thereof, that is, the interlayer dielectric layer 20 between the gate electrode G and the field plate FP is formed while the second dielectric layer a2 is formed, in which case the interlayer dielectric layer 20 and the second dielectric layer a2 use the same dielectric material.
For the arrangement mode that the second dielectric layer a2 extends from the side surface of the field plate FP and covers the upper surface of the field plate FP, the second dielectric layer a2 has a higher dielectric coefficient, and the corresponding interlayer dielectric layer 20 has a higher dielectric coefficient, so that a larger parasitic capacitance is generated between the gate G and the field plate FP, and the switching speed of the transistor is reduced. Accordingly, parasitic capacitance between the gate G and the field plate FP may be reduced by reducing the dielectric coefficient of the interlayer dielectric layer 20.
For example, in some possible implementations, as shown in fig. 7, a second dielectric layer a2 may be disposed to extend from the side of the field plate FP and slightly cover the top of the field plate FP, and an intermediate dielectric layer b may be added between the gate G and the field plate FP, where the dielectric coefficient of the intermediate dielectric layer b is smaller than that of the second dielectric layer a 2; in this case, the interlayer dielectric layer 20 includes an upper layer and a lower layer, and the lower layer is made of the same material as the second dielectric layer a2 and has a relatively thin thickness; the upper layer (b) is made of a material with a smaller dielectric coefficient and has a larger thickness. Illustratively, the upper layer may be Si having a thickness of about 15nm 3 N 4 The lower layer is SiO of about 10nm 2 A layer.
For another example, in other possible implementations, as shown in fig. 8, the interlayer dielectric layers 20 may all be an intermediate dielectric layer b with a smaller dielectric coefficient, that is, the intermediate dielectric layer b directly covers the upper surface of the field plate FP; of course, in this case, the interlayer dielectric layer 20 may be extended downward to the side of the field plate FP as appropriate according to the actual manufacturing process.
In addition, in order to further modulate the breakdown field outside the field plate FP, so that the design of the device is more flexible, in some possible implementations, as shown with reference to fig. 9 and 10, at least one step structure 30 may be provided on the side of the field plate FP. The left and right sides of the field plate FP are generally symmetrical. The step structure 30 includes two step surfaces: an upper step surface (i.e., a step surface on a side close to a notch of the groove) and a lower step surface (i.e., a step surface on a side close to a bottom of the groove), the upper step surface protruding from the lower step surface; i.e. the width of the field plate FP is in a structure with a wide upper part and a narrow lower part. In this way, by arranging the step structure 30 on the side surface of the field plate FP, the capacitance per unit area between the field plate and the drift region (N-drift) is changed by changing the thickness of the dielectric layer at the position of the step structure 30, so as to change the modulation effect of the field plate on the electric field, thereby introducing a new spike electric field at the position of the step structure 30, improving the breakdown voltage of the device and improving the reliability of the device.
The specific arrangement position of the step structure 30 on the side of the field plate FP is not limited in this application, and may be actually set as needed. For example, as shown in fig. 9, in some possible implementations, a stair-step structure 30 may be disposed at a side of the field plate FP corresponding to a region of the first dielectric layer a1. As another example, as shown in fig. 10, in some possible implementations, a stair-step structure 30 may be provided at a side of the field plate FP corresponding to a region of the second dielectric layer a 2. For another example, in some possible implementations, the sides of the field plate FP may be provided with a stepped structure 30 in the regions corresponding to the first dielectric layer a1 and the second dielectric layer a2, respectively.
An embodiment of the present application further provides a method for manufacturing a transistor as shown in fig. 3, and as shown in fig. 11, the method may include:
step 11, referring to fig. 12 (a), a substrate 1 is provided, and an epitaxial layer 2 is grown on the surface of the substrate 1.
Illustratively, in some possible implementations, the step 11 may include: an N-epitaxial silicon layer having a specific thickness and resistivity is grown on an N+ silicon substrate.
In step 12, referring to fig. 12 (b) and (c), a trench T is formed on the surface of the epitaxial layer 2, and a first dielectric layer a1 is formed in the inner wall of the trench T.
Illustratively, in some possible implementations, the step 12 may include: referring to fig. 12 (b), a trench T having a certain morphology and interface quality is formed by using photolithography, trench etching, sacrificial oxide growth, and removal thereof. Then, referring to fig. 12 (c), a first dielectric layer a having a specific thickness is formed on the side wall of the trench T and the surface of the epitaxial layer 21, the first dielectric layer a1 may be SiO with a dielectric constant of about 3.9 2 . The SiO is 2 The thermal oxidation growth may be used entirely or a thin layer may be grown by thermal oxidation followed by CVD (chemical vapor deposition ) to deposit the remainder and then annealing.
Step 13, referring to fig. 12 (d), a field plate FP is formed in the groove T in which the first dielectric layer a1 is formed, and the first dielectric layer a1 is etched back to a depth below the top of the field plate FP.
It will be appreciated that the gate G needs to be formed on top of the field plate FP in the subsequent step 13, and thus the depth of the top of the field plate FP should meet the requirements of the subsequent gate G.
Illustratively, in some possible implementations, referring to (d) in fig. 12, step 13 may include: depositing a layer of polysilicon by LP-CVD (low pressure chemical vapor deposition ) and forming a good fill for the trench T; then, etching back (etch-back) the polysilicon to a specific depth d0 without a mask to form a field plate FP, i.e., to form field plate polysilicon (field plate polysilicon); the first dielectric layer a1 is then etched back to another specific depth d1 in a self-aligned manner, and d1> d0. Optionally, the field plate polysilicon may be subjected to CMP (chemical mechanical polishing ) before back etching, so as to improve the flatness of the upper surface thereof, and ensure the isolation effect of the subsequently formed interlayer dielectric layer 20 on the field plate polysilicon-gate polysilicon (refer to fig. 13).
Step 14, referring to fig. 12 (e) and (f), a second dielectric layer a2 is formed on the surface of the first dielectric layer a1 on the side surface of the field plate FP; the dielectric coefficient of the second dielectric layer a2 is larger than that of the first dielectric layer a 1.
Illustratively, in some possible implementations, the step 14 may include: referring to fig. 12 (e), a second dielectric layer a2 is deposited by CVD and a good filling of the trench T is formed. The second dielectric layer a2 may be Si with a dielectric constant of about 7.5 3 N 4 . After depositing the second dielectric layer a2, the surface of the second dielectric layer a2 may be subjected to CMP as needed to extractAnd the flatness of the upper surface is improved. Then, referring to fig. 12 (f), the second dielectric layer a2 may be etched back to another specific depth d2 in a self-aligned manner, and d2<d0. Thus, the second dielectric layer a2 covers the field plate FP by a certain thickness as the interlayer dielectric layer 20.
In step 15, referring to fig. 13 (a) and (b), a gate dielectric layer 12 is formed on the sidewall of the trench T, and a gate G is formed on the surface of the second dielectric layer a 2.
Illustratively, in some possible implementations, referring to fig. 13 (a), a gate dielectric layer 12 (also referred to as a gate dielectric layer or a gate oxide layer) is grown on the exposed sidewall of the trench T and the upper surface of the epitaxial layer 2 by thermal oxidation, and the gate dielectric layer 12 may be formed of SiO 2 . Alternatively, the growth of the sacrificial oxide layer may be performed once and removed before the gate dielectric layer 12 is grown. Of course, the gate dielectric layer 12 may also be formed by CVD. Then, referring to fig. 13 (b), polysilicon is deposited on the surface of the second dielectric layer a2 by LP-CVD to form a good filling of the trench; next, the polysilicon is etched back to a certain depth (typically slightly below the upper surface of the epitaxial layer 2) without a mask to form a gate G; i.e., gate polysilicon (gate polysilicon) is formed. Alternatively, the polysilicon pattern that needs to be preserved for the gate connection structure or other functions may be defined while the gate is formed through a photolithographic mask.
It can be understood herein that the key steps involved in the foregoing manufacturing processes from step 11 to step 15 may be self-aligned, so that the whole manufacturing process is easier to control, i.e. the device has stronger manufacturability.
Of course, after the gate G is fabricated, referring to fig. 3, a P-type lightly doped layer (P), an N-type heavily doped layer (n+) and the like may be formed on the surface of the epitaxial layer 2 by ion implantation, an insulating dielectric layer 3 and a second metal layer M2 may be fabricated on the surface of the epitaxial layer, and a first metal layer M1 and the like may be fabricated on the lower surface of the substrate 1, which may be specifically fabricated in combination with the related art, and will not be described herein.
The steps 11 to 15 are one method of manufacturing the transistor shown in fig. 3, but the present application is not limited thereto, and other manufacturing methods may be used for manufacturing. The transistor of other structure may be fabricated by performing corresponding fabrication in combination with the related art, or by performing corresponding adjustment with reference to steps 11 to 15.
For example, in the case of using the intermediate dielectric layer b with a smaller dielectric coefficient for the interlayer dielectric layer 20 between the gate electrode G and the field plate FP in fig. 7 and 8, the manufacturing manner is basically the same as that of the foregoing steps 11 to 15, except that the etching back depth of the second dielectric layer a2 in step 14 is different, and only the thinner second dielectric layer a2 can be remained as a part of the interlayer dielectric layer 20 on the surface of the field plate FP by controlling the etching back depth (corresponding to fig. 7), or the second dielectric layer a2 on the surface of the field plate FP is completely removed by etching back (corresponding to fig. 8), and then the intermediate dielectric layer b is formed by CVD and etching back using a dielectric material with a relatively lower dielectric coefficient.
Example two
The second embodiment provides a semiconductor device using a split gate (double gate) trench type field effect transistor.
As shown in fig. 14, the split gate (double gate) trench field effect transistor is mainly different from the split gate (single gate) trench field effect transistor in the first embodiment in that the transistor is provided with two gates in the trench T: a first gate G1 and a second gate G2. The first grid electrode G1 and the second grid electrode G2 are positioned on two sides of the top end of the field plate FP, and an interlayer dielectric layer 20 is arranged between the first grid electrode G1, the second grid electrode G2 and the field plate FP in the horizontal direction; i.e. the interlayer dielectric layer 20 is arranged above the isolation dielectric layer 10.
It will be appreciated here that, within the recess T, the first gate G1 and the second gate G2 are distributed on both sides in the lateral direction of the field plate FP, whereas in the longitudinal direction the first gate G1, the second gate G2 substantially coincide with the direction of extension of the field plate FP and substantially coincide with the length of the field plate FP. In addition, the first gate G1 and the second gate G2 may be connected to the surface of the epitaxial layer 2, so that the first gate G1 and the second gate G2 may be in an equipotential body, and normal operation of the transistor is ensured.
In the second embodiment, the arrangement of the isolation dielectric layer 10 on the side surface of the field plate FP is basically consistent with that in the first embodiment, and the dielectric coefficient of the isolation dielectric layer 10 is increased from bottom to top, so that the purpose of changing the capacitance of a unit area can be achieved, the modulation effect of the field plate on the electric field is further changed, a new peak electric field is introduced at the position where the dielectric constant of the isolation dielectric layer 10 changes, so that multimodal or even rectangular distribution of breakdown electric fields is realized, and the breakdown voltage of the device is improved.
The second embodiment of the present application further provides a method for manufacturing a transistor as shown in fig. 14, and as shown in fig. 15, the method may include:
step 21, referring to fig. 16 (a), a substrate 1 is provided, and an epitaxial layer 2 is grown on the surface of the substrate 1.
The above step 21 is substantially identical to the step 11 in the first embodiment, and reference may be made to the description of the step 11, which is not repeated here.
In step 22, referring to fig. 16 (b) and (c), a trench T is formed on the surface of the epitaxial layer 2, and a first dielectric layer a1 is formed in the inner wall of the trench T.
The above step 22 is substantially identical to the step 12 in the first embodiment, and reference may be made to the description of the step 12, which is not repeated here.
In step 23, referring to fig. 16 (d), a field plate FP is formed in the recess T in which the first dielectric layer a1 is formed, and the first dielectric layer a1 is etched back to a depth below the top of the field plate FP.
Illustratively, in some possible implementations, referring to (d) in fig. 16, the step 23 may include: depositing a layer of polysilicon by LP-CVD (low pressure chemical vapor deposition ) and forming a good fill for the trench T; then, the polysilicon is etched back (etch-back) to a certain depth d0 (typically slightly below the upper surface of epitaxial layer 2) without a mask to form field plate FP; the first dielectric layer a1 is then etched back to another specific depth d1 in a self-aligned manner, and d1> d0. Optionally, the field plate polysilicon may be CMP (chemical mechanical polishing ) prior to back etching to improve the planarity of its upper surface.
Step 24, referring to fig. 16 (e) and (f), a second dielectric layer a2 is formed on the side surface of the field plate FP and on the surface of the first dielectric layer a1, and the second dielectric layer a2 is etched back to a depth below the top of the field plate FP; the dielectric coefficient of the second dielectric layer a2 is larger than that of the first dielectric layer a 1.
It will be appreciated that the gate (G1, G2) needs to be formed on top of the second dielectric layer a2 later, and thus the depth of the top of the second dielectric layer a2 formed in step 24 should meet the requirement of manufacturing the gate (G1, G2) later.
Illustratively, in some possible implementations, the step 24 may include: referring to fig. 16 (e), a second dielectric layer a2 is deposited by CVD and a good filling of the trench T is formed. The second dielectric layer a2 may be Si with a dielectric constant of about 7.5 3 N 4 . After the second dielectric layer a2 is deposited, CMP may be performed on the surface of the second dielectric layer a2 as needed to improve the flatness of the upper surface thereof. Then, referring to fig. 16 (f), the second dielectric layer a2 may be etched back to another specific depth d2 in a self-aligned manner, and d2<d1。
In step 25, referring to fig. 17 (a) and (b), a gate dielectric layer 12 is formed on the side walls of the field plate FP and the trench T, and a first gate G1 and a second gate G2 are formed on both sides of the field plate FP.
Illustratively, in some possible implementations, the step 25 may include: referring to fig. 17 (a), a gate dielectric layer 12 is grown on the exposed sidewall of the trench T and the upper surface of the epitaxial layer 2 by thermal oxidation, and the gate dielectric layer 12 may be formed of SiO 2 . Alternatively, the growth of the sacrificial oxide layer may be performed once and removed before the gate dielectric layer 12 is grown. Of course, the gate dielectric layer 12 may also be formed by CVD. Then, referring to fig. 17 (b), polysilicon is deposited on the surface of the second dielectric layer a2 by LP-CVD on both sides of the field plate FP to form a good filling of the trench; next, the polysilicon is etched back to a certain depth (generally slightly below the upper surface of the epitaxial layer 2) without a mask, thereby forming a first gate G1 and a second gate G2 on both sides of the field plate FP, respectively. Optionally byThe photolithographic masks form the gates (G1, G2) while the polysilicon pattern that needs to be preserved may be defined for the gate connection structure or other functions.
It can be understood that, in the above manufacturing process, the gate dielectric layer 12 is formed and the interlayer dielectric layer 20 is formed at the same time, that is, the interlayer dielectric layer 20 and the gate dielectric layer 12 are manufactured by the same manufacturing process, and the materials of the gate dielectric layer 12 and the interlayer dielectric layer 20 are the same.
Of course, other manufacturing processes after the manufacturing of the gate electrodes (G1, G2) is completed may be combined with the related art to manufacture the gate electrodes, which is not described herein.
Other related structures of the transistor in the second embodiment, such as the isolation dielectric layer 10, the isolation buffer layer 11, the interlayer dielectric layer 20, the step structure 30, etc., may be referred to in the related content of the first embodiment, and will not be described herein.
Example III
The third embodiment provides a semiconductor device using a non-split gate trench type field effect transistor (non-split gate trench MOS).
As shown in fig. 18, the main difference between the non-split-gate trench type field effect transistor and the split-gate (single gate) trench type field effect transistor in the first embodiment is that the gate G located in the trench T is connected to the top of the field plate FP, and the two may be a connected integral structure. In this case, the gate G and the field plate FP do not have an interlayer dielectric layer.
In the third embodiment, the arrangement of the isolation dielectric layer 10 on the side surface of the field plate FP is basically the same as that in the first embodiment, and the dielectric coefficient of the isolation dielectric layer 10 is increased from bottom to top, so that the purpose of changing the capacitance of a unit area can be achieved, the modulation effect of the field plate on the electric field is further changed, a new peak electric field is introduced at the position where the dielectric constant of the isolation dielectric layer 10 changes, so that multimodal or even rectangular distribution of breakdown electric fields is realized, and the breakdown voltage of the device is improved.
The third embodiment of the present application further provides a method for manufacturing a transistor as shown in fig. 18, and as shown in fig. 19, the method may include:
step 31, referring to fig. 20 (a), a substrate 1 is provided, and an epitaxial layer 2 is grown on the surface of the substrate 1.
The above step 31 is substantially identical to the step 11 in the first embodiment, and reference may be made to the description of the step 11, which is not repeated here.
In step 32, referring to fig. 20 (b) and (c), a trench T is formed on the surface of the epitaxial layer 2, and a first dielectric layer a1 is formed in the inner wall of the trench T.
The above step 32 is substantially identical to the step 12 in the first embodiment, and reference may be made to the description of the step 12, which is not repeated here.
In step 33, referring to fig. 20 (d), a dummy field plate FP 'is formed in a recess formed on the inner wall of the first dielectric layer a1, and the first dielectric layer a1 is etched back to a depth below the top of the dummy field plate FP'.
Illustratively, in some possible implementations, referring to (d) in fig. 20, the step 33 may include: depositing a layer of polysilicon by LP-CVD (low pressure chemical vapor deposition ) and forming a good fill for the trench T; then, etching back (etch-back) the polysilicon to a certain depth d0 (generally lower than the upper surface of epitaxial layer 2) without a mask to form a dummy field plate FP' (which may also be referred to as a sacrificial field plate); the first dielectric layer a1 is then etched back to another specific depth d1 in a self-aligned manner, and d1> d0.
Step 34, referring to fig. 20 (e) and (f), a second dielectric layer a2 is formed on the side surface of the dummy field plate FP 'and on the surface of the first dielectric layer a1, and the second dielectric layer a2 is etched back to a depth below the top of the dummy field plate FP'; the dielectric coefficient of the second dielectric layer a2 is larger than that of the first dielectric layer a 1.
Illustratively, in some possible implementations, step 34 may include: referring to fig. 20 (e), a second dielectric layer a2 is deposited by CVD and a good filling of the trench T is formed. The second dielectric layer a2 may be Si with a dielectric constant of about 7.5 3 N 4 . After depositing the second dielectric layer a2, the surface of the second dielectric layer a2 may be subjected to CMP as needed to raise the upper surface thereofFlatness of the face. Then, referring to fig. 20 (f), the second dielectric layer a2 may be etched back to another specific depth d2 in a self-aligned manner, and d2<d1。
In step 35, referring to fig. 21 (a) and (b), a gate dielectric layer 12 is formed on the sidewall of the trench T, and an integral structure of the gate G and the field plate FP is formed after the dummy field plate FP' is removed.
Illustratively, in some possible implementations, the step 35 may include: referring to fig. 21 (a), a gate dielectric layer 12 is grown by thermal oxidation on the exposed sidewalls of the trench T and the upper surface of the epitaxial layer 2, and the dummy field plate FP' is removed. The gate dielectric layer 12 may be SiO 2 . Alternatively, the growth of the sacrificial oxide layer may be performed once and removed before the gate dielectric layer 12 is grown. Of course, the gate dielectric layer 12 may also be formed by CVD. Then, as shown in (b) of fig. 21, redeposition of the polysilicon by LP-CVD forms a good filling of the trench; next, the polysilicon is etched back to a certain depth (typically slightly below the upper surface of epitaxial layer 2) without a mask, thereby forming an integral structure of field plate FP with gate G within trench T. Alternatively, the polysilicon pattern that needs to be preserved for the gate connection structure or other functions may be defined while the gate G is formed through the photolithographic mask.
Of course, other manufacturing processes after the manufacture of the gate electrode G is completed may be performed in combination with related technologies, which will not be described herein.
Other related arrangement structures of the transistor in the third embodiment, such as the isolation dielectric layer 10, the isolation buffer layer 11, the step structure 30, etc., may be referred to in the related content of the first embodiment, and will not be described herein.
Example IV
The fourth embodiment provides a semiconductor device employing a double trench field effect transistor.
Fig. 22 is a schematic structural diagram of a double trench type field effect transistor in a semiconductor device (a single cell is shown in a dashed line box). As shown in fig. 22, the main difference between the dual trench type field effect transistor and the split gate (single gate) trench type field effect transistor in the first embodiment is that the gate G and the field plate FP are located in different trenches.
As shown in fig. 22, the transistor is provided with a first trench T1 and a second trench T2 in parallel on the surface of the epitaxial layer 2. Wherein the depth of the second trench T2 is smaller than the depth of the first trench T1; the field plate FP is located in the first trench T1, and the gate G is located in the second trench T2.
The depth of the second trench T2 is typically shown passing through the well region (P-well) into the surface layer of the drift region (N-drift) to meet the gate G arrangement requirements. The depth of the first trench T1 should extend into the drift region (N-drift) to ensure the set requirements of the field plate FP.
In the fourth embodiment, the arrangement of the isolation dielectric layer 10 on the side surface of the field plate FP is basically the same as that in the first embodiment, and the dielectric coefficient of the isolation dielectric layer 10 is increased from bottom to top, so that the purpose of changing the capacitance of a unit area can be achieved, the modulation effect of the field plate on the electric field is further changed, a new peak electric field is introduced at the position where the dielectric constant of the isolation dielectric layer 10 changes, so that multimodal or even rectangular distribution of the breakdown electric field is realized, and the breakdown voltage of the device is improved.
For the fabrication method of the transistor in this embodiment, reference may be made to the related fabrication method and related technology, and the description thereof will not be repeated here.
Other related arrangement structures of the transistor in the fourth embodiment, such as the isolation dielectric layer 10, the isolation buffer layer 11, the interlayer dielectric layer 20, the step structure 30, etc., may be referred to in the related content of the first embodiment, and will not be described herein.
Example five
The fifth embodiment provides a semiconductor device employing an insulated gate bipolar transistor (insulated gate bipolar transistor, IGBT).
Fig. 23 is a schematic structural diagram of two IGBTs (i.e., two cells) connected in parallel in a semiconductor device. As shown in fig. 23, the design of the gate G and the field plate FP in the IGBT is similar to the embodiment, and the isolation dielectric layer 10 on the side surface of the field plate FP is made of a dielectric material with a dielectric coefficient increased and changed from bottom to top, so that the purpose of changing the capacitance of a unit area can be achieved, the modulation effect of the field plate on the electric field can be further changed, a new peak electric field is introduced at the position where the dielectric constant of the isolation dielectric layer 10 changes, so that multimodal or even rectangular distribution of the electric field is realized, and the breakdown voltage of the device is improved.
The IGBT is mainly different from the split gate (single gate) trench field effect transistor in the first embodiment in that: generally, the IGBT may directly employ a lightly doped N-type semiconductor substrate as a field stop (field stop), and a P-type doped layer is provided on the lower surface of the substrate as an emission layer (injection); other film structures (e.g., M1, M2, P-well, N-drift, etc.) are substantially the same as those of the first embodiment, and will not be described herein.
It will be appreciated that since the IGBT and the aforementioned field effect transistor operate on different principles, the same (or similar) layers may not function exactly the same even if they are provided. For example, in this IGBT, the first metal layer M1 and the second metal layer M2 function as a collector (collector) and an emitter (emitter), respectively.
The manufacturing method of the IGBT in this embodiment may refer to the related manufacturing method and related technology described above, and will not be described here again.
Other related structures of the transistor in the fifth embodiment, such as the isolation dielectric layer 10, the isolation buffer layer 11, the interlayer dielectric layer 20, the step structure 30, etc., may be referred to in the related content of the first embodiment, and will not be described herein.
Example six
The sixth embodiment provides a semiconductor device employing a trench MOS barrier schottky diode (trench MOS barrier schottky diode, TMBS).
Fig. 24 is a schematic structural diagram of two trench MOS barrier schottky diodes (i.e., two cells) connected in parallel in a semiconductor device. As shown in fig. 24, the design of the field plate FP in the trench MOS barrier schottky diode (hereinafter may be simply referred to as a diode) is similar to that of the embodiment, and the isolation dielectric layer 10 disposed on the side surface of the field plate FP adopts a dielectric material with a dielectric coefficient that increases from bottom to top, so that the purpose of changing the capacitance of a unit area can be achieved, and further, the modulation effect of the field plate on the electric field is changed, and a new spike electric field is introduced at the position where the dielectric constant of the isolation dielectric layer 10 changes, so as to realize multimodal or even rectangular distribution of the electric field, and improve the breakdown voltage of the device.
The diode is mainly different from the transistor in the first embodiment in that the epitaxial layer 2 may include only a drift region (N-drift) of an N-type lightly doped layer, and the second metal layer M2 is directly disposed on the upper surface of the epitaxial layer 2 as an anode (anode) of the diode and is connected (contacted) with the field plate FP, and the first metal layer M1 is used as a cathode (cathode) of the diode.
For the fabrication method of the diode in this embodiment, reference may be made to the related fabrication method and related technology, and the description thereof will not be repeated here.
Other relevant arrangement structures of the diode in this embodiment, such as the isolation dielectric layer 10, the isolation buffer layer 11, the step structure 30, etc., may be referred to in the related content of the first embodiment, and will not be described herein.
The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes and substitutions are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (22)
1. A semiconductor device is characterized by comprising a split gate trench type field effect transistor; wherein, divide gate trench type field effect transistor includes:
A substrate;
the epitaxial layer is arranged on the substrate, and a groove is formed in one side, far away from the substrate, of the epitaxial layer;
the field plate is positioned in the groove;
the isolation medium layer at least covers the side face of the field plate;
the isolation dielectric layer comprises a first dielectric layer and a second dielectric layer which are covered on the side face of the field plate, the first dielectric layer is close to the bottom of the groove relative to the second dielectric layer, and the dielectric coefficient of the second dielectric layer is larger than that of the first dielectric layer.
2. The semiconductor device according to claim 1, wherein,
the split gate trench field effect transistor further includes: a first gate and a second gate located within the trench;
the first grid electrode and the second grid electrode are positioned on two sides of the top end of the field plate, and interlayer dielectric layers are arranged among the first grid electrode, the second grid electrode and the field plate;
and the interlayer dielectric layer is positioned at one side of the isolation dielectric layer far away from the bottom of the groove.
3. The semiconductor device according to claim 1, wherein,
the split gate trench field effect transistor further includes: a gate located within the trench;
The grid electrode is positioned on one side of the field plate far away from the substrate, and an interlayer dielectric layer is arranged between the grid electrode and the field plate.
4. A semiconductor device according to any one of claims 1 to 3, wherein,
the isolation medium layer further comprises a third medium layer covering the side face of the field edge;
the third dielectric layer is far away from the bottom of the groove relative to the second dielectric layer; the dielectric coefficient of the third dielectric layer is larger than that of the second dielectric layer.
5. A semiconductor device according to any one of claims 1 to 4, wherein,
at least one of the first dielectric layer or the second dielectric layer has a graded dielectric coefficient;
the graded dielectric coefficient gradually increases along the direction from the bottom of the groove to the notch.
6. The semiconductor device according to claim 5, wherein,
the first dielectric layer is made of a first dielectric material;
the second dielectric layer is made of the multi-compound dielectric material, and the atomic or molecular components of the multi-compound dielectric material gradually change along the direction from the bottom of the groove to the notch.
7. A semiconductor device according to any one of claims 3 to 6, wherein,
And an isolation buffer layer is arranged between the isolation medium layer and the side wall of the groove in the side surface area close to the top end of the field plate.
8. The semiconductor device according to claim 7, wherein,
the isolation buffer layer adopts SiO 2 。
9. A semiconductor device according to any one of claims 3 to 8, wherein,
the isolation dielectric layer extends and covers to the top surface of the field plate.
10. A semiconductor device according to any one of claims 3 to 9, wherein,
the interlayer dielectric layer comprises an intermediate dielectric layer;
the dielectric coefficient of the intermediate dielectric layer is smaller than that of the second dielectric layer.
11. The semiconductor device of claim 10, wherein the semiconductor device comprises,
the intermediate dielectric layer covers the top surface of the field plate.
12. A semiconductor device according to any one of claims 1 to 11, wherein,
at least one ladder structure is arranged on the side face of the field plate;
of the two stepped surfaces of the stepped structure, the stepped surface on the side close to the notch of the groove protrudes from the stepped surface on the side close to the bottom of the groove.
13. A semiconductor device according to any one of claims 1 to 12, wherein,
The split gate trench field effect transistor further includes: the first metal layer, the second metal layer and the insulating medium layer; the first metal layer is arranged on one side of the substrate far away from the epitaxial layer, and the insulating medium layer is arranged between the epitaxial layer and the second metal layer;
the substrate is made of an N-type lightly doped semiconductor material; the epitaxial layer is divided into: an N-type lightly doped layer, a P-type doped layer and an N-type heavily doped layer; wherein the N-type lightly doped layer is adjacent to the substrate relative to the N-type heavily doped layer; the field plate is positioned in the area where the N-type lightly doped layer is positioned;
or the substrate is a P-type lightly doped semiconductor material; the epitaxial layer is divided into: a P-type lightly doped layer, an N-type doped layer, and a P-type heavily doped layer; wherein the P-type lightly doped layer is close to the substrate relative to the P-type heavily doped layer; the field plate is located in the region where the P-type lightly doped layer is located.
14. A semiconductor device comprising a trench-type electronic component;
the trench type electronic component includes:
a substrate;
the epitaxial layer is arranged on the substrate, and a first groove is formed in one side, far away from the substrate, of the epitaxial layer;
A field plate located within the first trench;
the isolation medium layer at least covers the side face of the field plate;
the isolation medium layer comprises a first medium layer and a second medium layer which are covered on the side face of the field plate, and the first medium layer is close to the bottom of the first groove relative to the second medium; the dielectric coefficient of the second dielectric layer is larger than that of the first dielectric layer.
15. The semiconductor device of claim 14, wherein the semiconductor device comprises,
the groove type electronic element is a non-split gate groove type field effect transistor;
the trench field effect transistor further comprises a gate;
the grid is positioned in the first groove, and the grid is connected with the top of the field plate.
16. The semiconductor device of claim 14, wherein the semiconductor device comprises,
the groove type electronic element is a double groove type field effect transistor;
the double-groove type field effect transistor further comprises a grid electrode;
the epitaxial layer is further provided with a second groove at one side far away from the substrate; the second groove is arranged in parallel with the first groove; the depth of the second groove is smaller than that of the first groove;
The grid electrode is positioned in the second groove.
17. The semiconductor device of claim 14, wherein the semiconductor device comprises,
the groove type electronic element is a groove MOS barrier Schottky diode;
the trench MOS barrier Schottky diode further comprises a first metal layer and a second metal layer;
the first metal layer is positioned on one side of the substrate far away from the epitaxial layer, and the second metal layer is positioned on one side of the epitaxial layer far away from the substrate;
the top of the field plate is connected with the second metal layer.
18. The semiconductor device of claim 14, wherein the semiconductor device comprises,
the groove type electronic element is an insulated gate bipolar transistor;
the substrate is made of an N-type semiconductor material;
the insulated gate bipolar transistor further comprises a grid electrode and a P-type semiconductor layer;
the grid electrode is positioned in the first groove, the grid electrode is positioned at one side of the field plate far away from the bottom of the first groove, and an interlayer dielectric layer is arranged between the grid electrode and the field plate;
the P-type semiconductor layer is positioned on one side of the substrate away from the epitaxial layer;
the epitaxial layer is sequentially provided with an N-type lightly doped region, a P-type doped region and an N-type heavily doped region along the direction far away from the substrate.
19. An electronic device comprising a printed wiring board and the semiconductor device according to any one of claims 1 to 18; the semiconductor device is electrically connected with the printed wiring board.
20. A method of fabricating a semiconductor device, comprising:
providing a substrate and growing an epitaxial layer on the surface of the substrate;
forming a groove on the surface of the epitaxial layer, and forming a first dielectric layer in the inner wall of the groove;
forming a field plate in the groove formed with the first dielectric layer, and etching the first dielectric layer back to a depth below the top of the field plate;
forming a second dielectric layer on the surface of the first dielectric layer, which is positioned on the side surface of the field plate; the dielectric coefficient of the second dielectric layer is larger than that of the first dielectric layer.
21. The method of manufacturing a semiconductor device according to claim 20, wherein,
and forming a second dielectric layer on the side surface of the field plate and the surface of the first dielectric layer, wherein the second dielectric layer comprises the following components:
and depositing a multi-compound dielectric material on the side surface of the field plate and the surface of the first dielectric layer, and controlling atomic or molecular components in the multi-compound dielectric material in the deposition process to form a second dielectric layer with gradually increased dielectric coefficient.
22. The method for manufacturing a semiconductor device according to claim 20 or 21, wherein,
after forming the isolation dielectric layer including the first dielectric layer and the second dielectric layer on the side surface of the field plate, the manufacturing method further includes:
and forming an intermediate dielectric layer on the top of the field plate, wherein the dielectric coefficient of the intermediate dielectric layer is smaller than that of the second dielectric layer.
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| CN202210080586.1A CN116525672A (en) | 2022-01-24 | 2022-01-24 | Semiconductor device, manufacturing method thereof and electronic equipment |
| PCT/CN2022/129022 WO2023138153A1 (en) | 2022-01-24 | 2022-11-01 | Semiconductor device and manufacturing method therefor, and electronic device |
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| CN107170827B (en) * | 2017-06-08 | 2020-05-26 | 电子科技大学 | Shielding gate VDMOS device for limiting avalanche breakdown point |
| CN108010961A (en) * | 2017-11-30 | 2018-05-08 | 上海华虹宏力半导体制造有限公司 | Shield grid groove MOSFET and its manufacture method |
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| CN216213475U (en) * | 2021-10-14 | 2022-04-05 | 绍兴中芯集成电路制造股份有限公司 | Shielding gate groove type power MOSFET device |
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