CN116525613A - BCD device - Google Patents

BCD device Download PDF

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Publication number
CN116525613A
CN116525613A CN202211056231.5A CN202211056231A CN116525613A CN 116525613 A CN116525613 A CN 116525613A CN 202211056231 A CN202211056231 A CN 202211056231A CN 116525613 A CN116525613 A CN 116525613A
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China
Prior art keywords
hole
bcd
dmos
region
concentration doped
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CN202211056231.5A
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Chinese (zh)
Inventor
莫海锋
冯新
张耀辉
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Suzhou Huatai Electronics Co Ltd
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Suzhou Huatai Electronics Co Ltd
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Priority to CN202211056231.5A priority Critical patent/CN116525613A/en
Publication of CN116525613A publication Critical patent/CN116525613A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7817—Lateral DMOS transistors, i.e. LDMOS transistors structurally associated with at least one other device

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The embodiment of the application provides a BCD device, and relates to the technical field of semiconductors. The BCD device at least comprises the following components connected in sequence: the device comprises a substrate region, a second concentration doped buried region, a plurality of DMOS device units and a dielectric layer, wherein each DMOS device unit at least comprises: the double-diffused metal oxide semiconductor field effect transistor (DMOS) device is characterized in that a first through hole is formed between two adjacent DMOS device units, penetrates through the dielectric layer and extends to the second concentration doped buried region, and at least conductive materials are filled in the first through hole; and a metal silicide layer is arranged between the inner wall of the first through hole and the filler made of the conductive material. The technical problem of low surface utilization rate of the existing BCD device is solved, and the technical effect of improving the surface utilization rate of the BCD device is achieved.

Description

BCD device
Technical Field
The application relates to the technical field of semiconductors, in particular to a BCD device.
Background
BCD (bipolar CMOS DMOS) is a semiconductor device integrating bipolar transistor, CMOS device and DMOS device on one chip, and combines the advantages of high transconductance, strong load driving capability, high CMOS integration level, low power consumption, high-voltage and high-current driving of the DMOS device and the like.
Conventional DMOS devices typically connect a substrate to a metal layer on the surface by means of heavy doping, thereby achieving electron conduction. The resistor of the DMOS device mainly comprises a drift region resistor and an interconnection resistor, and for a low-voltage device, the drift region is thinner, the drift region resistor is reduced, the duty ratio of the interconnection resistor is greatly increased, and the DMOS device is not negligible in actual products; for a high-voltage device, the drift region is thicker, the resistance of the drift region is increased, the thickness of the interconnection is also increased, deep doping is difficult to realize by ion implantation, and the interconnection resistance is also increased. The general measure for this situation is to increase the ion implantation depth in the ultra-high temperature thermal process, but as the ion depth increases, the lateral diffusion of ions also increases, the area of the interconnection area increases, and the surface area of the DMOS device correspondingly increases, so that the number of devices set per unit area of the surface of the BCD device also correspondingly decreases.
Thus, current BCD device surface utilization is low.
Disclosure of Invention
In order to solve the technical problems, a BCD device is provided in an embodiment of the present application.
In a first aspect of the embodiments of the present application, there is provided a BCD device, at least including: the device comprises a substrate region, a second concentration doped buried region, a plurality of DMOS device units and a dielectric layer, wherein each DMOS device unit at least comprises: the double-diffused metal oxide semiconductor field effect transistor (DMOS) device is characterized in that a first through hole is formed between two adjacent DMOS device units, penetrates through the dielectric layer and extends to the second concentration doped buried region, and at least conductive materials are filled in the first through hole; and a metal silicide layer is arranged between the inner wall of the first through hole and the filler made of the conductive material.
In an alternative embodiment of the present application, the metal silicide layer is a titanium silicide layer.
In an alternative embodiment of the present application, the conductive material is tungsten.
In an optional embodiment of the present application, a depth of the first through hole in the second concentration doped buried region is not less than a thickness of an epitaxial layer where the DMOS device unit is located.
In an alternative embodiment of the present application, the number of the first through holes is positively correlated with the number of the DMOS device cells.
In an alternative embodiment of the present application, the depth of the first via is positively correlated to the number of DMOS device cells.
In an alternative embodiment of the present application, the positive correlation coefficient between the depth of the first through hole and the number of DMOS device cells is 5% to 10%.
In an alternative embodiment of the present application, the substrate region is a P-type substrate, and the depth of the first through hole in the second concentration doped buried region is not greater than 95% of the thickness of the second concentration doped buried region.
In an optional embodiment of the present application, the substrate region is an N-type substrate, and the depth of the first through hole in the second concentration doped buried region is not greater than the thickness of the second concentration doped buried region.
In an alternative embodiment of the present application, a second through hole is annularly formed at an outer edge portion of the BCD device, wherein a first end of the second through hole penetrates through a surface of the BCD device, and a second end of the second through hole extends to a substrate region of the BCD device; the second through hole is filled with a metal material.
In the BCD device, a first through hole is formed between two adjacent DMOS device units, and at least a conductive material is filled in the first through hole, and electrons in the first concentration doped drift region and the second concentration doped buried region can be led into the semiconductor surface through the first through hole and the conductive material in the first through hole, so that the whole DMOS device units are interconnected.
In the first aspect, in the embodiment of the disclosure, the first through hole is provided, and the conductive material is filled in the first through hole, so that interconnection of DMOS device units is completed through the first through hole and the conductive material in the first through hole, that is, the drain electrode in the DMOS device is led to the surface, so that connection with other circuits or devices is facilitated, no additional packaging is needed, and the cost is lower;
in a second aspect, the electron flow direction of the DMOS device unit provided in the embodiment of the present application is sequentially along the first concentration doped drift region, the second concentration doped buried region and the first through hole, compared with the conventional path, in the epitaxial region, that is, the lateral diffusion in the first concentration doped drift region and the second concentration doped buried region is less, so that the resistance of the drift region is reduced, and the total resistance of the DMOS device unit is reduced on the basis of ensuring the performances of the BCD device; meanwhile, the thicknesses of the semiconductor epitaxial layer, namely the first concentration doped drift region and the second concentration doped buried region in the embodiment of the application are not excessively limited, the semiconductor epitaxial layer can be specifically set according to actual needs, the flexibility is higher, the preparation precision requirement is low, and the cost is further reduced;
in the third aspect, since the breakdown voltage is mainly affected by the distance between the device unit and the substrate, the breakdown voltage in the conventional semiconductor device is generally between 20V and 50V, the breakdown voltage is less than 20V, the semiconductor device cannot work normally, if the breakdown voltage is greater than 50V, the thickness between the device unit and the substrate needs to be increased, namely, an epitaxial layer is increased, and the cost is high; according to the embodiment of the application, the change of the electron flow direction is changed by arranging the first through hole filled with the conductive material, the breakdown voltage of the semiconductor can be adjusted to 600V by prolonging the depth of the first through hole, and is far greater than the maximum bearing voltage of 60V in the traditional scheme, but the cost of the conductive material is lower relative to doping ions and the like in the epitaxial layer, so that the electrical performance of the DMOS device unit is greatly improved on the premise of reducing the cost;
in the fourth aspect, since the first through hole filled with the conductive material is formed, compared with the 60V breakdown voltage of the traditional BCD device, the BCD device provided in the embodiment of the present application has stronger voltage tolerance, so that the interval distance between two electrodes in the semiconductor surface, that is, the interval distance between the gate and the source, can be smaller than that in the traditional manner, so that the surface area of the DMOS device unit is smaller, and more device units can be configured in a unit area, thereby solving the technical problem that the surface utilization rate of the traditional BCD device is lower, and achieving the technical effect of improving the surface utilization rate of the BCD device; in a fifth aspect, the substrate material of the DMOS device is generally silicon, and in this embodiment of the present application, by disposing a metal silicide layer between the substrate material and the inner wall of the first via hole, ohmic contact is formed between the substrate material and an epitaxial layer, a buried layer, and the substrate in the semiconductor device, so as to reduce contact resistance, further reduce the total resistance of the DMOS device unit in this embodiment of the present application, and further reduce the resistance of the BCD device.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute an undue limitation to the application. In the drawings:
fig. 1 is a schematic structural diagram of a conventional BCD device of the present application;
fig. 2 is a schematic structural diagram of a BCD device provided in an embodiment of the present application;
fig. 3 is a schematic structural diagram of another BCD device with ohmic contact according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of another BCD device with a second through hole according to an embodiment of the present application;
fig. 5 is a structural top view of a BCD device with a second through hole according to an embodiment of the present application.
Detailed Description
In the course of implementing the present application, the applicant has found that the surface utilization of the current BCD device is low.
In view of the above problems, embodiments of the present application provide a BCD device. In order to make the objects, technical solutions and advantages of the present application more apparent, the following embodiments are used to further describe an atomic operation control circuit, a system and an electronic device of the present application in detail by referring to the accompanying drawings. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.
The numbering of the components itself, e.g. "first", "second", etc., is used herein merely to distinguish between the described objects and does not have any sequential or technical meaning. The terms "coupled" and "connected," as used herein, are intended to encompass both direct and indirect coupling (coupling), unless otherwise indicated. In the description of the present application, it should be understood that the terms "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," etc. indicate or refer to an orientation or positional relationship based on that shown in the drawings, merely for convenience of description and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present application.
In this application, unless expressly stated or limited otherwise, a first feature "up" or "down" a second feature may be the first and second features in direct contact, or the first and second features in indirect contact via an intervening medium. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.
BCD (BJT CMOS DMOS) devices are semiconductor devices in which BJT (Bipolar Junction Transistor ) devices, CMOS (Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductor) devices and DMOS (double-diffused, metal Oxide Semiconductor, double-diffused metal oxide semiconductor) devices are integrated on a single chip, and combine the advantages of high transconductance, high load driving capability, high CMOS device integration, low power consumption, high-voltage and high-current driving of the DMOS devices.
Where the drive and control circuitry is typically implemented by CMOS devices and BJT devices and the high power output devices are typically implemented by DMOS devices 120, it is often necessary to route the drain of the DMOS devices from the back side of the BCD devices to the surface to facilitate connection to other circuits or electronics. Referring to fig. 1, a BCD device 10 in a conventional manner includes: trench gate 101, gate oxide 102, N-type heavily doped source region 103, P-type heavily doped body contact region 104, P-type lightly doped body region (not shown in fig. 1), N-type lightly doped drift region 106, N-type heavily doped buried layer region 107, substrate 108, N-type heavily doped connection region 109, connection body 110, metal layer 111, dielectric layer 112. The BCD device 10 is heavily doped in epitaxy and connects the substrate 108 and the metal layer 111 on the surface of the BCD device 10 via the connection body 110.
However, the resistor of the DMOS device 120 is mainly composed of a drift region resistor and an interconnection resistor, and for a low-voltage device, the drift region is thinner, the drift region resistor is reduced, the duty ratio of the interconnection resistor is greatly increased, and the resistor is not negligible in an actual product; for a high-voltage device, the drift region is thicker, the resistance of the drift region is increased, the thickness of the interconnection is also increased, deep doping is difficult to realize by ion implantation, and the interconnection resistance is also increased. A common measure for this is to increase the ion implantation depth during the ultra-high temperature thermal process, but as the ion depth increases, the lateral diffusion of ions increases, and the area of the interconnect region increases, so that the surface area of DMOS device 120 increases, and the number of devices per unit area set on the surface of BCD device 10 decreases accordingly. Thus, current BCD devices 10 have low surface utilization.
In order to solve the technical problem that the surface utilization rate of the BCD device 10 is low at present, the embodiment of the present application provides a BCD device 10, so as to improve the surface utilization rate of the BCD device 10.
Referring to fig. 2, the BCD device 20 provided in the embodiment of the present application at least includes: the substrate region 201, the second concentration doped buried region 202, a plurality of DMOS device cells 203 and the dielectric layer 204, wherein each DMOS device cell 203 at least comprises: the first concentration doped drift region 2031 having a concentration smaller than that of the second concentration doped buried region 202, and the double-diffused metal oxide semiconductor field effect transistor DMOS device are characterized in that a first through hole 205 is formed between two adjacent DMOS device units 203, the first through hole 205 penetrates through the dielectric layer 204 and extends to the second concentration doped buried region 202, and at least the first through hole 205 is filled with a conductive material 206. Of course, other functional layers, such as trench gate 208, gate oxide 209, N-type heavily doped source region 210, P-type heavily doped body contact region 211, P-type lightly doped body region 212, metal layer 214, etc., are also included in the BCD device 20, which is not intended to be exhaustive.
It should be noted that, the first through hole 205 in the embodiment of the present application is a DMOS device unit 203 formed in the BCD device 20, and is independent of the BJT device and CMOS device in the BCD device 20. The first concentration doped drift region 2031 and the second concentration doped buried region 202 are used for providing current-carrying electrons, and the specific doping ion type can be specifically set according to practical situations. For example, the first concentration doped drift region 2031 is an N-type lightly doped drift region, and the second concentration doped buried region 202 is an N-type heavily doped buried region, or other types of drift regions and doped buried regions, which are not specifically limited and may be specifically selected or set according to practical situations. In this embodiment, the first through hole 205 includes a first end and a second end, the first end is located on the surface of the DMOS device unit 203, and the second end extends to the second concentration doped buried region 202, which should be explained that in this embodiment, the second end of the first through hole 205 may be located in the second concentration doped buried region 202, or may extend through the second concentration doped buried region 202 to reach the substrate region 201, which is not specifically limited in this embodiment, and may be specifically set according to a specific type of DMOS device in the DMOS device unit 203. The conductive material 206 may be, for example, a metal or a metal compound such as tungsten or titanium, or may be a non-metal conductive material 206 such as graphite, which is not specifically limited in the embodiment of the present application, and may be specifically selected according to practical situations, so long as the purpose of conductivity can be achieved. Of course, the DMOS device cells 203 may include other functional components, which are not intended to be exhaustive, and may be specifically configured according to the type of DMOS device cells 203.
Referring to fig. 3, in addition to the above structure, in the BCD device 20 provided in the embodiment of the present application, a metal silicide layer 207 is disposed between the inner wall of the first via 205 and the filler made of the conductive material 206. The substrate material of the DMOS device is typically silicon, and in this embodiment of the present application, a metal silicide layer 207 is disposed between the substrate and the inner wall of the first via 205, so that ohmic contact is formed between the substrate and the epitaxial layer, buried layer, and epitaxial layer in the semiconductor device.
The following briefly describes the operation principle of the BCD device 20 provided in the embodiment of the present application:
in the BCD device 20 of the present embodiment, the gate electrode of the DMOS device in the DMOS device unit 203 forms an inversion layer electron on the surface where the P-type lightly doped region is connected to the gate oxide layer under the control of the applied voltage, so as to form an electron path. The electron flow of the inversion electrons reaches the first concentration doped drift region 2031 from the N-type heavily doped region through the inversion channel, and then reaches the conductive material 206 in the first via 205 through the second concentration doped buried region 202, and the electron flow is introduced into the surface of the DMOS device by the conductive material 206 in the first via 205, so as to facilitate connection with other devices or circuits. Experiments prove that compared with the conventional heavily doped connection mode of the DMOS device, under the same interconnection area, the number of cells covered by each first through hole 205 in the BCD device 20 provided by the embodiment of the present application can be increased by 80% -200%.
In the BCD device 20 provided in this embodiment, a first through hole 205 is formed between two adjacent DMOS device units 203, and at least a conductive material 206 is filled in the first through hole 205, so that electrons in the first concentration doped drift region 2031 and the second concentration doped buried region 202 can be led into the semiconductor surface through the first through hole 205 and the conductive material 206 in the first through hole 205, thereby completing interconnection of the entire DMOS device units 203.
In a first aspect, in the embodiment of the present disclosure, by providing the first through hole 205 and filling the conductive material 206 in the first through hole 205, interconnection of the DMOS device units 203 is completed through the first through hole 205 and the conductive material 206 in the first through hole 205, that is, the drain electrode in the DMOS device is led to the surface, so that connection with other circuits or devices is facilitated, no additional package is required, and the cost is lower;
in the second aspect, the electron flow direction of the DMOS device unit 203 provided in the embodiment of the present application is sequentially along the first concentration doped drift region 2031, the second concentration doped buried region 202 and the first through hole 205, compared with the conventional path, the electron flow direction of the DMOS device unit 203 in the epitaxial region, that is, the first concentration doped drift region 2031 and the second concentration doped buried region 202, is less in lateral diffusion, so that the drift region resistance is reduced, and the total resistance is reduced on the basis of ensuring the performance of the BCD device 20; meanwhile, for the semiconductor epitaxial layer, that is, the thicknesses of the first concentration doped drift region 2031 and the second concentration doped buried region 202 in the embodiment of the application are not excessively limited, the thickness can be specifically set according to actual needs, the flexibility is higher, the preparation precision requirement is low, and the cost is further reduced;
in the third aspect, since the breakdown voltage is mainly affected by the distance between the device unit and the substrate, the breakdown voltage in the conventional semiconductor device is generally between 20V and 50V, the breakdown voltage is less than 20V, the semiconductor device cannot work normally, if the breakdown voltage is greater than 50V, the thickness between the device unit and the substrate needs to be increased, namely, an epitaxial layer is increased, and the cost is high; according to the embodiment of the application, the change of the electron flow direction is changed by forming the first through hole 205 filled with the conductive material 206, the breakdown voltage of the semiconductor can be adjusted to 600V by prolonging the depth of the first through hole 205, and is far greater than the maximum bearing voltage 60V in the traditional scheme, but the cost of the conductive material is lower relative to doped ions and the like in the epitaxial layer, so that the electrical performance of the DMOS device unit 203 is greatly improved on the premise of reducing the cost;
in the fourth aspect, since the first through hole 205 filled with the conductive material 206 is formed, compared with the conventional BCD device, the BCD device 20 provided in this embodiment has a stronger voltage tolerance compared with the 60V breakdown voltage of the conventional BCD device, so that the separation distance between the two electrodes in the semiconductor surface, that is, the separation distance between the gate and the source, can be smaller compared with the separation distance in the conventional manner, so that the surface area of the DMOS device unit 203 is smaller, and more device units can be configured in a unit area, thereby solving the technical problem that the surface utilization rate of the BCD device 20 is lower at present, and achieving the technical effect of improving the surface utilization rate of the BCD device 20; in the fifth aspect, the substrate material of the DMOS device is typically silicon, and in this embodiment, by disposing a metal silicide layer 207 between the substrate material and the inner wall of the first through hole 205, ohmic contact is formed between the substrate material and an epitaxial layer, a buried layer, a substrate, etc. in the semiconductor device, so as to reduce the contact resistance, further reduce the total resistance of the DMOS device unit 203 in this embodiment, and further reduce the resistance of the BCD device 20.
In an alternative embodiment of the present application, the metal silicide layer 207 is a titanium silicide layer, which has stable performance and lower resistance, and can further reduce the resistance between the metal silicide layer 207 and an epitaxial layer, a buried layer, a substrate, etc. in the semiconductor device, and reduce the total resistance of the DMOS device unit 203 in the embodiment of the present application, so as to further improve the performance of the BCD device 20.
In an alternative embodiment of the present application, the conductive material 206 is tungsten, which has stable performance, and does not cause excessive pollution to the preparation of the device during the preparation process of the semiconductor, and belongs to a cleaner metal, so that the cleanliness of the prepared semiconductor device can be improved; meanwhile, the substrate of the DMOS device unit 203 is typically silicon, and the crystal structure of tungsten is relatively close to that of silicon, so in the embodiment of the present application, tungsten is filled in the first through hole 205, so that stability and reliability of the DMOS device unit 203 and the BCD device 20 can be improved.
In an alternative embodiment of the present application, the substrate region 201 is a P-type substrate, the depth of the first via 205 in the second doped region 202 is not greater than 95% of the thickness of the second doped region 202, and the depth of the first via 205 in the second doped region 202 is not less than 50% of the thickness of the second doped region 202.
For the P-type substrate, as the depth of the first through hole 205 entering the second concentration doped buried region 202 increases, the thickness of the second concentration doped buried region 202 needs to be increased, in this embodiment, the depth of the first through hole 205 in the second concentration doped buried region 202 is not greater than 95% of the thickness of the second concentration doped buried region 202, and the allowance of 5% of the thickness of the second concentration doped buried region 202 is reserved, so that the first through hole 205 cannot penetrate the second concentration doped buried region 202 due to long-time electron flow during operation, and reliability of the DMOS device unit 203 and the BCD device 20 is further improved.
Meanwhile, the depth of the first through hole 205 in the second concentration doped buried region 202 is not less than 50% of the thickness of the second concentration doped buried region 202, otherwise, the electron flow width at the bottom of the first through hole is narrower, and the DMOS device unit 203 may not be turned on. In the embodiment of the present application, the depth of the first through hole 205 in the second concentration doped buried region 202 is set to be 50% -95% of the thickness of the second concentration doped buried region 202, so that the maximum electron current width is provided under the condition that the DMOS device unit 203 is normally turned on, and the conductivity of the BCD device 20 provided in the embodiment of the present application is improved to the greatest extent. In an alternative embodiment of the present application, the substrate region 201 is an N-type substrate, and the depth 215 of the first via 205 in the second concentration doped buried region 202 is not greater than the thickness of the second concentration doped buried region 202.
The depth of the first via 205 in the second concentration doped buried region 202 is not greater than the thickness of the second concentration doped buried region 202. For an N-type substrate, as the doping concentration of the second concentration doped buried region 202 and the substrate difference are not large, the second concentration doped buried region can directly enter the buried layer along with the increase of the depth of the first through hole 205, and excessive severity is not required for the process precision when the first through hole 205 is etched, so that the preparation difficulty is further reduced and the preparation cost is further reduced on the premise of ensuring the reliable performance of the DMOS device units 203 and the BCD device 20.
In an alternative embodiment of the present application, the depth 215 of the first through hole 205 in the second concentration doped buried region 202 is not less than the thickness of the epitaxial layer where the DMOS device unit 203 is located.
As shown by the dashed arrows in fig. 2 and 3, the electron flow direction of the DMOS device cell 203 in the on state, the first via 205 and the conductive material 206 in the first via 205 need to penetrate deep into the second concentration doped buried region 202 to provide a wider low-resistance current path, avoiding the increase of the resistance due to the accumulation of current. Particularly, for a part of high-voltage devices, after the epitaxial thickness is increased, the thickness of the first through hole 205 entering the second concentration doped buried region 202 is correspondingly increased, so that the thickness is not smaller than the thickness of the epitaxial layer. Therefore, the depth of the first through hole 205 in the second concentration doped buried region 202 is not less than the thickness of the epitaxial layer where the DMOS device unit 203 is located, so as to ensure the conductivity of the first through hole 205 and the conductive material 206 in the first through hole 205, and further improve the performances of the DMOS device unit 203 and the BCD device 20.
In an alternative embodiment of the present application, the number of the first through holes 205 is positively correlated with the number of the DMOS device cells 203.
A grid represents a cell, and when no voltage is applied, no current exists in the N-type doped source region, the P-type channel region, the N-type drift region and the N-type buried layer. When the voltage of the gate is greater than the threshold voltage, the surface of the connector, which is close to the gate, forms an electron accumulation layer, which is communicated with the source region and the drift region, and under the action of the electric field, source electrons form on-current from the channel, the first concentration doped drift region 2031, the second concentration doped buried region 202, the substrate, and the conductive material 206 in the first through hole 205 to the metal layer. When conducting, electrons of a plurality of cells share one first through hole 205 passage, so in an actual DMOS device, the number of first through holes 205 and the number of DMOS device units 203 are positively correlated, so as to meet the conducting requirement of the device and improve the working performance and reliability of the DMOS device units 203.
In an alternative embodiment of the present application, the depth of the first via 205 is positively correlated with the number of DMOS device cells 203.
The depth of the first through holes 205 into the second concentration doped buried region 202 is positively correlated with the number of cells covered by each first through hole 205, i.e. positively correlated with the DMOS device cells 203, so as to provide an electronic path for conducting the covered DMOS device cells 203, thereby improving the operation performance and reliability of the DMOS device cells 203.
In an alternative embodiment of the present application, the positive correlation coefficient between the depth of the first via 205 and the number of DMOS device cells 203 is 5% to 10%.
The depth of each first through hole 205 into the second concentration doped buried region 202 increases with the increase of the number of the covered DMOS device units 203, and each time one DMOS device unit 203 is added, the depth of the first through hole 205 needs to be increased by 5% -10% of the first through hole, that is, the maximum electronic path is provided for the covered DMOS device units 203 under the conditions of increasing the minimum resistance and the weakest current aggregation effect, so that the working performance and reliability of the DMOS device units 203 are improved.
In an optional embodiment of the present application, a second through hole is annularly formed at an outer edge portion of the BCD device, wherein a first end of the second through hole penetrates through a surface of the BCD device, and a second end of the second through hole extends to a substrate area of the BCD device; and the second through hole is filled with a metal material.
Referring to fig. 4 and fig. 5, in an alternative embodiment of the present application, a second through hole 216 is annularly formed at an outer edge portion of the BCD device 20, wherein a first end of the second through hole 216 penetrates through a surface of the BCD device, a second end of the second through hole 216 extends to a substrate area of the BCD device, and a metal material is filled in the second through hole 216. The metal material may be grounded, and the second through hole 216 filled with the metal material is formed at the outer edge of the BCD device 20, so that the gate, the source, the base, the emitter, or the like inside the BCD device 20 can be covered therein to achieve the purpose of shielding, thereby avoiding the influence of the external environment on the internal electron flow, and further improving the reliability of the BCD device 20 in the embodiment of the present application.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples only represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the claims. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.

Claims (10)

1. A BCD device comprising at least: the device comprises a substrate region, a second concentration doped buried region, a plurality of DMOS device units and a dielectric layer, wherein each DMOS device unit at least comprises: the double-diffused metal oxide semiconductor field effect transistor (DMOS) device is characterized in that a first through hole is formed between two adjacent DMOS device units, penetrates through the dielectric layer and extends to the second concentration doped buried region, and at least conductive materials are filled in the first through hole; and a metal silicide layer is arranged between the inner wall of the first through hole and the filler made of the conductive material.
2. The BCD device of claim 1, wherein the metal silicide layer is a titanium silicide layer.
3. The BCD device of claim 1, wherein the conductive material is tungsten.
4. The BCD device of claim 1, wherein a depth of the first via in the second concentration doped buried region is not less than a thickness of an epitaxial layer in which the DMOS device cells are located.
5. The BCD device of claim 1, wherein the number of first vias is positively correlated to the number of DMOS device cells.
6. The BCD device of claim 1, wherein a depth of the first via is positively correlated to the number of DMOS device cells.
7. The BCD device of claim 6, wherein a positive correlation coefficient of the depth of the first via and the number of DMOS device cells is 5% to 10%.
8. The BCD device of claim 1, wherein the substrate region is a P-type substrate and the first via is no more than 95% of the thickness of the second concentration doped buried region in depth of the second concentration doped buried region.
9. The BCD device of claim 1, wherein the substrate region is an N-type substrate and the first via is no deeper in the second concentration doped buried region than the second concentration doped buried region thickness.
10. The BCD device of claim 1, wherein the BCD device peripheral portion is annularly provided with a second through hole, wherein a first end of the second through hole penetrates the surface of the BCD device, and a second end of the second through hole extends to the substrate region of the BCD device; and the second through hole is filled with a metal material.
CN202211056231.5A 2022-08-30 2022-08-30 BCD device Pending CN116525613A (en)

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CN202211056231.5A CN116525613A (en) 2022-08-30 2022-08-30 BCD device

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Application Number Priority Date Filing Date Title
CN202211056231.5A CN116525613A (en) 2022-08-30 2022-08-30 BCD device

Publications (1)

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