CN116524981A - Test system and test method - Google Patents

Test system and test method Download PDF

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Publication number
CN116524981A
CN116524981A CN202210067893.6A CN202210067893A CN116524981A CN 116524981 A CN116524981 A CN 116524981A CN 202210067893 A CN202210067893 A CN 202210067893A CN 116524981 A CN116524981 A CN 116524981A
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CN
China
Prior art keywords
circuit
read
memory
write
offset
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Pending
Application number
CN202210067893.6A
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Chinese (zh)
Inventor
林士杰
林盛霖
邓力玮
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Realtek Semiconductor Corp
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Realtek Semiconductor Corp
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Priority to CN202210067893.6A priority Critical patent/CN116524981A/en
Publication of CN116524981A publication Critical patent/CN116524981A/en
Pending legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/12015—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising clock generation or timing circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits

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  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

The invention provides a test system, which comprises a plurality of memory circuits and a test circuit. The test circuit is coupled to the memory circuits. The test circuit is used for executing a read-write operation on the memory circuits, and each memory circuit has a read-write starting time point corresponding to the read-write operation. The test circuit is also used for controlling the read-write starting time points of the memory circuits to be different from each other.

Description

Test system and test method
Technical Field
The present invention relates to testing technology, and more particularly, to a testing system and a testing method for testing a memory circuit.
Background
With the development of technology, the amount of memory in electronic devices is increasing. However, the memory may have defects due to the process or other factors. In some related art, a test circuit may be used to test the memory to confirm whether the memory is defective.
Disclosure of Invention
Some embodiments of the invention relate to a test system. The test system includes a plurality of memory circuits and a test circuit. The test circuit is coupled to the memory circuits. The test circuit is used for executing a read-write operation on the memory circuits, and each memory circuit has a read-write starting time point corresponding to the read-write operation. The test circuit is also used for controlling the read-write starting time points of the memory circuits to be different from each other.
Some embodiments of the invention relate to a test method. The test method comprises the following operations: performing a read-write operation on a plurality of memory circuits through a test circuit, wherein each of the memory circuits has a read-write start time point corresponding to the read-write operation; and controlling the read-write start time points of the memory circuits to be different from each other by the test circuit.
In summary, in the present invention, a single test circuit is used to test a plurality of memory circuits, and the test circuit may stagger the read/write start time points of the memory circuits. Therefore, the invention can avoid the excessive instant voltage drop under the condition of not (or a small amount of) increasing the circuit area occupied by the test circuit and not increasing the test time so as to ensure the normal operation of the circuit.
Drawings
In order to make the above and other objects, features, advantages and embodiments of the present invention more comprehensible, the accompanying drawings are described in which:
FIG. 1 is a schematic diagram of a test system according to some embodiments of the invention;
FIG. 2 is a timing diagram of the test system of FIG. 1, shown in accordance with some embodiments of the present invention;
FIG. 3 is a schematic diagram of an offset circuit according to some embodiments of the invention; and
FIG. 4 is a flow chart of a test method according to some embodiments of the invention.
Reference numerals illustrate:
100: test system 120: test circuit 121: enable signal generating circuit
122: address generation circuits 123, 124: offset circuit 300: offset circuit
310: multiplexer 320: register 400: test method
M1, M2, M3: memory circuit
ST1, ST2, ST3: read-write start time points ET1, ET2, ET3: read-write end time point
CLK: clock signals EN1, EN2, EN3: enable signal
AD: address signals DS1, DS2: offset signal
OFFSET1, OFFSET2, OFFSET3, OFFSET4: candidate offset value
OF1, OF2: offset value SS: selection signals S410, S420: operation of
Detailed Description
The term "coupled," as used herein, may also refer to "electrically coupled," and the term "connected," may also refer to "electrically connected. "coupled" and "connected" may also mean that two or more elements co-operate or interact with each other.
Reference is made to fig. 1. FIG. 1 is a schematic diagram of a test system 100, shown according to some embodiments of the invention.
Taking fig. 1 as an example, the test system 100 includes memory circuits M1-M3 and a test circuit 120. Test circuit 120 is coupled to memory circuits M1-M3. In some embodiments, test circuit 120 is implemented using Memory build-in Self Test (MBIST) circuitry and is integrated on a chip with Memory circuits M1-M3.
In some embodiments, the storage capacities of these memory circuits M1-M3 are different from each other. In some other embodiments, the storage capacities of these memory circuits M1-M3 are not different from each other.
For easy understanding, the memory capacities of the memory circuits M1 to M3 will be described below by way of example, but the invention is not limited thereto. Taking fig. 1 as an example, the memory circuit M1 has Q entries (entries), the memory circuit M2 has P entries, and the memory circuit M2 has N entries, wherein Q, P, N is a positive integer, Q is greater than P and P is greater than N. In other words, the memory capacity of the memory circuit M1 is larger than the memory capacity of the memory circuit M2, and the memory capacity of the memory circuit M2 is larger than the memory capacity of the memory circuit M3.
It is specifically noted herein that the number of memory circuits in fig. 1 is merely exemplary, and that various suitable numbers are within the scope of the present invention.
The test circuit 120 may be understood as a memory access controller for performing a read/write operation on the memory circuits M1-M3 to test the memory circuits M1-M3. For this same read/write operation, all entries in each of the memory circuits M1-M3 are read or written. That is, for the same read and write operation, the total operation time interval of the memory circuit M1 having the most entries (the memory capacity is the largest) is the longest, and the total operation time interval of the memory circuit M3 having the least entries (the memory capacity is the smallest) is the shortest.
Reference is made to fig. 1 and 2 together. Fig. 2 is a timing diagram of the test system 100 of fig. 1, shown in accordance with some embodiments of the present invention. The test circuit 120 may control the read/write start time points ST1 to ST3 of the memory circuits M1 to M3 to be different from each other based on the clock signal CLK. Taking fig. 2 as an example, for the same read/write operation, the test circuit 120 may control the memory circuit M1 to perform the read/write operation at the read/write start time point ST1 based on the clock signal CLK, control the memory circuit M2 to perform the read/write operation at the read/write start time point ST2 based on the clock signal CLK, and control the memory circuit M3 to perform the read/write operation at the read/write start time point ST3 based on the clock signal CLK.
Taking fig. 1 as an example, the test circuit 120 may include an enable signal generating circuit 121, an address generating circuit 122, an offset circuit 123 and an offset circuit 124.
The enable signal generation circuit 121 is used to generate and output enable signals EN1-EN3. The enable signals EN1-EN3 are primarily used to enable or disable the memory circuits M1-M3. The address generating circuit 122 is used for generating and outputting the address signal AD. The address signal AD is mainly used to decide which entry in the memory circuits M1-M3 to perform a read-write operation.
In fig. 1, an enable signal generating circuit 121 and an address generating circuit 122 are coupled to a memory circuit M1. The memory circuit M1 may receive the enable signal EN1 from the enable signal generating circuit 121 and the address signal AD from the address generating circuit 122. Accordingly, if the enable signal EN1 has an enable level at the read/write start time point ST1, the memory circuit M1 may be subjected to a read/write operation at the read/write start time point ST1 according to the enable signal EN1 and the address signal AD.
On the other hand, the enable signal generating circuit 121 and the address generating circuit 122 are coupled to the offset circuit 123, and the offset circuit 123 is coupled to the memory circuit M2. The offset circuit 123 may receive the enable signal EN2 from the enable signal generating circuit 121 and the address signal AD from the address generating circuit 122. Then, the offset circuit 123 may generate the offset signal DS1 according to the enable signal EN2 and the address signal AD. And the memory circuit M2 can be subjected to a read-write operation at the read-write start time point ST2 in accordance with the offset signal DS1.
In some embodiments, offset circuit 123 may include a comparator. This comparator may compare the address value carried by the address signal AD with a first offset value (e.g., 256). The address value carried by the address signal AD may be counted down from an initial address value (e.g., 0). When the current address value (e.g., 256) carried by the address signal AD is equal to the first offset value (e.g., time point ST 2), the enable signal EN2 has an enable level. At this time, the offset circuit 123 may generate the offset signal DS1 to enable the memory circuit M2 at the read/write start time point ST2 and determine which entry (e.g., entry 0) in the memory circuit M2 to perform the read/write operation according to the difference (e.g., 256-256=0) between the current address value and the first offset value.
Similarly, the enable signal generating circuit 121 and the address generating circuit 122 are coupled to the offset circuit 124, and the offset circuit 124 is coupled to the memory circuit M3. The offset circuit 124 may receive the enable signal EN3 from the enable signal generating circuit 121 and the address signal AD from the address generating circuit 122. Then, the offset circuit 124 may generate the offset signal DS2 according to the enable signal EN3 and the address signal AD. And the memory circuit M3 can be subjected to a read-write operation at the read-write start time point ST3 in accordance with the offset signal DS2.
Similarly, in some embodiments, the offset circuit 124 may include a comparator. This comparator may compare the address value carried by the address signal AD with a second offset value (e.g., 128). As previously described, the address value carried by the address signal AD may be counted down from an initial address value (e.g., 0). When the current address value (e.g., 128) carried by the address signal AD is equal to the second offset value (e.g., time point ST 3), the enable signal EN3 has an enable level. At this time, the offset circuit 124 may generate the offset signal DS2 to enable the memory circuit M3 at the read/write start time point ST3 and determine which entry (e.g., entry 0) in the memory circuit M3 to perform the read/write operation according to the difference (e.g., 128-128=0) between the current address value and the second offset value.
Taking fig. 2 as an example, the start time ST1 is earlier than the start time ST3, and the start time ST3 is earlier than the start time ST2. That is, the read/write start time point ST1 of the memory circuit M1 having the largest storage capacity is earliest. The first delay time interval (marked with dots) is provided between the start time point ST3 and the start time point ST1, and the second delay time interval (also marked with dots) is provided between the start time point ST2 and the start time point ST1, and is longer than the first delay time interval. It is specifically described that, although the read/write start time ST3 is earlier than the read/write start time ST2 in fig. 2, the present invention is not limited thereto. In some other embodiments, the start time ST3 may be later than the start time ST2.
The time interval (operating time interval) between the start point and the end point of a memory circuit is positively correlated to the storage capacity of the memory circuit. Taking fig. 2 as an example, since the memory capacity of the memory circuit M1 is the largest, the time interval covered between the read/write start time point ST1 and the read/write end time point ET1 of the memory circuit M1 is the longest. Since the memory circuit M3 has the smallest storage capacity, the time period covered between the read/write start time point ST3 of the memory circuit M3 and the read/write end time point ET3 thereof is the shortest.
In some embodiments, the test circuit 120 may control the read/write end time ET2 of the memory circuit M2 and the read/write end time ET3 of the memory circuit M3 to be no later (same as or earlier) than the read/write end time ET1 of the memory circuit M1 having the maximum storage capacity. Accordingly, additional testing time is avoided. In the example of fig. 2, the test circuit 120 controls the read/write end time point ET1 of the memory circuit M1, the read/write end time point ET2 of the memory circuit M2, and the read/write end time point ET3 of the memory circuit M3 to be different from each other.
In some embodiments, the disable time point of a memory circuit is the read/write end time point of the memory circuit. Taking fig. 1 and fig. 2 as an example, the enable signal EN1 may have a disable level at the end time ET1 to disable the memory circuit M1. The enable signal EN2 may have a disable level at the end of read/write time ET2 to enable the corresponding generated offset signal DS1 to disable the memory circuit M2. The enable signal EN3 may have a disable level at the end of read/write time ET3 to enable the corresponding generated offset signal DS2 to disable the memory circuit M3. Therefore, the power saving effect can be achieved.
In some other embodiments, the disabling time points of all the memory circuits M1-M3 are the read/write end time points of the memory circuit M1 having the maximum storage capacity. That is, the enable signals EN1-EN3 each have a disable level at the end of read/write time ET1 to disable the memory circuits M1-M3. The idle period of the memory circuit M2 is between the read/write end time ET2 of the memory circuit M2 and the read/write end time ET1 of the memory circuit M1, and the idle period of the memory circuit M3 is between the read/write end time ET3 of the memory circuit M3 and the read/write end time ET1 of the memory circuit M1.
In some related art, in order to save circuit area occupied by a memory test circuit, a plurality of memory circuits are tested using a single test circuit. In this case, when the test starts (the process of switching from the idle state to the test state), a great current will be generated. This extremely large current can cause insufficient power supply, resulting in excessive instantaneous voltage drops and hence circuit failure.
In some related art, to avoid the excessive transient voltage drop, a plurality of memory circuits are tested by a plurality of test circuits. However, this increases the circuit area occupied by the test circuit and thus increases the size of the entire chip. In other related art, to avoid excessive transient voltage drops, these memory circuits are time-divided into multiple groups for testing. However, this may increase the test time.
In comparison with the above-mentioned related arts, in the present invention, a plurality of memory circuits M1-M3 are tested by a single test circuit 120, and the test circuit 120 can stagger the read/write start time points ST1-ST3 of the memory circuits M1-M3. Therefore, the invention can avoid the excessive instant voltage drop caused by the extremely large current under the condition of not increasing the circuit area occupied by the test circuit and not increasing the test time, thereby ensuring the normal operation of the circuit. The less the overlapping of the operating time intervals of the memory circuits M1-M3, the better the effect of avoiding extremely large currents.
Reference is made to fig. 3. Fig. 3 is a schematic diagram of an offset value generation circuit 300 according to some embodiments of the invention. In some embodiments, the delay circuit 123 or 124 OF fig. 1 may further include an offset value generating circuit 300, and the offset value generating circuit 300 may be configured to generate the first offset value (denoted by OF1 in fig. 3) or the second offset value (denoted by OF2 in fig. 3) as described above.
Taking fig. 3 as an example, the offset circuit 300 includes a multiplexer 310 and a register 320. The multiplexer 310 includes a plurality of inputs. One of the inputs of the multiplexer 310 is coupled to the register 320, and the other input of the multiplexer 310 is respectively configured to receive the candidate OFFSET value OFFSET1, the candidate OFFSET value OFFSET2, and the candidate OFFSET value OFFSET3. The register 320 may generate candidate OFFSET value OFFSET4 based on system requirements or application scenarios and according to a user operation or a command from a control circuit.
The multiplexer 310 may output one OF the candidate OFFSET values OFFSET1, OFFSET2, OFFSET3, OFFSET4 according to the selection signal SS to generate the first OFFSET value OF1 or the second OFFSET value OF2. The selection signal SS may be generated based on system requirements or application scenarios and according to a user operation or a command from a control circuit. Then, as described above, the delay circuit 123 or 124 may further generate the offset signal DS1 or DS2 according to the first offset value OF1 or the second offset value OF2.
Since the candidate OFFSET value OFFSET4 or the selection signal SS can be adjusted based on the system requirements or the application scenario, this structure has greater application flexibility and can be applied to more use environments.
It is specifically noted herein that the number of candidate offset values or registers in fig. 3 is merely exemplary, and that various applicable numbers are within the scope of the present invention.
Refer to fig. 4. Fig. 4 is a flow chart of a test method 400 shown in accordance with some embodiments of the present invention. Taking fig. 4 as an example, the test method 400 includes operation S410 and operation S420.
In some embodiments, the test method 400 may be applied to the test system 100 in fig. 1, but the invention is not limited thereto. However, for ease of understanding, the test method 400 will be described in connection with the test system 100 of FIG. 1.
In operation S410, a read/write operation is performed on the memory circuits M1-M3 through the test circuit 120. The memory circuits M1-M3 each have a read-write start time point corresponding to the read-write operation. Taking fig. 2 as an example, the memory circuit M1 corresponds to a read/write start time point ST1, the memory circuit M2 corresponds to a read/write start time point ST2, and the memory circuit M3 corresponds to a read/write start time point ST3.
In operation S420, the read/write start time points ST1 to ST3 of the memory circuits M1 to M3 are controlled to be different from each other by the test circuit 120. In some embodiments, the read/write start time ST1 of the memory circuit M1 with the largest memory capacity is the earliest, while the read/write start time ST2-ST3 of the other memory circuits M2-M3 is later than the read/write start time ST1.
In summary, in the present invention, a single test circuit is used to test a plurality of memory circuits, and the test circuit may stagger the read/write start time points of the memory circuits. Therefore, the invention can avoid the excessive instant voltage drop under the condition of not (or a small amount of) increasing the circuit area occupied by the test circuit and not increasing the test time so as to ensure the normal operation of the circuit.
Although embodiments of the present invention have been disclosed above, these are not intended to limit the present invention, and those skilled in the art will appreciate that various modifications and adaptations can be made without departing from the spirit and scope of the present invention, and that the scope of the present invention is to be defined by the appended claims.

Claims (10)

1. A test system, comprising:
a plurality of memory circuits; and
a test circuit coupled to the plurality of memory circuits, wherein the test circuit is used for performing a read-write operation on the plurality of memory circuits, and each of the plurality of memory circuits has a read-write start time point corresponding to the read-write operation,
wherein the test circuit is further configured to control the plurality of read/write start time points of the plurality of memory circuits to be different from each other.
2. The test system of claim 1, wherein the plurality of memory circuits comprises a first memory circuit and a second memory circuit, wherein a storage capacity of the first memory circuit is greater than a storage capacity of the second memory circuit, and the read-write start time point of the first memory circuit is earlier than the read-write start time point of the second memory circuit.
3. The test system of claim 2, wherein a read-write end time point of the second memory circuit corresponding to the read-write operation is the same as or earlier than a read-write end time point of the first memory circuit corresponding to the read-write operation.
4. The test system of claim 2, wherein the test circuit comprises:
an enable signal generating circuit for generating a first enable signal and a second enable signal;
an address generating circuit for generating an address signal; and
a first offset circuit for generating a first offset signal according to the second enable signal and the address signal,
wherein the first memory circuit is to perform the read and write operations in accordance with the first enable signal and the address signal,
wherein the second memory circuit is to perform the read and write operations in accordance with the first offset signal.
5. The test system of claim 4, wherein the first offset circuit is configured to compare an address value carried by the address signal with an offset value, wherein the first offset circuit generates the first offset signal to perform the read/write operation on the second memory circuit according to the second enable signal and the address signal when the address value is equal to the offset value.
6. The test system of claim 5, wherein the first offset circuit comprises:
a multiplexer for receiving a plurality of candidate offset values and outputting one of the candidate offset values as the offset value according to a selection signal; and
and a register coupled to the multiplexer, wherein the register is configured to generate one of the plurality of candidate offset values.
7. The test system of claim 4, wherein the second memory circuit has a read-write end time corresponding to the read-write operation, and the second enable signal has a disable level at the read-write end time of the second memory circuit.
8. The test system of claim 4, wherein the first memory circuit has a read-write end time corresponding to the read-write operation, and the second enable signal has a disable level at the read-write end time of the first memory circuit.
9. The test system of claim 4, wherein the plurality of memory circuits further comprises a third memory circuit, wherein the enable signal generation circuit is further configured to generate a third enable signal, wherein the test circuit further comprises:
a second offset circuit for generating a second offset signal according to the third enable signal and the address signal,
wherein the third memory circuit is configured to perform the read and write operations in accordance with the second offset signal.
10. A method of testing, comprising:
performing a read-write operation on a plurality of memory circuits through a test circuit, wherein each of the plurality of memory circuits has a read-write start time point corresponding to the read-write operation; and
the plurality of read-write start time points of the plurality of memory circuits are controlled to be different from each other by the test circuit.
CN202210067893.6A 2022-01-20 2022-01-20 Test system and test method Pending CN116524981A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210067893.6A CN116524981A (en) 2022-01-20 2022-01-20 Test system and test method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210067893.6A CN116524981A (en) 2022-01-20 2022-01-20 Test system and test method

Publications (1)

Publication Number Publication Date
CN116524981A true CN116524981A (en) 2023-08-01

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210067893.6A Pending CN116524981A (en) 2022-01-20 2022-01-20 Test system and test method

Country Status (1)

Country Link
CN (1) CN116524981A (en)

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