CN116524856A - Array substrate row driving circuit, display panel and display device - Google Patents
Array substrate row driving circuit, display panel and display device Download PDFInfo
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- CN116524856A CN116524856A CN202310481042.0A CN202310481042A CN116524856A CN 116524856 A CN116524856 A CN 116524856A CN 202310481042 A CN202310481042 A CN 202310481042A CN 116524856 A CN116524856 A CN 116524856A
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- 239000010409 thin film Substances 0.000 description 13
- 239000003990 capacitor Substances 0.000 description 7
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- 230000009286 beneficial effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
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Abstract
The application relates to an array substrate row drive circuit, display panel and display device, array substrate row drive circuit includes: n+1 array substrate row driving units and N logic units; the input ends of the N+1 array substrate row driving units are connected with the clock signal lines in a cascading manner, and the N+1 array substrate row driving units are used for generating N+1 scanning signals according to clock signals on the clock signal lines; the output ends of any two adjacent array substrate row driving units in the N+1 array substrate row driving units are respectively connected with the input end of one logic unit in the N logic units, and each logic unit in the N logic units is used for generating a luminous control signal according to two scanning signals received by each logic unit; the output ends of the N+1 array substrate row driving units and the output ends of the N logic units are connected with the input ends of the N x M pixel driving circuits. Therefore, the occupied space of the edge of the display panel is reduced, and the narrow frame design of the control panel is facilitated.
Description
Technical Field
The application relates to the technical field of display, in particular to an array substrate row driving circuit, a display panel and a display device.
Background
Because the organic light emitting diode (Organic Light Emitting Display, abbreviated as OLED) display has the advantages of low energy consumption, wide viewing angle, high resolution, wide temperature characteristic, capability of preparing a flexible screen and the like, more and more display manufacturers worldwide invest in research and development of the OLED, and the industrialization process of the OLED is greatly promoted.
However, in the conventional OLED design, each sub-pixel on the display panel needs a scan signal and a light emission control signal, wherein the scan signal needs to be generated by an array substrate row driving (GOA) unit using a part of clock signals provided by a timing control circuit board (Timing Controller, abbreviated as TCON), and the light emission control signal needs to be generated by an array emission driving (EOA) unit using another part of clock signals provided by the timing control circuit board, so that a large number of clock signal lines, GOA units and EOA units need to be arranged at the frame positions of the display panel, which makes it difficult to realize a narrow frame design of the display panel. Therefore, how to realize the narrow frame design of the control panel is a technical problem to be solved.
Disclosure of Invention
The application provides an array substrate row driving circuit, a display panel and a display device to solve the problem that the display panel is difficult to realize narrow frame design because a large number of clock signal lines, GOA units and EOA units are required to be distributed at the frame position of the display panel in the prior OLED design.
In a first aspect, an embodiment of the present application provides an array substrate row driving circuit, including: n+1 array substrate row driving units and N logic units;
the input ends of the N+1 array substrate row driving units are connected with a clock signal line in a cascading manner, and the N+1 array substrate row driving units are used for generating N+1 scanning signals according to clock signals on the clock signal line, wherein N is an integer greater than or equal to 1;
the output ends of any two adjacent array substrate row driving units in the N+1 array substrate row driving units are respectively connected with the input end of one logic unit in the N logic units, and each logic unit in the N logic units is used for generating a light-emitting control signal according to two scanning signals received by each logic unit;
the output ends of the N+1 array substrate row driving units and the output ends of the N logic units are connected with the input ends of N.M pixel driving circuits, and the pixel driving circuits are used for driving the organic light emitting diodes corresponding to the pixels to emit light according to the received scanning signals and the received light emitting control signals, wherein M is an integer larger than or equal to 1.
Optionally, the logic unit includes: the first field effect transistor, the second field effect transistor, the third field effect transistor and the fourth field effect transistor;
the grid electrode of the first field effect tube and the grid electrode of the third field effect tube are respectively connected with the output end of the first array substrate row driving unit, the grid electrode of the second field effect tube and the grid electrode of the fourth field effect tube are respectively connected with the output end of the second array substrate row driving unit, the drain electrode of the first field effect tube and the drain electrode of the second field effect tube are respectively connected with positive working voltage, the source electrode of the first field effect tube, the source electrode of the second field effect tube and the drain electrode of the third field effect tube are jointly used as the output end of the logic unit to be connected with the input end of the pixel driving circuit of the corresponding row, and the source electrode of the third field effect tube is connected with negative working voltage;
the output ends of the first array substrate row driving unit and the second array substrate row driving unit are output ends of any two adjacent array substrate row driving units in the N+1 array substrate row driving units, and the positive working voltage, the negative working voltage and the clock signal are provided by a time sequence control circuit board.
Optionally, the scanning signal output by the output end of the first array substrate row driving unit is a first scanning signal, the scanning signal output by the output end of the second array substrate row driving unit is a second scanning signal, and the light emitting control signal of the output end of the logic unit connected with the first array substrate row driving unit and the second array substrate row driving unit is a first light emitting control signal;
wherein the first light emission control signal is low level in case that both the first scan signal and the second scan signal are high level;
in the case that the first scan signal is at a high level and the second scan signal is at a low level, the first light emitting control signal is at a high level;
in the case where the first scan signal is at a low level and the second scan signal is at a high level, the first light emitting control signal is at a high level.
Optionally, the first field effect transistor and the second field effect transistor are P-type MOS transistors, and the third field effect transistor and the fourth field effect transistor are N-type MOS transistors.
Optionally, the clock signal lines are composed of any even number of clock signal lines.
In a second aspect, an embodiment of the present application further provides a display panel, including a display area and an array substrate row driving area;
wherein the display area is provided with N x M pixel driving circuits, N and M are integers greater than or equal to 1,
the array substrate row driving region is provided with the array substrate row driving circuit according to the first aspect, and the array substrate row driving circuit is connected to the n×m pixel driving circuits.
Optionally, the array substrate row driving area is located at an edge position of at least one side edge of the display panel.
Optionally, the array substrate row driving area is located at edge positions of two opposite sides of the display panel.
Optionally, the n×m pixel driving circuits are n×m 7T1C driving circuits.
In a third aspect, embodiments of the present application further provide a display device, where the display device includes a timing control circuit board and a display panel according to the second aspect; and a clock signal line is arranged between the time sequence control circuit board and the display panel.
In an embodiment of the present application, an array substrate row driving circuit includes: n+1 array substrate row driving units and N logic units; the input ends of the N+1 array substrate row driving units are connected with a clock signal line in a cascading manner, and the N+1 array substrate row driving units are used for generating N+1 scanning signals according to clock signals on the clock signal line, wherein N is an integer greater than or equal to 1; the output ends of any two adjacent array substrate row driving units in the N+1 array substrate row driving units are respectively connected with the input end of one logic unit in the N logic units, and each logic unit in the N logic units is used for generating a light-emitting control signal according to two scanning signals received by each logic unit; the output ends of the N+1 array substrate row driving units and the output ends of the N logic units are connected with the input ends of N.M pixel driving circuits, and the pixel driving circuits are used for driving the organic light emitting diodes corresponding to the pixels to emit light according to the received scanning signals and the received light emitting control signals, wherein M is an integer larger than or equal to 1. Therefore, the light-emitting control signals can be generated through the scanning signals and the logic units output by the array substrate row driving unit, and no extra clock signal lines are required to be arranged to be connected with the EOA unit to generate the light-emitting control signals, so that the number of wires of clock signal lines at the edge of the display panel is reduced, the occupied space at the edge of the display panel is further reduced, and the narrow frame design of the control panel is facilitated.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, and it will be obvious to a person skilled in the art that other drawings can be obtained from these drawings without inventive effort.
Fig. 1 is a schematic structural diagram of a row driving circuit of an array substrate according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a 7T1C driving circuit according to the prior art;
fig. 3 is a schematic structural diagram of a row driving circuit of an array substrate provided in the prior art;
fig. 4 is a schematic structural diagram of a logic unit according to an embodiment of the present application;
FIG. 5 is a timing diagram of a 7T1C driving circuit according to an embodiment of the present disclosure;
FIG. 6 is a schematic diagram of a 7T1C driving circuit according to an embodiment of the present disclosure;
FIG. 7 is a second circuit conduction state diagram of a 7T1C driving circuit according to an embodiment of the present disclosure;
FIG. 8 is a third diagram illustrating a circuit on state of a 7T1C driving circuit according to an embodiment of the present disclosure;
fig. 9 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure;
fig. 10 is a schematic structural diagram of a display device according to an embodiment of the present application.
100, an array substrate row driving unit; 110. a logic unit; 120. a clock signal line; 130. a display panel; 1301. a display area; 1302. an array substrate row driving region; 140. and a timing control circuit board.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present application based on the embodiments herein.
Referring to fig. 1, fig. 1 is a schematic structural diagram of an array substrate row driving circuit according to an embodiment of the present application. As shown in fig. 1, the array substrate row driving circuit includes: n+1 array substrate row driving units 100 and N logic units 110;
the input ends of the n+1 array substrate row driving units 100 are connected with the clock signal line 120 in a cascade manner, and the n+1 array substrate row driving units 100 are used for generating n+1 scanning signals according to clock signals on the clock signal line 120, wherein N is an integer greater than or equal to 1;
the output ends of any two adjacent array substrate row driving units 100 in the N+1 array substrate row driving units 100 are respectively connected with the input end of one logic unit 110 in the N logic units 110, and each logic unit 110 in the N logic units 110 is used for generating a light-emitting control signal according to two received scanning signals;
the output ends of the n+1 array substrate row driving units 100 and the output ends of the N logic units 110 are connected to the input ends of n×m pixel driving circuits (not shown in the figure), where the pixel driving circuits are configured to drive the organic light emitting diodes corresponding to the pixels to emit light according to the received scan signals and the emission control signals, and M is an integer greater than or equal to 1.
Specifically, the number of the array substrate row driving units 100 and the number of the logic units 110 may be determined according to the actual number of rows of the pixels of the display panel, for example, when the number of rows of the pixels of the display panel is 1080, the number of the required array substrate row driving units 100 is 1081 and the number of the required logic units 110 is 1080. The clock signal line 120 is a signal line between the array substrate row driving circuit and the timing control circuit board, and the clock signal line 120 is used for transmitting a clock signal to the array substrate row driving unit 100, so that the array substrate row driving unit 100 can generate a scanning signal according to the clock signal. The logic unit 110 is a logic unit formed by using a plurality of field effect transistors, and the logic unit 110 is configured to generate a light emission control signal according to two received scan signals. The above-described pixel driving circuit may be any circuit that requires a scanning signal and a light emission control signal to drive, such as a 7T1C driving circuit, a 5T1C driving circuit, a 7T2C driving circuit (where the number before T represents the number of thin film transistors, and the number before C represents the number of storage capacitors), and the like.
For ease of understanding, the 7T1C driving circuit is used herein for explanation as a pixel driving circuit corresponding to each pixel on the display panel. The structure of the 7T1C driving circuit is shown in fig. 2, and the structure of the 7T1C driving circuit includes 7 thin film transistors (Thin Film Transistor, abbreviated as TFTs), 1 storage capacitor and 1 organic light emitting diode, wherein T1 'is a TFT for controlling whether the organic light emitting diode emits light, and under normal conditions, the current flowing through the organic light emitting diode must flow through T1'; t2' is a TFT controlling the magnitude of a current flowing through the organic light emitting diode; t3' is a TFT controlling the potential on the initializing storage capacitor C, and T4' is a TFT compensating for the threshold voltage Vth of T2 '; t5' is a TFT controlling when the high voltage ELVDD supplies power to the organic light emitting diode; t6' is a TFT that controls when the data voltage Vdata charges the storage capacitor C; t7' is the TFT initializing the anode of the organic light emitting diode. In the figure, VINT is an initialization voltage, vdata is a data voltage, ELVDD is a high voltage for supplying current to the OLED, and ELVSS is a low voltage for supplying current to the OLED. Two signals, scan (n-1) and Scan (n), and an emission control signal EM (n), are required to drive the organic light emitting diode in the 7T1C driving circuit to emit light. In the prior art, these two signals need to be provided by the timing control board, and need to be routed through the edge of the screen to be connected with the pixel driving circuit, so that more screen edge space is required to be occupied, which becomes a bottleneck of the narrow-frame technology.
Here, 2 clock signal lines are taken as an example for explanation, and other numbers of clock signal lines are similar, and are not repeated. When the array substrate row driving circuit shown in fig. 3 is adopted, the timing control circuit board TCON board needs to provide 2 clk_g and 2 clk_e for 4 signals, and these 4 signals are transmitted to the corresponding module unit (clk_g signal is transmitted to the GOA unit and clk_e signal is transmitted to the EOA unit) through the flexible circuit board (Flexible Printed Circuit, abbreviated as FPC) and the Chip On Film (abbreviated as COF) through the screen edge, so that the GOA unit outputs the Scan signal Scan (n) and the EOA unit outputs the light emission control signal Em (n) for driving and controlling the pixel driving circuit.
When the array substrate row driving circuit shown in fig. 1 is adopted, the clk_e signal in the clock signal can be removed, the timing control circuit board TCON board only needs to provide 2 clk_g signals, these 2 signals are transmitted to the corresponding GOA unit through the flexible circuit board and the flip chip film and finally through the screen edge, the GOA unit outputs the Scan signal Scan (n), and the two adjacent Scan signals can generate the light emission control signal Em (n) through the logic unit 110 for driving and controlling the pixel driving circuit.
Compared with the array substrate row driving circuit shown in fig. 3, the array substrate row driving circuit provided by the embodiment of the application can reduce the number of clock signals by half, and the display panel can better realize narrow frame design.
Further, referring to fig. 4, the logic unit 110 includes: the first field effect transistor T1, the second field effect transistor T2, the third field effect transistor T3 and the fourth field effect transistor T4;
the grid electrode of the first field effect tube T1 and the grid electrode of the third field effect tube T3 are respectively connected with the output end of the first array substrate row driving unit 100, the grid electrode of the second field effect tube T2 and the grid electrode of the fourth field effect tube T4 are respectively connected with the output end of the second array substrate row driving unit 100, the drain electrode of the first field effect tube T1 and the drain electrode of the second field effect tube T2 are respectively connected with positive working voltage VCC, the source electrode of the first field effect tube T1, the source electrode of the second field effect tube T2 and the drain electrode of the third field effect tube T3 are jointly used as the output end of the logic unit 110 to be connected with the input end of a pixel driving circuit of a corresponding row, and the source electrode of the third field effect tube T3 is connected with negative working voltage VSS;
the output end of the first array substrate row driving unit 100 and the output end of the second array substrate row driving unit 100 are output ends of any two adjacent array substrate row driving units 100 in the n+1 array substrate row driving units 100, and the positive working voltage VCC, the negative working voltage VSS and the clock signal are provided by the timing control circuit board.
In this embodiment, since the logic unit 110 is composed of 4 field effect transistors, and the existing array emission driving unit (i.e. EOA unit) generally needs to be composed of more than ten or even tens of field effect transistors, the volume of the logic unit 110 is far smaller than that of the array emission driving unit, so that when the logic unit 110 is used to replace the array emission driving unit to generate the light-emitting control signal, the occupied space at the edge of the display panel can be further reduced, which is beneficial to realizing the narrow frame design of the control panel.
Further, the scanning signal output by the output end of the first array substrate row driving unit is a first scanning signal, the scanning signal output by the output end of the second array substrate row driving unit is a second scanning signal, and the light-emitting control signal of the output end of the logic unit connected with the first array substrate row driving unit and the second array substrate row driving unit is a first light-emitting control signal;
wherein, in the case that the first scanning signal and the second scanning signal are both high level, the first light emitting control signal is low level;
in the case that the first scan signal is at a high level and the second scan signal is at a low level, the first light emitting control signal is at a high level;
in the case where the first scan signal is at a low level and the second scan signal is at a high level, the first light emission control signal is at a high level.
Specifically, the first scanning signal and the second scanning signal are scanning signals output by any two adjacent array substrate row driving units in the n+1 array substrate row driving units; the first light emission control signal is a light emission control signal generated by a logic unit based on the first scanning signal and the second scanning signal.
In an embodiment, the logic unit 110 and the level signals of the first scan signal and the second scan signal may be used to generate the obtained first light emitting control signal, where the first scan signal, the second scan signal and the first light emitting control signal satisfy the timing relationship: when the first scanning signal is at a low level and the second scanning signal is at a high level, the generated first light emitting control signal is at a high level; when the first scanning signal is at a high level and the second scanning signal is at a low level, the generated first light emitting control signal is at a high level; when both the first scan signal and the second scan signal are at a high level, the generated first light emission control signal is at a low level. For convenience of explanation, a 7T1C driving circuit is taken as an example of the pixel driving circuit. The Scan signals Scan (n-1) and Scan (n) and the emission control signal EM (n) of the driving control 7T1C driving circuit are required to satisfy the timing chart shown in fig. 5, and thus a single sub-pixel operation sequence can be realized. For example, in the reset stage (i.e. the T1 stage), the 7T1C driving circuit needs Scan (n-1) to be at a low level, and Scan (n) and EM (n) to be at a high level, so that the thin film transistors T2 'and T3' are in on states, the other thin film transistors are in off states, the circuit on states are as shown in fig. 6, the reset stage is used for resetting the storage capacitor, and signal residues may exist in the previous stage; in the Data charging stage (i.e. stage T2), the 7T1C driving circuit needs Scan (n) to be low level, and Scan (n-1) and EM (n) to be high level, so that the tfts T2', T4' and T6' are turned on, the other tfts are turned off, the Data line Data is used to supply Data to charge the capacitor, and the circuit is turned on as shown in fig. 7. DATA may be temporarily stored in the capacitor during the DATA charging phase (the DATA signal is used to determine the light emitting brightness of the organic light emitting diode); in the light-emitting phase (i.e., the T3 phase), the 7T1C driving circuit needs EM (n) to be low level, and Scan (n-1) and Scan (n) to be high level, so that the thin film transistors T1', T2', and T5' are in on state, the other thin film transistors are in off state, ELVDD voltage (high voltage for providing current to OLED) is transferred to the organic light-emitting diode, the organic light-emitting diode emits light, and the circuit on state is shown in fig. 8.
In this embodiment, the logic unit 110 generates a light emission control signal according to the received two scan signals, and enables the two scan signals and the light emission control signal to satisfy the timing relationship shown in fig. 5, so that the pixel driving circuit can be normally driven to emit light.
Further, with continued reference to fig. 4, the first field effect transistor T1 and the second field effect transistor T2 are P-type MOS transistors, and the third field effect transistor T3 and the fourth field effect transistor T4 are N-type MOS transistors.
It should be noted that, according to the operating characteristics of the P-type MOS transistor and the N-type MOS transistor, when the two Scan signals Scan (N-1) and Scan (N) received by the logic unit 110 are both at the high level, the first field effect transistor T1 and the second field effect transistor T2 are turned off, the third field effect transistor T3 and the fourth field effect transistor T4 are turned on, and at this time, the output Em (N) is at the low level; when Scan (n-1) is at a high level and Scan (n) is at a low level, the first field effect transistor T1 and the fourth field effect transistor T4 are closed, the second field effect transistor T2 and the third field effect transistor T3 are opened, and then Em (n) output is at a high level; when Scan (n-1) is at low level and Scan (n) is at high level, the second fet T2 and the third fet T3 are turned off, the first fet T1 and the fourth fet T4 are turned on, and Em (n) is at high level. The logic unit in the embodiment of the present application can be used to generate a timing relationship required to satisfy the pixel driving circuit. Taking a 7T1C driving circuit as an example of a pixel driving circuit, the timing relationship required for realizing the operation sequence of the individual sub-pixels is as shown in fig. 5:
when Scan (n-1) is at low level and Scan (n) is at high level, the generated EM (n) is at high level, and at this time, the thin film transistors T2 'and T3' in the 7T1C driving circuit are in on state, and the other thin film transistors are in off state, so that the 7T1C driving circuit is in reset phase (i.e., T1 phase);
when the first scanning signal is at a high level and the second scanning signal is at a low level, the generated first light emitting control signal is at a high level; when both the first scan signal and the second scan signal are at a high level, the generated first light emission control signal is at a low level.
When Scan (n-1) is at a high level and Scan (n) is at a low level, the generated EM (n) is at a high level, and at this time, the thin film transistors T2', T4', and T6' in the 7T1C driving circuit are in an on state, and the other thin film transistors are in an off state, so that the 7T1C driving circuit is in a data charging stage (i.e., a T2 stage);
when Scan (n-1) is at a high level and Scan (n) is at a high level, the generated EM (n) is at a low level, and at this time, the thin film transistors T1', T2', and T5' in the 7T1C driving circuit are in an on state, and the other thin film transistors are in an off state, so that the 7T1C driving circuit is in a light emitting stage (i.e., a T3 stage). In this embodiment, by setting the first field effect transistor T1 and the second field effect transistor T2 in the logic unit as P-type MOS transistors, and setting the third field effect transistor T3 and the fourth field effect transistor T4 as N-type MOS transistors, it is possible to realize that the light emission control signal output by the logic unit and the inputted scanning signal satisfy the timing relationship required by the pixel driving circuit.
Further, the clock signal line 120 is composed of any even number of clock signal lines.
In an embodiment, the clock signal lines 120 connected to the array substrate row driving unit 100 may be composed of any even number of clock signal lines, such as 2, 4, 6, 8, etc., and may be specifically determined according to the size and display requirements of the display panel, which is not specifically limited in the embodiment of the present application.
Therefore, the number of clock signal lines connected with the array substrate row driving units can be flexibly set according to the actual requirements of the display panel, and diversified setting is realized.
In addition, referring to fig. 9, fig. 9 is a schematic diagram of a display panel according to an embodiment of the present application. As shown in fig. 9, the display panel 130 includes a display region 1301 and an array substrate row driving region 1302;
wherein the display region 1301 is provided with n×m pixel driving circuits, N and M are integers greater than or equal to 1,
the array substrate row driving region 1302 is provided with the aforementioned array substrate row driving circuit, and the array substrate row driving circuit is connected to the n×m pixel driving circuits.
It should be noted that, since the display panel 130 has the structure of the array substrate row driving circuit, the display panel 130 can achieve the same technical effects as the array substrate row driving circuit, and will not be described in detail herein.
Further, the array substrate row driving region 1302 is located at an edge position of at least one side of the display panel 130.
In an embodiment, the array substrate row driving area 1302 may be located at an edge position of one side of the display panel 130, or at edge positions of multiple sides, which is not specifically limited in the embodiments of the present application. Thereby increasing the flexibility of setting the row driving circuit of the array substrate.
Further, the array substrate row driving regions 1302 are located at edge positions of two opposite sides of the display panel 130.
In an embodiment, the array substrate row driving area 1302 may be located at edge positions of two opposite sides of the display panel 130, so that the entire array substrate row driving circuit may be set at the edge positions of two sides, so that the occupied space of each edge position is smaller, which is beneficial to implementing a narrow frame design.
Further, the n×m pixel driving circuits are n×m 7T1C driving circuits.
In one embodiment, the pixel driving circuit may be a 7T1C driving circuit,
thus, the 7T1C driving circuit can be driven row by row through the array substrate row driving circuit.
In addition, referring to fig. 10, fig. 10 is a schematic structural diagram of a display device according to an embodiment of the present application. As shown in fig. 10, the display device includes a timing control circuit board 140 and the display panel 130, wherein a clock signal line 120 is disposed between the timing control circuit board 140 and the display panel 130. The timing control circuit board 140 transmits a clock signal to the array substrate row driving circuits in the display panel 130 through the clock signal line 120 to drive the pixel driving circuits on the display panel 130 to operate.
Since the array substrate row driving circuit can generate the light emission control signal using the logic unit 110 and the scan signal, the driving circuit design of the timing control circuit board 140 with respect to the clock signal can be simplified, so that the cost of the timing control circuit board 140 is reduced. It should be noted that, since the display device has the structure of the display panel 130, the display device can achieve the same technical effects as the display panel 130, and will not be described in detail herein.
It should be noted that in this document, relational terms such as "first" and "second" and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The foregoing is only a specific embodiment of the invention to enable those skilled in the art to understand or practice the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. An array substrate row driving circuit, characterized in that the array substrate row driving circuit comprises: n+1 array substrate row driving units and N logic units;
the input ends of the N+1 array substrate row driving units are connected with a clock signal line in a cascading manner, and the N+1 array substrate row driving units are used for generating N+1 scanning signals according to clock signals on the clock signal line, wherein N is an integer greater than or equal to 1;
the output ends of any two adjacent array substrate row driving units in the N+1 array substrate row driving units are respectively connected with the input end of one logic unit in the N logic units, and each logic unit in the N logic units is used for generating a light-emitting control signal according to two scanning signals received by each logic unit;
the output ends of the N+1 array substrate row driving units and the output ends of the N logic units are connected with the input ends of N.M pixel driving circuits, and the pixel driving circuits are used for driving the organic light emitting diodes corresponding to the pixels to emit light according to the received scanning signals and the received light emitting control signals, wherein M is an integer larger than or equal to 1.
2. The array substrate row driving circuit of claim 1, wherein the logic unit comprises: the first field effect transistor, the second field effect transistor, the third field effect transistor and the fourth field effect transistor;
the grid electrode of the first field effect tube and the grid electrode of the third field effect tube are respectively connected with the output end of the first array substrate row driving unit, the grid electrode of the second field effect tube and the grid electrode of the fourth field effect tube are respectively connected with the output end of the second array substrate row driving unit, the drain electrode of the first field effect tube and the drain electrode of the second field effect tube are respectively connected with positive working voltage, the source electrode of the first field effect tube, the source electrode of the second field effect tube and the drain electrode of the third field effect tube are jointly used as the output end of the logic unit to be connected with the input end of the pixel driving circuit of the corresponding row, and the source electrode of the third field effect tube is connected with negative working voltage;
the output ends of the first array substrate row driving unit and the second array substrate row driving unit are output ends of any two adjacent array substrate row driving units in the N+1 array substrate row driving units, and the positive working voltage, the negative working voltage and the clock signal are provided by a time sequence control circuit board.
3. The array substrate row driving circuit of claim 2, wherein the scanning signal output from the output end of the first array substrate row driving unit is a first scanning signal, the scanning signal output from the output end of the second array substrate row driving unit is a second scanning signal, and the light emission control signal of the output end of the logic unit connected to the first array substrate row driving unit and the second array substrate row driving unit is a first light emission control signal;
wherein the first light emission control signal is low level in case that both the first scan signal and the second scan signal are high level;
in the case that the first scan signal is at a high level and the second scan signal is at a low level, the first light emitting control signal is at a high level;
in the case where the first scan signal is at a low level and the second scan signal is at a high level, the first light emitting control signal is at a high level.
4. The array substrate row driving circuit of claim 2, wherein the first field effect transistor and the second field effect transistor are P-type MOS transistors, and the third field effect transistor and the fourth field effect transistor are N-type MOS transistors.
5. The array substrate row driving circuit of claim 2, wherein the clock signal lines are composed of any even number of clock signal lines.
6. A display panel is characterized by comprising a display area and an array substrate row driving area;
wherein the display area is provided with N x M pixel driving circuits, N and M are integers greater than or equal to 1,
an array substrate row driving area provided with an array substrate row driving circuit according to any one of claims 1-5, said array substrate row driving circuit being connected to said N x M pixel driving circuits.
7. The display panel of claim 6, wherein the array substrate row driving region is located at an edge position of at least one side of the display panel.
8. The display panel of claim 7, wherein the array substrate row driving regions are located at edge positions of two opposite sides of the display panel.
9. The display panel of claim 6, wherein the N x M pixel driving circuits are N x M7T 1C driving circuits.
10. A display device, characterized in that the display device comprises a timing control circuit board and the display panel according to any one of claims 6-9;
and a clock signal line is arranged between the time sequence control circuit board and the display panel.
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| CN202310481042.0A CN116524856A (en) | 2023-04-27 | 2023-04-27 | Array substrate row driving circuit, display panel and display device |
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| CN202310481042.0A CN116524856A (en) | 2023-04-27 | 2023-04-27 | Array substrate row driving circuit, display panel and display device |
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| CN101281719A (en) * | 2007-04-06 | 2008-10-08 | 三星Sdi株式会社 | Organic light emitting display |
| CN111210776A (en) * | 2020-01-19 | 2020-05-29 | 京东方科技集团股份有限公司 | Gate drive circuit and display panel |
| CN115713915A (en) * | 2022-11-08 | 2023-02-24 | 深圳市华星光电半导体显示技术有限公司 | Integrated gate drive circuit and display device |
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| KR20060000437A (en) * | 2004-06-29 | 2006-01-06 | 삼성에스디아이 주식회사 | Light emitting display |
| CN101281719A (en) * | 2007-04-06 | 2008-10-08 | 三星Sdi株式会社 | Organic light emitting display |
| CN111210776A (en) * | 2020-01-19 | 2020-05-29 | 京东方科技集团股份有限公司 | Gate drive circuit and display panel |
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