CN116521589A

CN116521589A - Data transmission method, device and storage medium

Info

Publication number: CN116521589A
Application number: CN202210068255.6A
Authority: CN
Inventors: 石聪
Original assignee: Datang Mobile Communications Equipment Co Ltd
Current assignee: Datang Mobile Communications Equipment Co Ltd
Priority date: 2022-01-20
Filing date: 2022-01-20
Publication date: 2023-08-01

Abstract

The embodiment of the invention provides a data transmission method, a data transmission device and a storage medium, wherein the method applied to an FPGA comprises the following steps: receiving descriptor triggering information sent by a Central Processing Unit (CPU), wherein the descriptor triggering information comprises descriptor storage address information; analyzing the descriptor trigger information, and reading a plurality of descriptors stored in the CPU according to the descriptor storage address information obtained by analysis, and storing the plurality of descriptors, wherein the descriptors comprise data moving time, data source address information and data destination address information; analyzing the ith descriptor, and moving the data stored in the ith first target address in the CPU to the ith second target address in the FPGA according to the data moving time included in the analyzed ith descriptor; i is an integer from 1 to n, n representing the number of descriptors. Therefore, the embodiment of the invention can improve the time accuracy of the DMA transmission mode between the CPU and the FPGA.

Description

Data transmission method, device and storage medium

Technical Field

The present invention relates to the field of mobile communications technologies, and in particular, to a data transmission method, apparatus, and storage medium.

Background

In the communications industry, baseband processing units (Building Base band Unit, BBU) serve as an important part of communications equipment to process baseband signals for mobile communications.

The BBU has a plurality of data interactions between a central processing unit (central processing unit, CPU) and a field programmable gate array (Field Programmable Gate Array, FPGA), and the data are transmitted through a high-speed serial computer expansion bus standard (peripheral component interconnect express, PCIe) interface, including uplink data reporting, downlink channel parameter transmission, CPU parameter configuration and the like. In downlink channel parameter transmission, since in the BBU, data is transmitted in frames and data scheduling and synchronization are performed in a minimum unit of time slots, control of data transmission in time is in the order of microseconds. Namely, in the FPGA, the requirements on time and transmission efficiency are high in terms of downlink channel parameter transmission.

At present, the main mode of PCIe transmission between the CPU and the FPGA is a direct memory access (Direct Memory Access, DMA) transmission mode, and compared with the direct data transmission mode of the CPU in the traditional system, the transmission mode of the DMA controller does not need the participation of the CPU, thereby greatly improving the data transmission efficiency. However, the DMA transfer time is controlled by the CPU interrupt and is not sufficiently accurate in time.

From the above, in the prior art, the DMA transfer mode between the CPU and the FPGA has low accuracy in time.

Disclosure of Invention

The embodiment of the invention provides a data transmission method, a data transmission device and a storage medium, which are used for solving the problem that the time accuracy of a DMA transmission mode between a CPU and an FPGA is lower in the prior art.

In a first aspect, an embodiment of the present invention provides a data transmission method, applied to a field programmable gate array FPGA, where the method includes:

receiving descriptor trigger information sent by a Central Processing Unit (CPU), wherein the descriptor trigger information comprises descriptor storage address information;

analyzing the descriptor trigger information, reading a plurality of descriptors stored in the CPU according to the descriptor storage address information obtained by analysis, and storing the descriptors, wherein the descriptors comprise data moving time, data source address information and data destination address information;

analyzing an ith descriptor, and moving data stored in an ith first target address in the CPU to an ith second target address in the FPGA according to data moving time included in the ith descriptor obtained through analysis;

The ith first target address is an address represented by data source address information included in the ith descriptor, the ith second target address is an address represented by data destination address information included in the ith descriptor, i is an integer from 1 to n, and n represents the number of the descriptors.

Optionally, after the data stored in the nth first target address in the CPU is moved to the nth second target address in the FPGA according to the data movement time included in the nth descriptor obtained by parsing, the method further includes:

deleting the 1 st to nth descriptors.

Optionally, after parsing the descriptor trigger information, the method further includes:

judging whether the residual space of the storage space for storing the descriptors is smaller than a first preset threshold value;

and executing the steps of reading a plurality of descriptors stored in the CPU and storing the descriptors according to the descriptor storage address information obtained through analysis under the condition that the residual space is larger than or equal to the first preset threshold value.

Optionally, the method further comprises:

and under the condition that the residual space is smaller than the first preset threshold value, discarding the descriptor storage address information obtained by current analysis, starting a preset timer, discarding the descriptor storage address information obtained by analysis in the timing time of the timer, and returning to the step of judging whether the residual space of the storage space for storing the descriptors is smaller than the first preset threshold value until the timing time of the timer reaches the preset time.

Optionally, the descriptor trigger information further includes: the first indication information is used for indicating whether the descriptor triggering information is valid or not;

and executing the step of reading a plurality of descriptors stored in the CPU according to the descriptor storage address information obtained by analysis under the condition that the first indication information obtained by analysis indicates that the descriptor trigger information is valid.

Optionally, the descriptor further includes a descriptor valid signal, where the descriptor valid signal is used to indicate whether the descriptor is valid;

and executing the step of moving the data stored in the ith first target address in the CPU to the ith second target address in the FPGA according to the data moving time included in the ith descriptor obtained by analysis under the condition that the descriptor valid signal included in the ith descriptor obtained by analysis indicates that the ith descriptor is valid.

Optionally, after moving the data stored in the ith first target address in the CPU to the ith second target address in the FPGA according to the data moving time included in the ith descriptor obtained by parsing, the method further includes:

And converting the moved data into a first preset format.

Optionally, the method further comprises at least one of the following steps:

reporting data to the CPU;

receiving a DDR access request sent by the CPU, and sending data associated with the DDR access request to the CPU according to the DDR access request;

and receiving the configuration parameters sent by the CPU.

In a second aspect, an embodiment of the present invention further provides a data transmission method, applied to a central processing unit CPU, where the method includes:

transmitting descriptor trigger information to a Field Programmable Gate Array (FPGA);

the descriptor trigger information comprises descriptor storage address information, and the descriptor trigger information is used for indicating the FPGA to read a plurality of descriptors stored in the CPU according to the descriptor storage address information.

Optionally, sending descriptor trigger information to the FPAG includes:

and sending the descriptor trigger information to the FPAG at preset time intervals.

In a third aspect, an embodiment of the present invention provides a data transmission device applied to a field programmable gate array FPGA, the device including:

The interface conversion module is used for receiving descriptor triggering information sent by a Central Processing Unit (CPU), wherein the descriptor triggering information comprises descriptor storage address information;

the descriptor trigger information configuration module is used for analyzing the descriptor trigger information to obtain the descriptor storage address information;

the descriptor reading module is used for reading a plurality of descriptors stored in the CPU according to the descriptor storage address information obtained by the descriptor triggering information configuration module in a resolving mode;

the descriptor buffer module is used for storing the descriptors read by the descriptor reading module, wherein the descriptors comprise data moving time, data source address information and data destination address information;

the Direct Memory Access (DMA) control module and the data moving module, wherein the DMA control module is used for receiving the ith descriptor sent by the descriptor cache module, analyzing the ith descriptor, and controlling the data moving module to move the data stored in the ith first target address in the CPU to the ith second target address in the FPGA according to the data moving time included in the ith descriptor obtained by analysis;

Optionally, the DMA control module is configured to control the data movement module to move the data stored in the nth first target address in the CPU to the nth second target address in the FPGA according to the data movement time included in the nth descriptor obtained by the parsing, where the descriptor buffer module is further configured to:

deleting the 1 st to nth descriptors.

Optionally, after the read descriptor module receives the descriptor storage address information parsed by the descriptor trigger information configuration module, the read descriptor module is further configured to: judging whether the residual space of the storage space for storing the descriptors is smaller than a first preset threshold value;

and the descriptor reading module executes the step of reading a plurality of descriptors stored in the CPU according to the descriptor storage address information obtained by analyzing by the descriptor trigger information configuration module under the condition that the residual space is larger than or equal to the first preset threshold value.

Optionally, the read descriptor module is further configured to: and under the condition that the residual space is smaller than the first preset threshold value, discarding the currently received descriptor storage address information sent by the descriptor trigger information configuration module, starting a preset timer, discarding the descriptor storage address information sent by the descriptor trigger information configuration module and received within the timing time of the timer until the timing time of the timer reaches the preset time, and returning to the step of judging whether the residual space of the storage space for storing the descriptors is smaller than the first preset threshold value.

Optionally, the descriptor trigger information further includes: the first indication information is used for indicating whether the descriptor trigger signal is valid or not;

and the descriptor trigger information configuration module sends the descriptor storage address information obtained through analysis to the descriptor reading module under the condition that the first indication information obtained through analysis indicates that the descriptor trigger information is effective.

And the DMA control module executes the data moving time included in the ith descriptor obtained according to analysis under the condition that the descriptor valid signal included in the ith descriptor obtained by analysis indicates that the ith descriptor is valid, and controls the data moving module to move the data stored in the ith first target address in the CPU to the ith second target address in the FPGA.

Optionally, the apparatus further includes:

the format conversion module is used for converting the moved data into a first preset format.

Optionally, the apparatus further comprises at least one module of:

the reporting module is used for reporting data to the CPU;

the DDR module is used for receiving a DDR access request of the double rate synchronous dynamic random access memory sent by the CPU and sending data associated with the DDR access request to the CPU according to the DDR access request;

and the memory mapping module is used for receiving the configuration parameters sent by the CPU.

In a fourth aspect, an embodiment of the present invention provides a data transmission apparatus applied to a central processing unit CPU, the apparatus including:

the descriptor trigger information sending module is used for sending descriptor trigger information to the field programmable gate array FPGA;

Optionally, the descriptor triggering information sending module is specifically configured to:

In a fifth aspect, embodiments of the present invention further provide a processor-readable storage medium storing a computer program for causing the processor to perform the method according to the first aspect or the method according to the second aspect.

In the embodiment of the invention, after the FPGA receives the descriptor trigger information sent by the CPU, the descriptor trigger information can be analyzed to obtain the descriptor storage address information contained in the descriptor trigger information, so that the corresponding descriptor is read from the CPU according to the descriptor storage address information, the read descriptor is analyzed to obtain the data moving time, the data source address information and the data destination address information contained in the descriptor, and the data in the CPU is moved to the FPGA according to the data moving time, the data source address information and the data destination address information.

Therefore, in the embodiment of the invention, the CPU actively issues the descriptor trigger information, triggers the FPGA to actively read the descriptor and analyze the content of the descriptor, so that the data is moved according to the descriptor requirement, and time information is added in the descriptor to control the starting time and the ending time of the data movement, so that the data movement operation is controllable in time. Therefore, in the embodiment of the invention, the CPU informs the FPGA of reading the descriptor, and the FPGA controls the time of carrying out data movement according to the descriptor, wherein the time precision of the FPGA is higher.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments of the present invention will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a flowchart of a data transmission method according to an embodiment of the present invention;

Fig. 2 is a flowchart of another data transmission method according to an embodiment of the present invention;

fig. 3 is a block diagram of a data transmission device according to an embodiment of the present invention;

fig. 4 is a block diagram of another data transmission device according to an embodiment of the present invention;

FIG. 5 is a block diagram illustrating a specific implementation of a data transmission system according to an embodiment of the present invention;

FIG. 6 is a block diagram illustrating a DMA module according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of a data movement flow in an embodiment of the present invention;

FIG. 8 is a schematic diagram of a DMA control module state machine in an embodiment of the invention.

Detailed Description

In the embodiment of the invention, the term "and/or" describes the association relation of the association objects, which means that three relations can exist, for example, a and/or B can be expressed as follows: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship.

The term "plurality" in embodiments of the present invention means two or more, and other adjectives are similar.

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, and it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.

The embodiment of the invention provides a data transmission method, a data transmission device and a storage medium, which are used for solving the problem of lower time accuracy of a DMA transmission mode between a CPU and an FPGA in the prior art.

The CPU and the FPGA in the embodiment of the present invention may be disposed in a terminal device or may be disposed in a network device.

In addition, the method and the device are based on the same application conception, and because the principle of solving the problems by the method and the device is similar, the implementation of the device and the method can be mutually referred to, and the repetition is omitted.

In addition, the technical scheme provided by the embodiment of the invention can be suitable for various systems, especially 5G systems. For example, suitable systems may be global system for mobile communications (global system of mobilecommunication, GSM), code division multiple access (code division multiple access, CDMA), wideband code division multiple access (Wideband Code Division Multiple Access, WCDMA) universal packet Radio service (general packet Radio service, GPRS), long term evolution (long term evolution, LTE), LTE frequency division duplex (frequency division duplex, FDD), LTE time division duplex (time division duplex, TDD), long term evolution-advanced (long term evolution advanced, LTE-a), universal mobile system (universal mobile telecommunication system, UMTS), worldwide interoperability for microwave access (worldwide interoperability for microwave access, wiMAX), 5G New air interface (New Radio, NR), and the like. Terminal devices and network devices are included in these various systems. Core network parts such as evolved packet system (Evloved Packet System, EPS), 5G system (5 GS) etc. may also be included in the system.

The terminal device according to the embodiment of the present invention may be a device that provides voice and/or data connectivity to a user, a handheld device with a wireless connection function, or other processing devices connected to a wireless modem, etc. The names of the terminal devices may also be different in different systems, for example in a 5G system, the terminal devices may be referred to as User Equipment (UE). The wireless terminal device may communicate with one or more Core Networks (CNs) via a radio access Network (Radio Access Network, RAN), which may be mobile terminal devices such as mobile phones (or "cellular" phones) and computers with mobile terminal devices, e.g., portable, pocket, hand-held, computer-built-in or vehicle-mounted mobile devices that exchange voice and/or data with the radio access Network. Such as personal communication services (Personal Communication Service, PCS) phones, cordless phones, session initiation protocol (Session Initiated Protocol, SIP) phones, wireless local loop (Wireless Local Loop, WLL) stations, personal digital assistants (Personal Digital Assistant, PDAs), and the like. The wireless terminal device may also be referred to as a system, subscriber unit (subscriber unit), subscriber station (subscriber station), mobile station (mobile), remote station (remote station), access point (access point), remote terminal device (remote terminal), access terminal device (access terminal), user terminal device (user terminal), user agent (user agent), user equipment (user device), and embodiments of the present invention are not limited in this respect.

The network device according to the embodiment of the present invention may be a base station, where the base station may include a plurality of cells for providing services for the terminal. A base station may also be called an access point or may be a device in an access network that communicates over the air-interface, through one or more sectors, with wireless terminal devices, or other names, depending on the particular application. The network device may be operable to exchange received air frames with internet protocol (Internet Protocol, IP) packets as a router between the wireless terminal device and the rest of the access network, which may include an Internet Protocol (IP) communication network. The network device may also coordinate attribute management for the air interface. For example, the network device according to the embodiment of the present invention may be a network device (Base Transceiver Station, BTS) in a global system for mobile communications (Global System for Mobile communications, GSM) or code division multiple access (Code Division Multiple Access, CDMA), a network device (NodeB) in a wideband code division multiple access (Wide-band Code Division Multiple Access, WCDMA), an evolved network device (evolutional Node B, eNB or e-NodeB) in a long term evolution (long term evolution, LTE) system, a 5G base station (gNB) in a 5G network architecture (next generation system), a home evolved base station (Home evolved Node B, heNB), a relay node (relay node), a home base station (femto), a pico base station (pico), etc., which are not limited in the embodiment of the present invention. In some network structures, the network device may include a Centralized Unit (CU) node and a Distributed Unit (DU) node, which may also be geographically separated.

Multiple-input Multiple-output (Multi Input Multi Output, MIMO) transmissions may each be made between a network device and a terminal device using one or more antennas, and the MIMO transmissions may be Single User MIMO (SU-MIMO) or Multiple User MIMO (MU-MIMO). The MIMO transmission may be 2D-MIMO, 3D-MIMO, FD-MIMO, or massive-MIMO, or may be diversity transmission, precoding transmission, beamforming transmission, or the like, depending on the form and number of the root antenna combinations.

Fig. 1 shows a flow chart of a data transmission method according to an embodiment of the present invention, where the method may be applied to an FPGA, and includes the following steps 101 to 103:

step 101: and receiving descriptor trigger information sent by a Central Processing Unit (CPU).

Wherein the descriptor trigger information (may also be referred to as descriptor trigger) includes descriptor storage address information.

In addition, in the embodiment of the present invention, the data transmission between the CPU and the FPGA adopts the DMA transfer mode, and because of the DMA transfer characteristic, the memory addresses of all descriptors of each descriptor trigger information transfer are continuous, so the descriptor memory address information may include a first start address (also referred to as a first base address) and the number of descriptors. I.e. the first start address of the descriptor and the number of descriptors are indicated in the descriptor trigger information, the memory addresses of all descriptors associated with the descriptor trigger information can be known.

In addition, in the embodiment of the present invention, the CPU may send descriptor trigger information to the FPGA at preset time intervals.

Step 102: analyzing the descriptor trigger information, reading a plurality of descriptors stored in the CPU according to the descriptor storage address information obtained through analysis, and storing the descriptors.

In an embodiment of the present invention, one descriptor trigger information associates a plurality of descriptors, i.e. one descriptor trigger information is used to instruct the FPGA to move the plurality of descriptors into the CPU.

Wherein, alternatively, the descriptors are shifted to 512bit alignment, the shift data amount is 512bit integer multiple, and each descriptor is 128bit, so the shift descriptor amount is 4 or integer multiple of 4.

That is, alternatively, one descriptor trigger is at least one length, and one length of descriptor trigger is used to shift 4 descriptors, and thus one descriptor trigger is used to shift k×4 descriptors, where k is a positive integer.

Step 103: analyzing the ith descriptor, and moving the data stored in the ith first target address in the CPU to the ith second target address in the FPGA according to the data moving time included in the ith descriptor obtained by analysis.

In addition, the descriptor includes a data movement time, data source address information and data destination address information, the data movement time including a start time and an end time of the data movement.

Furthermore, in the embodiment of the present invention, the data transfer between the CPU and the FPGA adopts a DMA transfer manner, and the storage address of all data transferred by each descriptor is continuous due to the DMA transfer characteristic, so the data source address information may include a second start address (may also be referred to as a second base address) and a data length. I.e. the second start address of the data and the data length are indicated in the descriptor, the memory address of all data associated with the descriptor can be known.

As can be seen from steps 102 to 103, the FPGA may store the moved descriptors one by one in sequence, wait for a data start time indicated by each descriptor, and move the data from the source address to the destination address within a required time until the data movement of all the descriptors is completed.

In summary, in the embodiments of the present invention, after receiving the descriptor trigger information sent by the CPU, the FPGA may analyze the descriptor trigger information to obtain the descriptor storage address information included in the descriptor trigger information, so as to read the corresponding descriptor from the CPU according to the descriptor storage address information, further analyze the read descriptor to obtain the data moving time, the data source address information and the data destination address information included in the descriptor, and move the data in the CPU to the FPGA according to the data moving time, the data source address information and the data destination address information.

Therefore, in the embodiment of the invention, the CPU actively issues the descriptor trigger information, triggers the FPGA to actively read the descriptor and analyze the content of the descriptor, so that the data is moved according to the descriptor requirement, and time information is added in the descriptor to control the starting time and the ending time of the data movement, so that the data movement operation is controllable in time.

In the prior art, the data moving time is not strictly controlled, the CPU side actively transmits the descriptor according to the active transmission time such as interrupt, and the FPGA side immediately executes the DMA operation after receiving the descriptor, so that the data moving time is not controlled, but the requirement of each channel data on the BBU on time is strict, generally in microsecond level, so the mode is generally inaccurate.

In the embodiment of the invention, the CPU informs the FPGA of reading the descriptor, and the FPGA controls the time of carrying out data movement according to the descriptor, wherein the time precision of the FPGA is higher, so that the embodiment of the invention can improve the time precision of the DMA transmission mode between the CPU and the FPGA.

In addition, in practical application, the descriptor content of each time slot is basically unchanged, the descriptors are fixedly stored in a section of memory space of the CPU, and the number of the descriptors is large, if the descriptors are actively sent by the CPU, more CPU resources are occupied and the data transmission rate is influenced.

deleting the 1 st to nth descriptors.

It can be seen that, in the embodiment of the present invention, when the data is moved for the last descriptor in all descriptors associated with one descriptor trigger information, all the descriptors associated with the descriptor trigger information are deleted in a unified manner

When the CPU sends a descriptor trigger message to the FPGA at intervals of preset time, the FPGA analyzes the descriptor trigger message, stores address information according to the analyzed descriptor, reads the descriptor from the CPU, stores the read descriptor, synchronously analyzes the stored descriptor, carries out data movement according to the data movement time and the data source address information obtained by analysis, and deletes all the descriptors associated with the descriptor trigger after the data associated with all the descriptors associated with the descriptor trigger are moved, so that the number of the descriptors stored in the FPGA is in dynamic change.

and executing the steps of reading a plurality of descriptors stored in the CPU and storing the descriptors according to the descriptor storage address information obtained through analysis under the condition that the residual space is larger than or equal to the first preset threshold value. Optionally, the method further comprises:

In the embodiment of the invention, time information is added in the descriptor, so that the requirement on the data transmission time is strict, and if the time point of sending the descriptor triggering information is abnormal (such as the problem of filling errors in the data moving time in the descriptor, etc.), the descriptor can be accumulated in a large amount because the initial moving time is not reached and the descriptor is in a waiting state for a long time, or the data amount of a certain descriptor which needs to be moved is more, so that the moving time of a certain time is longer, and the descriptor can be accumulated in a large amount.

The descriptors are processed one by one according to the sequence of the moving back descriptors, so that the time delay is caused by the accumulation of the previous descriptors when the subsequent normal descriptors are processed, and the whole data movement is always in an abnormal state.

Therefore, the embodiment of the invention can also add a timeout protection mechanism, namely after analyzing one descriptor trigger information, judging whether the residual space of the storage space for storing the descriptors is smaller than a first preset threshold value or not, if the current residual space is larger than or equal to the first preset threshold value, indicating that the number of the descriptors stored currently does not reach the preset maximum value, the descriptor trigger information can be normally received, analyzing the received descriptor trigger information, and carrying out descriptor movement according to the descriptor storage address information obtained by analysis; if the current remaining space is smaller than the first preset threshold, the number of the descriptors stored currently reaches the preset maximum value, and therefore a protection mechanism is triggered.

The protection mechanism is as follows: directly discarding the descriptor storage address information obtained by analyzing the descriptor trigger information received at the present time, starting a preset timer, discarding the descriptor storage address information obtained by analyzing the descriptor trigger information within the timing time of the timer until the protection time is over (i.e. until the timer reaches the preset time), and re-judging whether the protection mechanism condition is met.

The number of descriptors (or the remaining space of the storage space for storing descriptors) when the protection mechanism is triggered and the timing time of the timer can be set according to actual needs, for example, the unit of the timing time of the timer is 10 microseconds.

And discarding the descriptor storage address information obtained by current analysis under the condition that the first indication information obtained by analysis indicates that the descriptor trigger information is invalid.

Specifically, each descriptor trigger information may be defined as 64 bits, for example, in the case that the CPU is 24 cores, 24 sets of register addresses may be opened for storing the descriptor trigger information, where each bit definition may be as shown in table 1:

table 1 descriptor trigger definition

Wherein, the "offset address" in table 1 is used to indicate that the information is descriptor trigger information; bit [8:0] in the high 32 bits and the low 32 bits jointly represent a first starting address (namely a first base address) of the descriptor, bit [19:9] represents the number of the descriptors, bit [31] represents the first indication information, namely whether the descriptor triggering information is valid or not, the value is 1, and the descriptor triggering information is valid; a value of 0 indicates that the descriptor trigger information is invalid.

And discarding the data migration time data source address information and the data destination address information included in the i-th descriptor obtained by analysis under the condition that the descriptor valid signal included in the i-th descriptor obtained by analysis indicates that the i-th descriptor is invalid.

In the embodiment of the invention, the FPGA moves data to the CPU according to the descriptor, and comprises a source address, a destination address, a data length, a data movement starting time and a data movement ending time, so that the DMA operation can only realize data movement in the starting time and the ending time.

Specifically, the descriptor may be defined as 128bit data, and the specific definition of each field may be as shown in table 2:

table 2 descriptor field definitions

The specific explanation of each field in table 2 is as follows:

SRC_ADDR_LSB: representing the source address is 32 bits lower, and in units of 64 Bytes, the data must be shifted aligned with 64 Bytes; src_addr_msb: representing 9 bits higher source address;

dest_addr_lsb: representing the destination address as low as 32 bits, with 64 bytes as units, the data must be shifted aligned with 64 bytes; dest_addr_msb: representing 9 bits higher destination address;

HFE: the odd-even field number where the data movement is finished is represented, 0 represents even field, and 1 represents odd field;

HFS: the odd-even field number where the data movement starts is represented, 0 represents even field, and 1 represents odd field;

TST: the initial time of data transfer is shown in 10US, the range is one half frame, and 511 represents instant transmission;

TET: the end time of the data movement is 10US, the range is one half frame, and is used for performing data movement timeout check, and 511 represents no check.

INFO: data associated information, namely attribute information representing data;

VLD: for descriptor valid flag, 0 indicates invalid, 1 indicates valid;

END: a descriptor linked list end flag indicating whether the descriptor is at the end of the linked list;

LEN: the data length is shifted in 64BYTE.

and converting the moved data into a first preset format.

The first preset format is, for example, a random access memory (Random Access Memory, RAM) interface format.

Therefore, in the embodiment of the present invention, after the FPGA moves the data from the CPU, the moved data may be further converted into the first preset format.

The existing DMA design is relatively single in function, and generally has no interface conversion function, but the data format directly output by the DMA may not be convenient for the data processing of the subsequent module. In the embodiment of the invention, on the data output of DMA (direct memory access) movement, for the convenience of data storage and use of other modules, the output data format is converted, for example, the output data is converted from an AXI4 format into a RAM (random access memory) interface format, so that the data is convenient for the next processing. Where AXI denotes advanced extensible interfaces.

Optionally, the method further comprises at least one of the following steps:

reporting data to the CPU;

receiving a Double Data Rate (DDR) access request sent by the CPU, and sending Data associated with the DDR access request to the CPU according to the DDR access request;

and receiving the configuration parameters sent by the CPU.

Other requirements may exist for data interaction between the FPGA and the CPU on the BBU, such as FPGA data reporting, CPU accessing to the DDR on the FPGA side, and CPU actively configuring a small number of parameters to the FPGA.

Fig. 2 shows a flow chart of a data transmission method according to an embodiment of the present invention, where the method may be applied to a CPU, and includes the following steps 201:

step 201: and sending the descriptor trigger information to the field programmable gate array FPGA.

The descriptor includes a data movement time, data source address information and data destination address information, and the data movement time includes a start time and an end time of the data movement.

In addition, in the embodiment of the invention, the data transmission between the CPU and the FPGA adopts a DMA (direct memory access) moving mode, and the storage address of all descriptors of each descriptor trigger information moving is continuous due to the DMA moving characteristic, and the storage address of all data of each descriptor moving is continuous.

Therefore, the descriptor storage address information may include a first start address (also referred to as a first base address) and the number of descriptors, that is, the first start address and the number of descriptors are indicated in the descriptor trigger information, so that the storage addresses of all the descriptors associated with the descriptor trigger information may be known; the data source address information may include a second start address (which may also be referred to as a second base address) and a data length, that is, the second start address and the data length of the data are indicated in the descriptor, so that the storage addresses of all the data associated with the descriptor can be known.

In addition, after receiving the descriptor trigger information sent by the CPU, the FPGA analyzes the descriptor trigger information, stores address information according to the analyzed and obtained descriptors, reads a plurality of descriptors stored in the CPU, stores the read descriptors, analyzes each descriptor, and moves data in the CPU to the FPGA according to data moving time, data source address information and data destination address information included in each analyzed and obtained descriptor.

In the embodiment of the invention, the CPU informs the FPGA of reading the descriptors, and the FPGA controls the time of carrying out data movement according to the descriptors, wherein the time precision of the FPGA is higher, so that the embodiment of the invention can improve the time precision of the DMA transmission mode between the CPU and the FPGA.

Optionally, sending descriptor trigger information to the FPAG includes:

The preset time interval can be configured according to an actual application scene.

Having described the data transmission method provided by the embodiment of the present invention, the data transmission device provided by the embodiment of the present invention will be described with reference to the accompanying drawings.

As shown in fig. 3, an embodiment of the present invention provides a data processing apparatus, applied to an FPGA, including:

an interface conversion module 301, configured to receive descriptor trigger information sent by a central processing unit CPU, where the descriptor trigger information includes descriptor storage address information;

the descriptor trigger information configuration module 302 is configured to parse the descriptor trigger information to obtain the descriptor storage address information;

a descriptor reading module 303, configured to read a plurality of descriptors stored in the CPU according to the descriptor trigger information configuration module 302 and the obtained descriptor storage address information;

a descriptor buffer module 304, configured to store the plurality of descriptors read by the read descriptor module 303, where the descriptors include data moving time, data source address information, and data destination address information;

a DMA control module 305 and a data moving module 306, where the DMA control module 305 is configured to receive an ith descriptor sent by the descriptor cache module 304, parse the ith descriptor, and control the data moving module 306 to move data stored in an ith first target address in the CPU to an ith second target address in the FPGA according to a data moving time included in the ith descriptor obtained by parsing;

deleting the 1 st to nth descriptors.

wherein the read descriptor module

And executing the step of reading a plurality of descriptors stored in the CPU according to the descriptor storage address information obtained by analyzing by the descriptor trigger information configuration module under the condition that the residual space is larger than or equal to the first preset threshold value.

wherein the descriptor trigger information configuration module

And under the condition that the first indication information obtained by analysis indicates that the descriptor trigger information is effective, sending the descriptor storage address information obtained by analysis to the descriptor reading module.

Optionally, the apparatus further includes:

Optionally, the apparatus further comprises at least one module of:

the reporting module is used for reporting data to the CPU;

As shown in fig. 4, an embodiment of the present invention provides a data transmission device applied to a central processing unit CPU, the device including:

the descriptor trigger information sending module 401 is configured to send descriptor trigger information to the field programmable gate array FPGA;

Optionally, the descriptor trigger information sending module 401 is specifically configured to:

It should be noted that, in the embodiment of the present invention, the division of the units is schematic, which is merely a logic function division, and other division manners may be implemented in actual practice. In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.

The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a processor-readable storage medium. Based on such understanding, the technical solution of the present application may be embodied in essence or a part contributing to the prior art or all or part of the technical solution, in the form of a software product stored in a storage medium, including several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor (processor) to perform all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

It should be noted that, the above device provided in the embodiment of the present invention can implement all the method steps implemented in the method embodiment and achieve the same technical effects, and detailed descriptions of the same parts and beneficial effects as those in the method embodiment in this embodiment are omitted.

The embodiment of the invention also provides a data transmission system which comprises the data transmission device applied to the FPGA and the data transmission device applied to the CPU.

Optionally, a specific implementation manner of the data transmission system according to the embodiment of the present invention may be as follows:

as shown in fig. 5, the data transmission system comprises an FPGA and a CPU, where the FPGA includes a BBU, and the BBU includes a PCIE IP core, a first data interconnection module, a second data interconnection module, a DMA module, a channel processing unit, a clock module, at least one reporting module, a format conversion module, and a DDR module;

the CPU is connected with the PCIE IP core through an X16 or X8 or X4 interface, and the PCIE IP core is respectively connected with a master interface (AXI_M) and a slave interface (AXI_S) of the first data interconnection module.

In addition, the DMA module is connected to the read description Fu Jiekou (axi_sg_r) and the read DATA interface (axi_data) of the first DATA interconnection module, the AXI interface of the first DATA interconnection module is connected to the format conversion module, the format conversion module is connected to the DMA write DATA interface (mem_w) of the channel processing unit, the second DATA interconnection module is connected to the AXI of the first DATA interconnection module, and the axi_lite interface of the second DATA interconnection module and the axi_lite interface of the DMA module are connected. The AXI_Lite interface transmits the descriptor trigger and the configuration parameters sent by the CPU, and the DMA is used for dividing the data into the descriptor trigger or the configuration parameters according to the address. Therefore, a DMA transmission path between the CPU and the FPGA is formed through the DMA module, the PCIE IP core, the first data interconnection module, the second data interconnection module, the format conversion module, and the channel processing unit (a specific DMA transmission process will be described in detail later);

The reporting module is connected with a write data interface (AXI_W) of the first data interconnection module, so that a channel for reporting data to the CPU by the FPGA is formed through the reporting module, the first data interconnection module and the PCIE IP core;

the DDR module is connected with an AXI interface of the first data interconnection module, so that a DDR channel for the CPU to access the FPGA is formed through the DDR module, the first data interconnection module and the PCIE IP core;

the AXI_Lite interface of the memory mapping module is connected with the AXI_Lite interface of the second interconnection module, wherein the second data interconnection module is also connected with the AXI of the first data interconnection module, so that a channel for configuring parameters from the CPU to the FPGA is formed.

In addition, the clock module is connected with the DMA module to clock the DMA module.

As can be seen from the above, in the embodiment of the present invention, the BBU of the FPGA mainly includes a PCIE portion, a DMA portion, and a data format conversion portion.

In the first aspect, the PCIE portion is composed of a PCIE IP core and a data interconnection module (i.e., an interconnect IP core), and is mainly responsible for performing PCIE communication with the CPU and an arbitration function before data enters the PCIE. In the design of the PCIE part, for simplicity and stability of the design, an IP core design scheme is adopted, the PCIE IP core adopts an AXI bridge mode, and a data interconnection module is adopted to arbitrate data of a master interface and a slave interface of the input PCIE IP core.

In a second aspect, the DMA portion is configured to perform functions such as descriptor trigger parsing, reading a descriptor, parsing the descriptor, and controlling PCIe to perform data movement, where time information for timing the descriptor is provided by a clock module with a count and a header signal in units of 10 us.

Specifically, as shown in fig. 6, the DMA module includes an interface conversion module, a descriptor trigger information configuration module, a description Fu Banyi module, a DMA control module, a data moving module, and a time control module, where the descriptor moving module includes a logic judgment module, a descriptor reading module, and a descriptor caching module.

The descriptor trigger sent by the CPU passes through the PCIE IP core, the first data interconnection module and the second data interconnection module, so that the descriptor trigger is transmitted to the DMA module, and then is received by the interface conversion module, and format conversion is performed. Because the data format output by the descriptor trigger sent by the CPU is an AXI4_Lite interface format, in order to conveniently analyze the descriptor trigger, the descriptor trigger is firstly converted into data in a RAM interface format in an interface conversion module and then is input into a descriptor trigger information configuration module.

The descriptor trigger information configuration module analyzes the descriptor trigger, and sends the analysis result (including the descriptor storage address information) to the logic judgment module, and the logic judgment module judges whether the descriptor trigger has errors such as length filling 0 and whether the descriptor trigger is in a protection state (the protection state will be described in detail below) currently, so as to determine whether the descriptor needs to be read. And when a plurality of descriptor triggers are continuously received, the module has certain buffer capacity, and the descriptor triggers are prevented from being lost due to the fact that the descriptors are not moved.

And the descriptor moving module reads the descriptor from the CPU through a path among the first data interconnection module, the PCIE IP core and the CPU according to the indication of the logic judging module and the analysis result, and sends the read descriptor to the descriptor caching module for storage.

The descriptor buffer module is used for buffering the received descriptor and synchronously sending the descriptor to the DMA control module, and the DMA control module is used for analyzing the received descriptor to obtain data moving time, data source address information and data destination address information, so that under the control of the time control module, the data moving module is controlled according to the data moving time, and the data in the CPU is moved to the FPGA through a channel among the first data interconnection module, the PCIE IP core and the CPU according to the data source address information and the data destination address information.

It should be noted that, 24 sets of register addresses may be opened in the above-mentioned descriptor trigger information configuration module, for storing the descriptor trigger, for example, in fig. 6, DDPi (LSB) represents a low 32-bit memory address of one descriptor trigger, DDPi (HSB) represents a high 32-bit memory address of one descriptor trigger, that is, DDPi (LSB) and DDPi (HSB) represent memory addresses of one descriptor trigger, and i is an integer from 0 to 23.

As shown in fig. 7, the data migration flow in the embodiment of the present invention is mainly divided into four stages as follows:

the first stage: the CPU generates descriptors and corresponding data thereof at specific addresses, and because of DMA (direct memory access) shifting characteristics, all descriptor addresses shifted by each descriptor trigger are continuous, and the data addresses shifted by the same descriptor are continuous addresses;

and a second stage: the CPU sends a descriptor trigger in the required time;

and a third stage: DMA control in FPGA analyzes descriptor trigger, moves descriptor and caches;

fourth stage: and the DMA module in the FPGA sequentially carries out data movement on the moved descriptors one by one, waits for the data starting time of each descriptor, and moves the data from the source address to the destination address in the required time until the data movement of all the descriptors is completed.

The DMA control module realizes a DMA control function, completes a control flow of whole data movement, and a state machine transition diagram is shown in fig. 8, and comprises the following contents:

1. starting a read descriptor linked list, namely starting a DMA control module to receive the descriptor sent by the descriptor caching module;

2. generating a data movement command according to the descriptor, wherein the data movement command is sent to the data movement module by the DMA control module;

3. Controlling a data movement command sending time point according to the data movement time included in the descriptor;

4. and (3) checking that the linked list moving operation is completed, namely judging whether the received descriptors are the last descriptors in the descriptors associated with the current descriptor trigger (namely, the descriptors of address storage represented by the descriptor address information included in the descriptor trigger) by the DMA control module.

In addition, the data moving module utilizes the existing IP to verify the moving of data, completes the high throughput data transmission between AXI4 memory mappings, supports 4KB address boundary protection and automatically bursts the partition.

In a third aspect, the data format conversion portion is implemented by a format conversion module, that is, the data moved by the data movement module is sent to the format conversion module through the first data interconnection module, the moved data is converted from the AXI4 format to the format of the RAM interface by the format conversion module, and then the converted data is sent to the channel processing unit for storage.

In addition, besides supporting DMA functions, PCIE IP cores in the BBU may further add other AXI interfaces as needed:

the data reported by the reporting module is reported to the CPU through the PCIE IP core;

the DDR module is added to facilitate the CPU to read and write the DDR of the FPGA and is used for realizing functions such as piling and positioning, wherein piling refers to sending a pile file from the CPU to the DDR on the FPGA side through the PCIE IP core and is used for verifying the DDR function and the like, positioning refers to writing data and state information and the like of the DMA module or other node data which can be used for positioning into the DDR in a grabbing mode, and whether abnormal information exists can be positioned by reading the data in the DDR.

The memory mapping module is added and used for supporting the direct configuration of a small amount of parameters of the CPU to the memory mapping module of the FPGA for analysis;

it can be seen that in the embodiment of the present invention, the interfaces have high flexibility, that is, the number of AXI interfaces can be controlled to flexibly increase or decrease according to the needs, so as to implement various functions.

In addition, the embodiment of the invention can also set a DMA exception recovery and protection mechanism, which is specifically as follows:

the descriptor buffer module analyzes the descriptors one by one (i.e. the DMA control module controls the data movement module to complete the data movement associated with one descriptor) by synchronously receiving and storing the descriptors read from the CPU by the descriptor read module, and deleting all the descriptors associated with the last descriptor in all the descriptors associated with one descriptor trigger when the data movement associated with the last descriptor in all the descriptors associated with one descriptor trigger is completed, so that the number of the descriptors stored in the descriptor buffer module is in dynamic change.

In the embodiment of the invention, time information is added in the descriptor, so that the requirement on the data transmission time is strict, and if the abnormal time point of sending the descriptor trigger (such as the problem of filling the data moving time in the descriptor) occurs, a large number of descriptors can be accumulated in the descriptor cache module because the initial moving time cannot be reached and the descriptor is in a waiting state for a long time, or the data amount of a certain descriptor which needs to be moved is more, so that the moving time of a certain time is longer, and a large number of descriptors can be accumulated in the descriptor cache module.

Therefore, the embodiment of the invention can further add a timeout protection mechanism, that is, after the read descriptor module receives the descriptor trigger analyzed by the descriptor trigger information configuration module, it is determined whether the remaining space of the buffer space for buffering the descriptor in the descriptor buffer module is smaller than a preset threshold, if yes, a protection state is entered, that is, the read descriptor module discards the received analyzed descriptor trigger, starts a timer, discards the received analyzed descriptor trigger in a timing time, and after the timing time reaches a preset time (for example, 10 microseconds), it is determined whether the remaining space is smaller than the preset threshold again.

In summary, the embodiments of the present invention have the following advantages:

1. the number of interfaces is flexible and controllable, an AXI interface can be added according to the need, and data interaction is carried out with the PCIE IP core;

2. the descriptor trigger FPAG actively reads the descriptor, so that the CPU occupancy rate can be reduced;

3. multiple descriptors can be moved at one time, and the descriptor buffer capacity of 2k is possessed, so that the data moving efficiency can be improved;

4. adding time information in the descriptor to enable the data moving time to be controllable;

5. the data output interface is converted into the RAM interface, so that the subsequent data storage and use are convenient.

Embodiments of the present invention also provide a processor-readable storage medium storing a computer program for causing the processor to execute the above-described data processing method.

The processor-readable storage medium may be any available medium or data storage device that can be accessed by a processor, including, but not limited to, magnetic storage (e.g., floppy disks, hard disks, magnetic tape, magneto-optical disks (MOs), etc.), optical storage (e.g., CD, DVD, BD, HVD, etc.), semiconductor storage (e.g., ROM, EPROM, EEPROM, nonvolatile storage (NAND FLASH), solid State Disk (SSD)), and the like.

It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, magnetic disk storage, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer-executable instructions. These computer-executable instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These processor-executable instructions may also be stored in a processor-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the processor-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These processor-executable instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims and the equivalents thereof, the present application is intended to cover such modifications and variations.

Claims

1. A data transmission method, applied to a field programmable gate array FPGA, comprising:

2. The data transmission method according to claim 1, wherein after the data stored in the nth first target address in the CPU is moved to the nth second target address in the FPGA according to the data movement time included in the nth descriptor obtained by parsing, the method further comprises:

Deleting the 1 st to nth descriptors.

3. The data transmission method according to claim 2, wherein after parsing the descriptor trigger information, the method further comprises:

4. A data transmission method according to claim 3, characterized in that the method further comprises:

5. The data transmission method according to claim 1, wherein the descriptor trigger information further comprises: the first indication information is used for indicating whether the descriptor triggering information is valid or not;

6. The data transmission method according to claim 1, wherein the descriptor further comprises a descriptor valid signal indicating whether the descriptor is valid;

7. The data transmission method according to claim 1, wherein after moving the data stored in the ith first target address in the CPU to the ith second target address in the FPGA according to the data moving time included in the ith descriptor obtained by parsing, the method further comprises:

And converting the moved data into a first preset format.

8. The data transmission method according to claim 1, characterized in that the method further comprises at least one of the following steps:

reporting data to the CPU;

and receiving the configuration parameters sent by the CPU.

9. A data transmission method applied to a central processing unit CPU, the method comprising:

10. The data transmission method according to claim 9, wherein transmitting descriptor trigger information to the FPAG comprises:

11. A data transmission device for use in a field programmable gate array FPGA, said device comprising:

12. The data transmission device according to claim 11, wherein the DMA control module is configured to control the data movement module to move the data stored in the nth first target address in the CPU to the nth second target address in the FPGA according to the data movement time included in the nth descriptor obtained by the parsing, and the descriptor buffer module is further configured to:

deleting the 1 st to nth descriptors.

13. The data transmission device of claim 12, wherein the data transmission device comprises a plurality of data transmission devices,

the descriptor reading module is further configured to, after receiving the descriptor storage address information parsed by the descriptor trigger information configuration module: judging whether the residual space of the storage space for storing the descriptors is smaller than a first preset threshold value;

wherein the read descriptor module

14. The data transmission apparatus of claim 13, wherein the read descriptor module is further configured to: and under the condition that the residual space is smaller than the first preset threshold value, discarding the currently received descriptor storage address information sent by the descriptor trigger information configuration module, starting a preset timer, discarding the descriptor storage address information sent by the descriptor trigger information configuration module and received within the timing time of the timer until the timing time of the timer reaches the preset time, and returning to the step of judging whether the residual space of the storage space for storing the descriptors is smaller than the first preset threshold value.

15. The data transmission apparatus of claim 11, wherein the descriptor trigger information further comprises: the first indication information is used for indicating whether the descriptor trigger signal is valid or not;

16. The data transmission apparatus of claim 11, wherein the descriptor further comprises a descriptor valid signal indicating whether the descriptor is valid;

17. The data transmission apparatus according to claim 11, wherein the apparatus further comprises:

18. The data transmission apparatus of claim 11, wherein the apparatus further comprises at least one of the following modules:

the reporting module is used for reporting data to the CPU;

19. A data transmission device for use in a central processing unit CPU, said device comprising:

20. The data transmission device according to claim 19, wherein the descriptor trigger information sending module is specifically configured to:

21. A processor-readable storage medium, characterized in that the processor-readable storage medium stores a computer program for causing the processor to perform the method of any one of claims 1 to 8 or to perform the method of any one of claims 9 to 10.