CN116520813B

CN116520813B - FPGA prototype verification method and system of controller

Info

Publication number: CN116520813B
Application number: CN202310780221.4A
Authority: CN
Inventors: 侯佳坤; 谌彤; 乐国庆; 夏少峰
Original assignee: Core Microelectronics Technology Zhuhai Co ltd
Current assignee: Core Microelectronics Technology Zhuhai Co ltd
Priority date: 2023-06-29
Filing date: 2023-06-29
Publication date: 2023-09-12
Anticipated expiration: 2043-06-29
Also published as: CN116520813A

Abstract

The invention discloses a method and a system for verifying an FPGA prototype of a controller, wherein the method comprises the steps of carrying a first delay line and a second delay line which are configurable on the FPGA, and configuring delay values; the controller stores the data acquired in the DDR in the controller according to the received data transmission instruction; the external flash memory device samples and stores data through a clock of the first delay line; the controller acquires a response signal according to the received data receiving instruction, samples data sent by the external flash memory device through a clock of the second delay line, and stores the sampled data in the controller and the DDR; and comparing the consistency of DDR sending data and DDR receiving data to realize the FPGA prototype verification of the controller. According to the embodiment of the invention, the first delay line and the second delay line with the configurable delay values are mounted on the FPGA, so that the simulation of the simulation part in the chip is realized.

Description

FPGA prototype verification method and system of controller

Technical Field

The invention relates to the technical field of prototype verification, in particular to a method and a system for verifying an FPGA prototype of a controller.

Background

eMMC (embedded Multi-Media Controller) and SD card (Secure Digital Memory Card) are information storage devices, and are widely used for embedded devices (e.g., smart phones, tablet computers, etc.) and removable devices (digital cameras, etc.), respectively. Due to the parallel characteristics of the protocol interface and the limitation of the controller, in order to further improve the performance and maintain the stability of the eMMC and SD cards, both add a tuning technology in a higher speed mode, aiming at performing clock phase change and obtaining an optimal sampling point through the design of a hardware controller algorithm, so that the system can operate at a higher frequency and has good stability. Typically, the introduction of tuning techniques requires the support of an analog Delay Line (Delay Line) through which the clock phase is changed to find the sampling point. Therefore, the tuning technology of eMMC and SD cards inevitably requires support of an actual hardware platform in the verification phase. FPGA (Field-Programmable Gate Array, line Field programmable gate array) is used as a reconfigurable hardware platform, the real hardware design can be restored as far as possible, the algorithm and the performance can be estimated more comprehensively, but verification of the simulation technology cannot be realized on the FPGA, so that the delay line simulation part cannot be realized or simulated in the FPGA prototype verification after the eMMC and SD card are added with the tuning technology.

In view of this, overcoming the drawbacks of the prior art is a problem to be solved in the art.

Disclosure of Invention

The invention aims to solve the technical problems that in order to improve the performance and stability of an external flash memory device, a delay line simulation part cannot be realized or simulated in FPGA prototype verification caused by introducing a tuning technology into the external flash memory device.

The invention adopts the following technical scheme:

in a first aspect, the present invention provides a method for verifying an FPGA prototype of a controller, including:

a first delay line and a second delay line with configurable delay values are carried on an FPGA;

the controller sets delay values of the first delay line and the second delay line according to the received delay line configuration instruction, and obtains clocks after the delay of the first delay line and the second delay line;

the controller sends a command to the external flash memory device according to the received data sending instruction, and after a first response signal returned by the external flash memory device is obtained, the data obtained in the DDR is stored in the controller; the external flash memory device samples the data stored in the controller through the clock delayed by the first delay line and stores the data in the external flash memory device;

the controller sends a command to the external flash memory device according to the received data receiving instruction, after a second response signal returned by the external flash memory device is obtained, the controller samples data sent by the external flash memory device through a clock delayed by a second delay line, and the sampled data are respectively stored in the controller and the DDR, wherein the data sent by the external flash memory device are data sampled by the clock delayed by the external flash memory device through the second delay line;

And comparing the consistency of data sent by the DDR with data sent by the DDR and received by the external flash memory device to realize the FPGA prototype verification of the controller.

Preferably, the controller sets delay values of the first delay line and the second delay line according to the received delay line configuration instruction, and specifically includes:

configuring a first preset number of delay units for a first delay line, cascading each delay unit in the first delay line in series, configuring a second preset number of delay units for a second delay line, and cascading each delay unit in the second delay line in series;

the controller configures a delay value of the first delay line and detects a response signal returned by the external flash memory device;

if the response signal is not detected, adjusting the delay value reconfiguration of the first delay line; if the response signal is detected to exist, the first delay line is configured successfully;

the controller executes a tuning algorithm, inputs a clock signal into the second delay line, generates a corresponding delay code value through the tuning algorithm, decodes the second delay line according to the delay code value, outputs a corresponding delay clock, performs data sampling according to the delay clock, performs tuning according to a data sampling result, and configures the delay value of the second delay line.

Preferably, a clock signal is input into the second delay line, a corresponding delay code value is generated by a tuning algorithm, the second delay line decodes according to the delay code value, outputs a corresponding delay clock, performs data sampling according to the delay clock, performs tuning according to a data sampling result, and configures a delay value of the second delay line, including:

standard data pre-stored in a controller are obtained;

numbering the delay units on the second delay line to be 0, 1, … and n according to the transmission sequence of the clock signal, wherein n+1 is the total number of the delay units in the second delay line;

when a delay unit with the number of i executes a tuning link, taking the total delay value of the delay units with the numbers of 0 to i as the delay value of a second delay line, sampling data sent by external flash memory equipment through a clock delayed by the second delay line, and comparing standard data in a controller with the sampled data, wherein i is more than or equal to 0 and less than or equal to n, and i is an integer;

if the delay units are the same, marking the delay units of the i as passing; if the delay units are different, marking the delay units of i as failed;

marking all delay units from the start of the delay unit execution tuning link with the number 0 to the end of the delay unit execution tuning link with the number n;

And selecting the longest delay unit link which is connected and passes, taking the intermediate value of the link as an optimal sampling point, and configuring the delay value of the second delay line through the sampling point.

Preferably, the selecting the longest delay unit link through which all the links pass, and taking the intermediate value of the link as an optimal sampling point, and configuring the delay value of the second delay line through the sampling point specifically includes:

obtaining the numbers of delay units at two ends of the longest delay unit link, averaging the numbers of the delay units at two ends, and obtaining an optimal sampling point;

and taking the delay sum of the delay unit with the number of 0 to the delay unit corresponding to the optimal sampling point as the delay value of the second delay line.

Preferably, the comparing the consistency of the data sent by the DDR with the data sent by the DDR and received by the DDR from the external flash memory device, so as to implement the FPGA prototype verification of the controller, specifically includes:

if the data sent by the DDR is the same as the data sent by the DDR received from the external flash memory device, the FPGA prototype verification of the controller is proved to pass;

if the data sent by the DDR is different from the data sent by the DDR received from the external flash memory device, the FPGA prototype verification of the controller fails, the delay value of the delay line is adjusted, and the FPGA prototype verification of the controller is carried out again.

In a second aspect, the present invention further provides an FPGA prototype verification system of a controller, for implementing the FPGA prototype verification method of the controller of the first aspect, where the system includes a CPU, a DDR, a controller, a first delay line, a second delay line, and an external flash memory device;

the CPU is used for sending a delay line configuration instruction, a data sending instruction and a data receiving instruction;

the DDR is used for storing data which is in data communication with the external flash memory device;

the controller is used for completing the conversion from the DDR internal data to an external flash memory device specified protocol;

the first delay line is used for carrying out phase delay on a clock of data acquired from the DDR by the controller;

the second delay line is used for carrying out phase delay on a clock of data sent by the external flash memory device;

the external flash memory device is used for storing data which is in data communication with the DDR.

Preferably, the FPGA prototype verification system of the controller further comprises a bus bridge and an input/output interface of the FPGA;

the bus bridge is used for address searching so that the controller can receive instructions sent by the CPU and data interaction is carried out between the DDR and the controller;

the input/output interface of the FPGA is used for outputting the data subjected to the phase modulation of the first delay line to an external flash memory device, and outputting the data subjected to the phase modulation of the second delay line to the controller.

Preferably, a first preset number of delay units are arranged in the first delay line, and the delay units are arranged in cascade and used for carrying out phase delay on a clock of data;

a second preset number of delay units and decoders are arranged in the second delay line; the delay units are arranged in cascade and used for carrying out phase delay on a clock of data, and the decoder is used for decoding delay coded values generated by a tuning algorithm.

Preferably, the delay unit is two carry chain delay modules connected in series, and is used for carrying out phase delay on the clock of the data.

The invention realizes the simulation of the simulation part in the chip by carrying the first delay line and the second delay line with configurable delay values on the FPGA; by carrying the first delay line and the second delay line with configurable delay values on the FPGA, the configurable delay can be realized without using an external special delay line chip test daughter board, thereby greatly shortening the prototype verification period of the FPGA and reducing the cost. In addition, the second delay line is a configurable delay line, and can configure a corresponding delay value according to a tuning algorithm, so that the problem that the simulation part of the chip cannot be simulated when a tuning technology is introduced in the prior art can be solved.

Drawings

In order to more clearly illustrate the technical solution of the embodiments of the present invention, the drawings that are required to be used in the embodiments of the present invention will be briefly described below. It is evident that the figures described below are only some embodiments of the invention, from which other figures can be obtained for a person skilled in the art without inventive effort.

FIG. 1 is a flowchart of a method for verifying an FPGA prototype of a controller according to an embodiment of the present invention;

fig. 2 is a schematic diagram of a prototype verification system of a controller FPGA with a delay line according to an embodiment of the present invention;

FIG. 3 is a block diagram of data interaction between an ASIC and an external flash memory device in accordance with an embodiment of the present invention;

FIG. 4 is a schematic diagram of clock delay of internal data of a chip according to an embodiment of the present invention;

FIG. 5 is a detailed flow chart of step 202 in a method for verifying an FPGA prototype of a controller according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a delay cell of Carry8 in a Xilinx FPGA according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of a delay unit according to an embodiment of the present invention for acquiring a second delay line when the delay unit is Carry 8;

FIG. 8 is a detailed flow chart of step 304 in a method for verifying an FPGA prototype of a controller according to an embodiment of the present application;

FIG. 9 is a detailed flow chart of step 405 in a method for verifying an FPGA prototype of a controller according to an embodiment of the present application;

fig. 10 is a detailed flowchart of step 205 in the FPGA prototype verification method of the controller according to the embodiment of the present application.

Detailed Description

The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.

In the description of the present application, the terms "inner", "outer", "longitudinal", "transverse", "upper", "lower", "top", "bottom", etc. refer to an orientation or positional relationship based on that shown in the drawings, merely for convenience of describing the present application and do not require that the present application must be constructed and operated in a specific orientation, and thus should not be construed as limiting the present application.

The terms "first," "second," and the like herein are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", etc. may explicitly or implicitly include one or more such feature. In the description of the present application, unless otherwise indicated, the meaning of "a plurality" is two or more.

In the present application, unless explicitly specified and limited otherwise, the term "connected" is to be construed broadly, and for example, "connected" may be either fixedly connected, detachably connected, or integrally formed; can be directly connected or indirectly connected through an intermediate medium. Furthermore, the term "coupled" may be a means of electrical connection for achieving signal transmission.

In addition, the technical features of the embodiments of the present application described below may be combined with each other as long as they do not collide with each other.

In the prior art, the prior prototype verification schemes for eMMC and SD cards mainly have the following 5 modes:

first, phase-locked loop based authentication scheme: the scheme comprises a CPU, a phase-locked loop, an eMMC and an SD controller, wherein a tuning algorithm is initiated through the controller, and the clock phase is changed through the phase-locked loop. The disadvantage of this technique is that the self-contained phase locked loop in the FPGA has a minimum VCO (voltage-controlled oscillator) oscillation frequency (typically 600 MHz) with a frequency division of maximally 255. And the eMMC and the SD card are in an open-drain state when started, and only the clock frequency of 400KHz at maximum is supported, so that the frequency division is difficult to obtain. On the other hand, an additional logic conversion is needed between the controller and the pll, to convert the output of the controller into the pll interface protocol.

Second, ODDR (Output Double Data Rate ) based authentication scheme: according to the scheme, the CPU, the FPGA IO and the ODDR module are adopted for verification, and because the configurable clock phase cannot be realized, only a lower speed mode can be verified, and the tuning verification cannot be performed.

Third, an external clock delay chip based verification scheme: according to the scheme, an FPGA platform and an external delay chip are adopted to verify a tuning scheme, and an algorithm is initiated by a controller on the FPGA platform to convert the output of the controller into a protocol corresponding to the external chip for adjustment. The disadvantage of this solution is that the verification cost is increased and a protocol conversion module needs to be added between the FPGA platform and the external delay chip.

Fourth, verification scheme based on FPGA delay block: the scheme adopts the original delay module on the FPGA input/output interface to carry out clock delay and can adjust the output clock. The disadvantage of this solution is that an internal clock delay cannot be formed, only the driving clock can be adjusted, and the sampling clock cannot be adjusted.

Fifth, look-Up Table (LUT) based verification scheme: the scheme realizes clock delay based on the lookup table resource of the FPGA, and forms a clock delay chain through delay brought by the clock passing through the lookup table. The disadvantage of this solution is that the delay of each step in the tuning algorithm cannot be averaged and needs to be put in a fixed position without reusability.

The embodiment of the invention provides an FPGA prototype verification method of a controller, as shown in fig. 1, comprising the following steps:

step 201: the method comprises the steps of carrying a first delay line and a second delay line with configurable delay values on an FPGA.

In order to realize the simulation verification process of the simulation part inside the chip in the FPGA prototype verification process of the embodiment of the invention, the embodiment of the invention firstly carries a first delay line and a second delay line which can be configured on the FPGA. It should be noted that, as shown in fig. 2, the structure diagram of the external flash memory device controller FPGA prototype verification system with the corresponding delay line is shown, in the FPGA prototype verification structure diagram, the FPGA actually includes two parts of an analog chip, the digital part in the FPGA prototype verification structure simulates a digital part of an Application Specific Integrated Circuit (ASIC), the analog part in the FPGA prototype verification structure simulates an analog part of an Application Specific Integrated Circuit (ASIC), and for the convenience of understanding, the labeled and Application Specific Integrated Circuit (ASIC) structures of two areas in the FPGA prototype verification structure are identical, and for the FPGA prototype verification structure (see fig. 2), the analog part in the FPGA prototype verification structure is substantially a digital part; it should be appreciated that the analog portion within the FPGA prototyping architecture is essentially another digital portion that differs from that in fig. 2, i.e., another digital portion is used to simulate the analog portion in the chip.

Step 202: the controller sets delay values of the first delay line and the second delay line according to the received delay line configuration instruction, and obtains clocks delayed by the first delay line and the second delay line through the delay values.

The embodiment of the invention comprises two delay lines, wherein the first delay line is arranged on a branch line for transmitting data to the external flash memory device by the DDR and is used for driving a clock of the external flash memory device to perform phase control; the second delay line is arranged on a branch of the external flash memory device for transmitting data to the DDR and is used for controlling the phase of an internal sampling clock. The controller configures delay values of the first delay line and the second delay line respectively through delay line configuration instructions sent by the CPU. It should be noted that, in the embodiment of the present invention, the delay value of the first delay line may be configured according to practical experience, the delay value of the second delay line is decoded by a tuning algorithm and a corresponding decoder, and then the corresponding delay value is obtained and then set by the obtained delay value, and the setting of the delay values of the first delay line and the second delay line will be described in detail later herein, which will not be repeated herein.

Step 203: the controller sends a command to the external flash memory device according to the received data sending instruction, and after a first response signal returned by the external flash memory device is obtained, the data obtained from the DDR is stored in the controller; the external flash memory device samples data stored in the controller by the clock delayed by the first delay line and stores the data in the external flash memory device.

The external flash memory device of the embodiment of the invention comprises an eMMC card and an SD card. Referring to fig. 3 and 4, in the circuit design of the control interface units of the eMMC card and the SD card, the circuit design is divided into two parts, i.e., a digital circuit and an analog circuit, and the controller belongs to the digital part. Referring to fig. 2, the CPU of the digital part transmits a data transmission instruction, and the controller receives the instruction transmitted by the CPU and transmits a command to the external flash memory device, the purpose of the controller transmitting the command being to acquire a first response signal returned from the external flash memory device. By whether the first response signal of the external flash memory device can be acquired, it can be determined whether the delay value of the first delay line is set to be reasonable. According to the eMMC protocol (Embedded Multi-Media Card Electrical Standard) and the SD protocol (SD specific standards) of the embodiments of the present invention, when the external flash memory device does not send the first response signal, it is indicated that the delay value of the first delay line is not configured reasonably, and the delay value of the first delay line needs to be reset until the first response signal fed back by the external flash memory device can be received. After the controller receives the first response signal, firstly the controller stores data which is required to be transmitted to the external flash memory device in the DDR in the controller, then the controller sends a clock signal to the first delay line, the external flash memory device samples the data stored in the controller through the clock delayed by the first delay line, and the sampled data is stored in the external flash memory device.

Step 204: the controller sends a command to the external flash memory device according to the received data receiving instruction, after obtaining a second response signal returned by the external flash memory device, the controller samples data sent by the external flash memory device through a clock delayed by a second delay line, and the sampled data are respectively stored in the controller and the DDR, wherein the data sent by the external flash memory device are data sampled by the clock delayed by the external flash memory device through the second delay line.

Referring to fig. 2, a CPU sends a data receiving instruction, a controller receives the instruction sent by the CPU and sends a command to an external flash memory device, acquires a second response signal of the external flash memory device (the second response signal can be normally acquired, which indicates that the external flash memory device is ready, and the controller can sample data in the external flash memory device), and after receiving the second response signal, the controller sends a clock signal to a second delay line, and samples the data sent by the external flash memory device by a clock after the second delay line, and stores the sampled data in the controller; and then, the data acquired from the external flash memory device in the controller is transmitted to the DDR for storage through the bus bridge. It should be noted that, in the embodiment of the present invention, a corresponding register is provided in the controller, and data in the controller is actually stored in the corresponding register. In addition, the first response signal and the second response signal of the embodiment of the invention are sent by the external flash memory device, so that whether the delay value of the first delay line is reasonable can be verified through the first response signal and the second response signal.

Step 205: and comparing the consistency of data sent by the DDR with data sent by the DDR and received by the external flash memory device to realize the FPGA prototype verification of the controller.

After the data in the controller is verified after corresponding clock delay, detecting whether the data in the controller changes (for example, the data is missing or data is wrong, etc.) so as to realize the FPGA prototype verification of the controller. According to the embodiment of the invention, the data in the DDR is stored in the external flash memory device, and then the data stored in the external flash memory device is stored in the DDR. Comparing the data sent by the DDR with the data of the DDR, and if the data are consistent, indirectly indicating that the data transmission function in the controller is accurate (the design in the controller operates normally); if the two data are inconsistent, the data transmission function in the controller is indirectly indicated to be accurate (the design in the controller operates abnormally), so that the FPGA prototype verification of the controller is realized.

To illustrate the distinction of the present invention from the prior art in the background, the prior art and the present invention are now compared and analyzed as follows:

The delay line formed by the delay unit (for example, carry 8) can solve the technical problems presented in prototype verification of eMMC and SD controllers in the prior art, and is specifically as follows:

1. compared with the prior art scheme 1, the delay unit (for example, carry 8) resources adopted in the scheme have no vibration frequency requirement, the frequency ranges (400 KHz to 200 MHz) expressed in the eMMC and SD protocols can be delayed through the delay line, the prior art scheme 1 cannot support the clock frequency to 400KHz, the eMMC or SD card cannot be started, and the verification purpose cannot be achieved. In addition, the original output of the controller is only needed to be used for configuring the delay line, and the purpose of prototype verification can be better achieved without additional logic conversion.

2. Compared with the prior art scheme 2, the scheme can use a tuning algorithm, and can configure any delay between 0 and n (the value of n is set according to the actual situation), thereby verifying a mode with higher speed. However, the conventional scheme 2 can only perform 180-degree phase inversion, and cannot implement a tuning algorithm.

3. Compared with the prior art scheme 3, the scheme can be realized by adopting the resources of the delay unit (for example, the carry 8) in the prior FPGA without adding an external chip.

4. Compared with the prior art 4, the method can delay the internal clock and output the delayed internal clock or delay the internal clock and then continuously use the internal clock. And scheme 4 cannot achieve the same effect and cannot achieve the tuning algorithm.

5. Compared with the prior art scheme 5, the scheme benefits from the position fixing property of the delay unit (for example, the carry 8) resources in the FPGA, and the delay unit (for example, the carry 8) resources in the FPGA are arranged in a cascade mode, so that the scheme does not need to limit the position of each delay unit (for example, the carry 8), can be automatically arranged by an FPGA tool, can effectively control and average the delay value of each step, enables a tuning algorithm to be more accurate, does not need any change when the FPGA chip is replaced, and has good consistency and reusability. In the prior art 5, the position of each lookup table needs to be manually placed, wiring delay is difficult to control, delay line results generated by comprehensive realization of each time of FPGA are inconsistent, a tuning algorithm in a high-speed mode is easy to fail due to delay difference, the consistency is not high, and the multiplexing performance is not achieved.

Therefore, the embodiment of the invention realizes the simulation of the simulation part in the chip by carrying the first delay line and the second delay line with the configurable delay values on the FPGA; by carrying the first delay line and the second delay line with configurable delay values on the FPGA, the configurable delay can be realized without using an external special delay line chip test daughter board, thereby greatly shortening the prototype verification period of the FPGA and reducing the cost. In addition, the second delay line is a configurable delay line, and can configure a corresponding delay value according to a tuning algorithm, so that the problem that the simulation part of the chip cannot be simulated when a tuning technology is introduced in the prior art can be solved.

In order to present a complete solution of the embodiments of the present invention, details of the embodiments of the present invention are set forth in the following. The controller sets the delay values of the first delay line and the second delay line according to the received delay line configuration instruction, as shown in fig. 5, and specifically includes:

step 301: the method comprises the steps of configuring a first preset number of delay units for a first delay line, cascading each delay unit in the first delay line in series, configuring a second preset number of delay units for a second delay line, and cascading each delay unit in the second delay line in series.

The first preset number and the second preset number in the embodiment of the present invention may be set according to actual requirements, and the first preset number may be equal to the second preset number or may be set unequal to the second preset number, for example, but not limited to, the first preset number and the second preset number may be set to 128. It should be noted that the present invention is a powerful delay unit, but not limited to, a Carry8 delay unit, and each Carry8 delay unit may be regarded as a Carry4, as shown in fig. 6, which shows an architecture diagram of a Carry8 delay unit in an FPGA according to an embodiment of the present invention, where a Carry8 resource has 8bit data input ports D [7:0], 8bit MUX (selector) selection ports S [7:0], 8bit MUX output ports CO [7:0], 8bit exclusive or output ports O [7:0] and 1bit Carry input port CIN. In this patent scheme, D [7:0] in each stage of Carry8 is set to 0, S [7:0] is set to 1, and the clock input is connected with CIN, so that the clock input can be output from CO [7] after passing through 8 selectors, and the delay of the part is a fixed value. Each Carry8 resource can be regarded as two Carry4 resources, and implementation by adopting similar Carry4 resources also belongs to the protection category of the scheme.

Step 302: the controller configures a delay value of the first delay line and detects a response signal returned from the external flash memory device.

The first delay line does not participate in the tuning algorithm, so that the delay value of the first delay line is actually a set value, the delay value of the first delay line is set according to actual experience, then the configuration is carried out through the controller, and whether the delay value of the first delay line is set reasonably or not is judged by utilizing response signals returned by the external flash memory device.

Step 303: if the response signal is not detected, adjusting the delay value of the first delay line to reconfigure; if the presence of the response signal is detected, the first delay line configuration is successful.

When the external flash memory device is monitored to send out a corresponding response signal, the delay value set by the first delay line is reasonable, and the delay value is used as the delay value of the first delay line; when the external flash memory device is monitored to not send out the corresponding response signal, the delay value set for the first delay line at the moment is unreasonable, then the delay value of the first delay line is adjusted, whether the external flash memory device sends out the corresponding response signal is monitored again until the delay value of the first delay line is set, and the external flash memory device is monitored to send out the corresponding response signal.

Step 304: the controller executes a tuning algorithm, inputs a clock signal into the second delay line, generates a corresponding delay code value through the tuning algorithm, decodes the second delay line according to the delay code value, outputs a corresponding delay clock, performs data sampling according to the delay clock, performs tuning according to a data sampling result, and configures the delay value of the second delay line.

In order to enable the FPGA prototype verification method of the embodiment of the present invention to be performed under a tuning function, the delay value of the second delay line of the embodiment of the present invention is processed by a tuning algorithm and then by a corresponding decoder, a corresponding delay clock is output, data sampling is performed by the delay clock, and the delay value of the second delay line is configured by a final result. Based on the above, the FPGA prototype verification method of the embodiment of the invention is suitable for a tuning function, and under the tuning function, the embodiment of the invention can simulate the progress of the simulation part in the chip, thereby realizing the simulation of the whole process of the chip.

In addition, a specific feasible decoder is provided in the embodiment of the present invention, as shown in fig. 7, when the delay unit selects the Carry8 delay unit, the embodiment of the present invention may be implemented by using a binary tree unit of the decoder to decode and using a lookup table resource in the FPGA, where the output of each Carry8 stage may be selected and output by a register DE [6:0], DE [6] is used to select the Carry8 output of the higher 64 stages or the lower 64 stages, DE [5] is used to select the Carry8 output of the higher 32 stages or the lower 32 stages in the higher 64 stages or the lower 64 stages, and so on, and DE [6:0] may cover the outputs of the Carry8 stages 0-127. In addition, in order to make the Carry8 delay unit more universal, the embodiment of the invention can also use a lookup table at the clock input port to realize 4-input 1-output selection and can switch between different clocks.

Next, to more precisely describe the content of step 304 of the embodiment of the present invention, a clock signal is input into the second delay line, a corresponding delay code value is generated by a tuning algorithm, the second delay line decodes according to the delay code value, outputs a corresponding delay clock, performs data sampling according to the delay clock, performs tuning according to the result of the data sampling, and configures a delay value of the second delay line, as shown in fig. 8, specifically including:

step 401: standard data stored in advance in the controller is acquired.

The FPGA prototype verification of the embodiment of the invention is used for verifying whether the data in the controller can be completely changed before and after delay. According to the embodiment of the invention, the standard data is stored in the controller in advance, the clock signal corresponding to the data is processed through the corresponding delay line in the data transmission process, so that the data is delayed, and whether the tuning algorithm passes or not can be known (succeeds) by sampling the delayed data and comparing the sampled data with the standard data.

Step 402: and numbering the delay units on the second delay line as 0, 1, … and n according to the transmission sequence of the clock signals, wherein n+1 is the total number of the delay units in the second delay line.

The delay units in the second delay line in the embodiment of the invention are cascaded in series, and the delay line processes the clock signal input by the controller. During the processing, an input clock signal is input from the first delay unit and then output from the last delay unit.

Step 403: when the delay unit with the number i executes a tuning link, taking the total delay value of the delay units with the numbers 0 to i as the delay value of the second delay line, sampling data sent by the external flash memory device through a clock delayed by the second delay line, and comparing standard data in the controller with the sampled data, wherein i is more than or equal to 0 and less than or equal to n, and i is an integer.

In the process of acquiring the delay value of the second delay line, the clock signal is input into the delay unit of the second delay line, is input from the first delay unit, and is output from the last delay unit. In this process, each delay unit corresponds to a tuning link, and a process of data sampling and comparison needs to be performed once, at this time, a delay value of the second delay line needs to be set for sampling, where the delay value is a temporarily set value, and when data sampling is performed in the tuning links with different numbers, the delay values corresponding to the second delay line are different. Because the delay units in the second delay line of the embodiment of the invention are arranged in a cascade connection mode; thus, when a tuning link is performed on the delay unit with the number i, the delay value of the corresponding second delay line is the total delay of the delay units with the numbers 0 to i, for example, when i=0, the delay value of the corresponding second delay line is the delay of one delay unit; when i=1, the delay value of the corresponding second delay line is the delay value of two delay units, and so on, when i=n, the delay value of the corresponding second delay line is the delay value of n+1 delay units, and in order to ensure the stability of the system inside the chip, the delay values of the delay units with different numbers are generally set to be the same because the first delay line and the second delay line of the embodiment of the invention are both configurable delay lines.

Step 404: if the delay units are the same, marking the delay units of the i as passing; if not, the delay cell of i is marked as failed.

The controller is used for sampling the data in each tuning link and comparing the data with the standard data in the controller. After each comparison, marking the corresponding delay unit as passing or failing, and marking the delay unit as passing when the acquired data is the same as the standard data; and when the acquired data is different from the standard data, marking as failure.

Step 405: sequentially starting a delay unit execution tuning link of number 0 to n (n is the number with the largest delay unit, and the number of the delay units in the delay line is n+1 at the moment), ending the delay unit execution tuning link, and marking all the delay units; and selecting the longest delay unit link which is connected and passes, taking the intermediate value of the link as an optimal sampling point, and configuring the delay value of the second delay line through the sampling point.

After all the tuning links are executed, all the delay units in the second delay line are correspondingly marked, and the longest delay unit link which is connected in the second delay line and passes through is selected. Taking the median value as a sampling point, and calculating the delay value of the second delay line.

Step 405 of the embodiment of the present invention may be further specifically refined, where the selecting the longest delay cell link through which all the links pass, and taking the intermediate value of the link as the optimal sampling point, and configuring the delay value of the second delay line through the sampling point, as shown in fig. 9, specifically includes:

step 501: and obtaining the numbers of delay units at the two ends of the longest delay unit link, averaging the numbers of the delay units at the two ends, and obtaining an optimal sampling point.

The setting process of the delay value for the second delay line according to the embodiment of the present invention will be described in detail below with specific examples. Assuming that 128 delay units are provided in the second delay line in the embodiment of the present invention, 128 tuning links need to be provided, and pass or fail are marked in the corresponding 128 delay units. Assuming that after all delay units are marked, there is a section of longest delay unit link, where the link is composed of delay units numbered 10 to 30, and the average number at this time is (10+30)/2=20, and the optimal sampling point is the delay unit numbered 20. It is worth to say that when the optimal sampling point is calculated to be decimal, the optimal sampling point adopts a one-in or one-out method to determine the optimal sampling point; for example, when the link is composed of delay units numbered 11 to 30, and the number average value is (11+30)/2=20.5, the optimal sampling point is a delay unit numbered 20 or a delay unit numbered 21. The optimal sampling point is selected only for determining the delay value of the second delay line when the data transmission is most stable, so that errors of data in the FPGA prototype verification process are avoided as much as possible.

Step 502: and taking the delay sum of the delay unit with the number of 0 to the delay unit corresponding to the optimal sampling point as the delay value of the second delay line.

When the optimal sampling point is obtained, the delay corresponding to the optimal sampling point is generally set as the delay value of the second delay line. Because the delay units in the second delay line in the embodiment of the invention adopt cascade connection, the delay value of the optimal sampling point is actually the sum of the delays from the delay unit with the number of 0 to the delay unit corresponding to the optimal sampling point. For example, assuming that the optimal sampling point is calculated as a delay unit numbered 20, the delay of the second delay line is the total delay of delay units numbered 0 to 20.

In the real-time example of the present invention, the consistency of the data sent by the DDR and received from the external flash memory device is compared to realize the prototype verification of the FPGA of the controller, as shown in fig. 10, which specifically includes:

step 601: and if the data sent by the DDR is the same as the data sent by the DDR received from the external flash memory device, the FPGA prototype verification of the controller is passed.

Step 602: if the data sent by the DDR is different from the data sent by the DDR received from the external flash memory device, the FPGA prototype verification of the controller fails, the delay value of the delay line is adjusted, and the FPGA prototype verification of the controller is carried out again.

For step 601 and step 602, in the embodiment of the present invention, the data sent by the DDR is compared with the data received by the DDR, and whether the data is the same or not is determined, so that the FPGA prototype verification process has been described in association with the foregoing, which is not described herein. It should be noted that, in the embodiment of the present invention, the data sent by the external flash memory device is data transmitted in the DDR; for example, assuming that the DDR transmits data a to the external flash memory device, the external flash memory device stores the data a in the external flash memory device, and then transmits the data a to the DDR through the external flash memory device, and compares the original data a in the DDR with the transmitted data a.

According to the embodiment of the invention, the first delay line and the second delay line with the configurable delay values are mounted on the FPGA, so that simulation of the simulation part in the chip is realized; by carrying the first delay line and the second delay line with configurable delay values on the FPGA, the configurable delay can be realized without using an external special delay line chip test daughter board, thereby greatly shortening the prototype verification period of the FPGA and reducing the cost. In addition, the second delay line is a configurable delay line, and can configure a corresponding delay value according to a tuning algorithm, so that the problem that the simulation part of the chip cannot be simulated when a tuning technology is introduced in the prior art can be solved. According to the scheme, two delay lines are realized in 1 FPGA chip, wherein one delay line is used for controlling the clock phase of a driving channel from the controller to the eMMC and the SD card, and the other delay line is used for controlling the clock phase of a sampling channel in the controller. The delay line of the drive path ensures that the timing of the eMMC and SD cards receiving the controller data is correct, while the delay line of the sampling path ensures that the tuning algorithm mechanism is executed in the high frequency mode.

The embodiment of the invention also provides an FPGA prototype verification system of the controller, which is used for realizing the FPGA prototype verification method of the controller, as shown in fig. 4, wherein the system comprises a CPU, a DDR, a controller, a first delay line, a second delay line and external flash memory equipment;

The FPGA prototype verification system of the controller comprises delay units, wherein no two carry chain delay modules connected in series are arranged in each delay unit, and the carry chain delay modules are used for carrying out phase delay on clocks of data. For example, when the delay unit is a Carry8 delay unit, the corresponding Carry chain delay module is Carry4.

In order to realize data transmission, the FPGA prototype verification system of the controller in the embodiment of the invention further comprises a bus bridge; the bus bridge is used for address searching so that the controller can receive instructions sent by the CPU and data interaction is carried out between the DDR and the controller. The input/output interface of the FPGA is used for outputting data and the clock phase-delayed by the first delay line to the external flash memory device, and outputting data sampled by the clock phase-delayed by the second delay line to the controller.

In order to enable the FPGA prototype verification system of the controller of the embodiment of the invention to be suitable for a tuning function, a first preset number of delay units are arranged in the first delay line of the embodiment of the invention, and the delay units are arranged in cascade and are used for carrying out phase delay on a clock of data;

a second preset number of delay units and decoders are arranged in the second delay line; the delay units are arranged in cascade and are used for carrying out phase delay on a clock of data, and the decoder is used for decoding a delay coding value generated by a tuning algorithm; the delay unit is two carry chain delay modules connected in series and is used for carrying out phase delay on the clock of the data.

The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.

Claims

1. An FPGA prototype verification method of a controller, comprising:

the method comprises the steps of carrying a first delay line and a second delay line with configurable delay values on an FPGA, configuring a first preset number of delay units for the first delay line, cascading each delay unit in the first delay line in series, configuring a second preset number of delay units for the second delay line, and cascading each delay unit in the second delay line in series;

the controller sets delay values of the first delay line and the second delay line according to the received delay line configuration instruction, and obtains clocks delayed by the first delay line and the second delay line through the delay values;

wherein the configuration of the delay value of the second delay line comprises: executing a tuning algorithm by the controller, inputting a clock signal into the second delay line, generating a corresponding delay code value through the tuning algorithm, decoding the second delay line according to the delay code value, outputting a corresponding delay clock, performing data sampling according to the delay clock, performing tuning according to a data sampling result, and configuring a delay value of the second delay line;

The controller sends a command to the external flash memory device according to the received data sending instruction, and after a first response signal returned by the external flash memory device is obtained, the data obtained from the DDR is stored in the controller; the external flash memory device samples the data stored in the controller through the clock delayed by the first delay line and stores the data in the external flash memory device;

2. The method for verifying the FPGA prototype of the controller according to claim 1, wherein the configuration of the delay value of the first delay line specifically includes:

if the response signal is not detected, adjusting the delay value of the first delay line to reconfigure; if the presence of the response signal is detected, the first delay line configuration is successful.

3. The FPGA prototype-verification method of the controller according to claim 2, wherein the inputting the clock signal into the second delay line, generating the corresponding delay code value by a tuning algorithm, decoding the second delay line according to the delay code value, outputting the corresponding delay clock, sampling data according to the delay clock, and tuning according to the result of the data sampling, and configuring the delay value of the second delay line includes:

standard data pre-stored in a controller are obtained;

numbering delay units on the second delay line as 0, 1, … and n according to the transmission sequence of the clock signal, wherein n+1 is the total number of delay units in the second delay line;

and selecting the longest delay unit link through which each delay unit passes, taking the intermediate value of the longest delay unit link as an optimal sampling point, and configuring the delay value of the second delay line through the sampling point.

4. The method for verifying the FPGA prototype of the controller according to claim 3, wherein selecting the longest delay unit link through which each delay unit passes, and using the intermediate value of the longest delay unit link as the optimal sampling point, and configuring the delay value of the second delay line through the sampling point comprises:

5. The FPGA prototype-verification method as set forth in claim 1, wherein the comparing the consistency of the data sent by the DDR with the data sent by the DDR received from the external flash memory device to implement the FPGA prototype-verification of the controller includes:

6. An FPGA prototype-verification system of a controller, for implementing the FPGA prototype-verification method of the controller according to any one of claims 1 to 5, the system comprising a CPU, a DDR, a controller, a first delay line, a second delay line, and an external flash memory device;

7. The FPGA prototype-verification system of a controller in accordance with claim 6, further comprising a bus bridge;

the bus bridge is used for address searching so that the controller can receive instructions sent by the CPU and data interaction is carried out between the DDR and the controller.

8. The controller's FPGA prototype-verification system as claimed in claim 6, further comprising an input-output interface of the FPGA;

the input/output interface of the FPGA is used for outputting data and the clock phase-delayed by the first delay line to the external flash memory device, and outputting data sampled by the clock phase-delayed by the second delay line to the controller.

9. The FPGA prototype-verification system of the controller according to claim 6, wherein a first preset number of delay units are disposed in the first delay line, and the delay units are disposed in cascade, and are used for performing phase delay on a clock of data;

10. The FPGA prototype-verification system of the controller of claim 9, wherein the delay unit is two carry chain delay modules connected in series for phase delaying the clock of the data.