CN116507195B - Based on WO x /YO y Preparation method of double-heterojunction structure analog memristor - Google Patents
Based on WO x /YO y Preparation method of double-heterojunction structure analog memristor Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 41
- 238000000151 deposition Methods 0.000 claims abstract description 83
- 230000008021 deposition Effects 0.000 claims abstract description 63
- 238000004544 sputter deposition Methods 0.000 claims abstract description 47
- 238000000034 method Methods 0.000 claims abstract description 34
- 238000003860 storage Methods 0.000 claims abstract description 32
- 230000008569 process Effects 0.000 claims abstract description 24
- 238000004088 simulation Methods 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 16
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 64
- 239000010410 layer Substances 0.000 claims description 39
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 35
- 239000001301 oxygen Substances 0.000 claims description 35
- 229910052760 oxygen Inorganic materials 0.000 claims description 35
- 229910052786 argon Inorganic materials 0.000 claims description 32
- 238000005137 deposition process Methods 0.000 claims description 29
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 26
- 239000002356 single layer Substances 0.000 claims description 26
- 238000005240 physical vapour deposition Methods 0.000 claims description 22
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical group [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 18
- 229910052721 tungsten Inorganic materials 0.000 claims description 18
- 239000010937 tungsten Substances 0.000 claims description 18
- 239000010931 gold Substances 0.000 claims description 12
- 229910052727 yttrium Inorganic materials 0.000 claims description 12
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical group [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 claims description 12
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 11
- 229910052737 gold Inorganic materials 0.000 claims description 11
- 239000010949 copper Substances 0.000 claims description 10
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 10
- 229910052697 platinum Inorganic materials 0.000 claims description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 8
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 8
- 229910052802 copper Inorganic materials 0.000 claims description 8
- 238000005516 engineering process Methods 0.000 claims description 8
- 239000013077 target material Substances 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims 1
- 238000004364 calculation method Methods 0.000 abstract description 5
- 230000015654 memory Effects 0.000 abstract description 5
- 238000013528 artificial neural network Methods 0.000 abstract description 3
- 239000010408 film Substances 0.000 description 147
- 230000008859 change Effects 0.000 description 20
- 239000010409 thin film Substances 0.000 description 18
- 229910052751 metal Inorganic materials 0.000 description 15
- 239000002184 metal Substances 0.000 description 15
- 238000010586 diagram Methods 0.000 description 11
- 239000002609 medium Substances 0.000 description 7
- 230000007547 defect Effects 0.000 description 5
- 239000007789 gas Substances 0.000 description 5
- 230000001105 regulatory effect Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000001276 controlling effect Effects 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 3
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 2
- 229910001882 dioxygen Inorganic materials 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- ZNOKGRXACCSDPY-UHFFFAOYSA-N tungsten trioxide Chemical compound O=[W](=O)=O ZNOKGRXACCSDPY-UHFFFAOYSA-N 0.000 description 2
- 125000000129 anionic group Chemical group 0.000 description 1
- 230000006399 behavior Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- WUKWITHWXAAZEY-UHFFFAOYSA-L calcium difluoride Chemical group [F-].[F-].[Ca+2] WUKWITHWXAAZEY-UHFFFAOYSA-L 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 239000013630 prepared media Substances 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000004576 sand Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 229910052723 transition metal Inorganic materials 0.000 description 1
- 229910000314 transition metal oxide Inorganic materials 0.000 description 1
- -1 transition metal yttrium oxide Chemical class 0.000 description 1
- 238000005019 vapor deposition process Methods 0.000 description 1
- RUDFQVOCFDJEEF-UHFFFAOYSA-N yttrium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[Y+3].[Y+3] RUDFQVOCFDJEEF-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/021—Formation of the switching material, e.g. layer deposition
- H10N70/026—Formation of the switching material, e.g. layer deposition by physical vapor deposition, e.g. sputtering
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a method based on WO x /YO y A preparation method of a double heterojunction structure analog memristor belongs to the field of nonvolatile memories. The preparation steps of the simulated memristor are as follows: depositing a conductive film on a substrate to serve as a lower electrode of the analog memristor; deposition of continuous WO on lower electrode by sputtering process x /YO y /WO x /YO y Film layer, preparation of WO x /YO y The double heterostructure is used as a medium storage layer of the analog memristor; depositing a conductive film on the dielectric storage layer as an upper electrode to obtain a dielectric storage layer based on WO x /YO y The double heterojunction structure simulates a memristor. The simulated memristor prepared by the method is controllable, is easy to realize scale, can realize controllable adjustment of the conductive channel, effectively improves the simulation performance, and has good market application prospect in the aspect of neural network calculation.
Description
Technical Field
The invention belongs to the technical field of nonvolatile memories, and particularly relates to a nonvolatile memory based on WO x /YO y A preparation method of a double heterojunction structure simulation memristor.
Background
In recent years, the nonvolatile analog memristor has a huge application prospect in-memory calculation and neuromorphic calculation. In this case, the memory device is also tasked with computation while it is tasked with data storage. Therefore, it is of profound interest to realize an analog memristor with high performance. The main stream memristors are based on the principle of conductive channels, and how to effectively control the formation and fracture of the conductive channels and realize the gradual change of the device conductance from abrupt change is a main problem faced by the current memristors. Therefore, the high-performance analog memristor with high dynamic range, high retention characteristic, good tolerance, high conversion speed and the like can be obtained by designing from the aspects of selection of memristor materials, construction of a device structure and the like.
Transition metal oxides are currently the storage medium for mainstream memristors, with tungsten trioxide compatible with CMOS processes considered as a very promising memristive material. The memristor prepared based on the method has excellent resistance change characteristics, such as larger storage window, multi-state storage and other performances. In addition, the transition metal yttrium oxide has high thermal stability and excellent electrical properties, and has good application prospects in nonvolatile storage and neuromorphic devices. Stable stoichiometry Y thereof 2 O 3 The crystal with cubic fluorite structure is oneThe metastable component with the orthorhombic crystal Pnma structure has the advantages that oxygen defects are easily embedded into a stoichiometric yttrium matrix, and the metastable component has good application prospect in realizing stable resistance change performance. In addition, yttria has a higher defect density because up to 25% of the anionic subcellular sites remain unoccupied. They form non-intersecting conductive channels such as vacancy chains along the crystal structure. Therefore, the yttrium oxide has good application prospect in the field of memristors.
However, the current analog memristors based on the above two storage layers lack related designs and researches by using WO x And YO y The preparation of the heterojunction structure to realize the simulated resistance characteristics with stability and excellent properties is not reported.
Disclosure of Invention
In order to overcome the disadvantages of the prior art described above, the object of the present invention is to provide a process based on WO x /YO y Preparation method of double heterojunction structure simulation memristor for solving existing problem based on WO x And YO y And (3) simulating the technical problem that the performance of the memristor cannot be realized.
In order to achieve the above purpose, the invention is realized by adopting the following technical scheme:
the invention discloses a method based on WO x /YO y The preparation method of the double heterojunction structure simulation memristor comprises the following steps:
1) Depositing a conductive film on a substrate by adopting a physical vapor deposition process to serve as a lower electrode;
2) WO is continuously deposited on the lower electrode prepared in the step 1) by adopting a sputtering process x /YO y /WO x /YO y The thin film layer is used for preparing a double heterojunction structure as a medium storage layer of the analog memristor;
3) Depositing a conductive film on the medium storage layer prepared in the step 2) by adopting a physical vapor deposition process to serve as an upper electrode to obtain a dielectric film based on WO x /YO y Analog memristors of double heterojunction structure.
Preferably, in step 1) and step 3), the upper electrode is selected to be an inert gold or platinum, active copper or tungsten conductive film; the lower electrode is selected to be an inert gold or platinum and active copper conductive film.
Preferably, in step 2), WO is deposited x The sputtering source of the film adopts tungsten target material to deposit YO y The sputtering source of the film is yttrium target material; WO (WO) x And YO y The films are all deposited by adopting a radio frequency magnetron sputtering mode.
Preferably, in step 2) a monolayer of WO x The film deposition time is 2-5 minutes; monolayer YO y The film deposition time is 0.4 to 1 minute.
Preferably, in step 2), WO x The radio frequency sputtering power of the film is 50-200 watts; YO (Yo) y The radio frequency sputtering power of the film is 50-180 watts.
Preferably, in step 2), WO x The film deposition temperature is 150-350 ℃; YO (Yo) y The film deposition temperature is 100-350 ℃.
Preferably, in the step 2), argon and oxygen are simultaneously introduced in the deposition process; WO (WO) x The flow rate of argon is 20-40 sccm and the flow rate of oxygen is 5-20 sccm in the film deposition process; YO (Yo) y The flow rate of argon in the film deposition process is 10-30 sccm, and the flow rate of oxygen is 5-20 sccm.
Preferably, in step 1) and step 3), the thickness of the lower electrode is 80 to 150 nm; the thickness of the upper electrode is 80-200 nanometers.
The invention also provides a preparation method based on WO x /YO y The double heterojunction structure simulates a memristor.
Compared with the prior art, the invention has the following beneficial effects:
one of the invention is based on WO x /YO y Preparation method of double heterojunction structure analog memristor, and device prepared by the method utilizes WO x /YO y The double heterojunction structure ensures that the resistance change characteristic has the characteristic of slow change by regulating and controlling the formation and fracture process from the upper electrode to the lower electrode, and has wide application prospect in the field of nonvolatile analog memories. Depositing a conductive film on a substrate by a physical vapor deposition process as a lower electrode, and similarly, adopting physicalThe vapor deposition process obtains a stable and reliable upper electrode, thereby providing a guarantee for simulating the high reliability of the memristor; deposition of WO on the bottom electrode by RF magnetron sputtering x /YO y The double heterojunction thin film layer unit is a key for obtaining the simulated memristive performance; and a physical vapor deposition process is adopted to deposit a conductive film on the dielectric storage layer as an upper electrode, so that a guarantee is provided for further realizing the simulation of the memristor.
Furthermore, inert gold and/or platinum are selected as upper and lower electrodes of the analog memristor, so that the influence of the electrodes on the resistance change characteristic can be reduced, and only oxygen holes in the dielectric layer participate in the resistance change characteristic; active metal atoms and oxygen defects in the electrodes can participate in the resistance change behavior together by using active copper and/or tungsten conductive films as upper and lower electrodes, and the resistance change simulation performance can be regulated and controlled well.
Further, tungsten targets and yttrium targets were chosen as deposition WO x Film and YO y The oxygen defect in the film can be effectively regulated and controlled by combining the target material of the film with the introduced oxygen; the prepared film has higher uniformity and high compactness, and is the basis for realizing excellent simulated resistance change characteristics.
Further, monolayer WO x The film deposition time is 2-5 minutes, and the single-layer YO y The film deposition time is 0.4 to 1 minute; above the deposition time range, the thickness of the prepared film becomes large, and the simulated resistance performance is affected; below this deposition time frame, the device fabricated is prone to breakdown.
Further, WO x The radio frequency sputtering power of the film is selected to be 50-200W, YO y The radio frequency sputtering power of the film is set to be 50-180 watts. The preparation efficiency of the film is low below the radio frequency sputtering power range, and the surface evenness of the film is poor above the radio frequency sputtering power range, so that the analog resistance change performance of the device is affected.
Further, in the deposition process of the thin film, WO x The film deposition temperature is 150-350 ℃ and YO y The film deposition temperature is 100-350 ℃. Below this deposition temperature range, the surface particles of the film become large and flatThe integrity is poor, the performance of the device is affected, and the surface morphology of the film is also poor in the temperature range.
Further, in WO x And YO y Argon and oxygen are introduced in the film deposition process; WO (WO) x The flow rate of argon is 20-40 sccm and the flow rate of oxygen is 5-20 sccm in the film deposition process; YO (Yo) y The flow rate of argon is 10-30 sccm and the flow rate of oxygen is 5-20 sccm in the film deposition process. The thickness of the prepared film is uncontrollable below the range of the gas flow rate; above the aforementioned flow rate range of the gas, the morphology of the thin film becomes poor, and the device stability becomes poor.
Further, the thickness of the lower electrode is 80-150 nm, and the thickness of the upper electrode is 80-200 nm. The adhesion between the films is poor due to the excessively thick electrodes, and the films are easily broken down due to the excessively thin electrodes.
One of the invention is based on WO x /YO y The double-heterojunction structure simulation memristor has the advantages of controllable preparation method, easiness in realization of scale, capability of realizing controllable adjustment of a conductive channel, effective improvement of simulation performance and good market application prospect in the aspect of neural network calculation.
Drawings
FIG. 1 is a diagram of the WO-based preparation of example 1 x /YO y The double heterojunction structure simulates a memristor structure schematic diagram.
FIG. 2 is a diagram of the WO-based product of example 1 x /YO y The double heterojunction structure simulates a direct voltage-current plot of a memristor.
FIG. 3 is a diagram of the WO-based preparation of example 1 x /YO y The double heterojunction structure simulates a continuous variation graph of device conductance of the memristor at different reset voltages.
FIG. 4 is a diagram of the WO-based product of example 1 x /YO y The double heterojunction structure simulates LTD and LTP patterns of memristors under successive pulses.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
The invention is described in further detail below with reference to the attached drawing figures:
currently, WO is used x /YO y The implementation of a double heterojunction structure to simulate a memristor has not been reported. In view of this, the present invention is directed to a method of using WO x /YO y The double heterojunction structure simulates the memristor to regulate and control the formation and breaking process of the conductive channel, and excellent simulated resistance change characteristics are obtained.
Based on WO x /YO y The preparation method of the double heterojunction structure simulation memristor comprises the following steps:
depositing a conductive film on a substrate by adopting a physical vapor deposition process to serve as a lower electrode;
the radio frequency magnetron sputtering technology is adopted to control the working power, the substrate deposition temperature, the flow rate of the reaction gas and the time parameter, and the continuous WO is deposited on the lower electrode x /YO y /WO x /YO y The thin film layer is used for preparing a double heterojunction structure as a medium storage layer of the analog memristor;
further adopting a physical vapor deposition process to deposit a conductive film on the medium storage layer as an upper electrode to obtain the dielectric storage layer based on WO x /YO y The double heterojunction structure simulates a memristor.
Specifically, the upper electrode is an inert gold or platinum, active copper or tungsten conductive film; the lower electrode is an inert gold or platinum and active copper conductive film.
In particular, WO x The sputtering source of the film is tungsten target material; YO (Yo) y The sputtering source of the film is yttrium target material; WO (WO) x And YO y The films are all deposited by adopting a radio frequency magnetron sputtering mode.
In particular, correspond to WO x The deposition time of the single-layer film is 2-5 minutes; corresponding to YO y Single layer film deposition time 0And 4-1 min.
In particular, WO x The sputtering power of the thin film is 50-200 watts; YO (Yo) y The sputtering power of the film is 50-180 watts.
In particular, WO x The film deposition temperature is 150-350 ℃; the YO y The film deposition temperature is 100-350 ℃.
Specifically, argon and oxygen are simultaneously introduced in the deposition process; WO (WO) x The flow rate of argon is 20-40 sccm and the flow rate of oxygen is 5-20 sccm in the film deposition process; YO (Yo) y The flow rate of argon in the film deposition process is 10-30 sccm, and the flow rate of oxygen is 5-20 sccm.
Specifically, the thickness of the lower electrode is 80-150 nanometers; the thickness of the upper electrode is 80-200 nanometers.
The invention also provides a device based on WO x /YO y Preparation method of double heterojunction structure simulation memristor, and structure of built device sequentially comprises a lower electrode and WO (WO) from bottom to top x /YO y A double heterojunction dielectric layer and an upper electrode, which belong to the field of nonvolatile memories; compared with the digital characteristic of memristors based on single-layer dielectric layers, the preparation method of the invention, WO x /YO y The double heterojunction device realizes excellent analog resistance change characteristics.
The invention provides a method based on WO x /YO y The preparation method of the double heterojunction structure simulation memristor comprises the following steps:
s1, adopting a physical vapor deposition process to deposit SiO 2 Depositing a conductive film on the Si substrate as a lower electrode;
preferably, the lower electrode is an inert metal Pt conductive film;
preferably, the thickness of the lower electrode film is 100 nm.
S2, adopting a radio frequency sputtering method, controlling working power, substrate deposition temperature, gas flow rate and time, and depositing continuous WO on the lower electrode x /YO y /WO x /YO y The thin film layer is used for preparing a double heterojunction structure as a medium storage layer of the analog memristor;
preferably, a metallic tungsten target and a metallic yttrium target are used as sputtering sources;
preferably, WO x The deposition time of the monolayer film is 5 minutes; corresponding to YO y The monolayer film deposition time was 1 minute.
Preferably, WO x The film radio frequency sputtering power is 100 watts; YO (Yo) y The film sputtering power was 100 watts.
Preferably, WO x The film deposition temperature is 250 ℃; YO (Yo) y The film deposition temperature was 250 ℃.
In particular, WO x The flow rate of argon in the film deposition process is 30 sccm, and the flow rate of oxygen is 10 sccm; YO (Yo) y The flow rate of argon gas in the film deposition process is 15sccm, and the flow rate of oxygen gas is 15sccm.
S3, depositing a conductive film on the substrate by adopting a physical vapor deposition process to serve as an upper electrode;
preferably, the upper electrode is a metal tungsten conductive film;
preferably, the thickness of the upper electrode film is 100 nm.
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Example 1
Based on WO x /YO y The preparation method of the double heterojunction structure simulation memristor comprises the following steps:
1) Physical vapor deposition technology is adopted to deposit SiO 2 /SAnd depositing a Pt conductive film on the substrate as a lower electrode, wherein the thickness of the lower electrode is 100 nanometers.
2) Selecting a metal tungsten target and a metal yttrium target as sputtering sources, and sequentially performing YO on a lower electrode by adopting a radio frequency magnetron sputtering mode y 、WO x 、YO y And WO x Film deposition: WO (WO) x The deposition time of the monolayer film is 5 minutes; YO (Yo) y The deposition time of the monolayer film is 1 minute; WO (WO) x Film sputtering power of 100W, YO y The film sputtering power is 100 watts; WO (WO) x And YO y The film deposition temperature is 250 ℃; WO (WO) x The flow rate of argon is 30 sccm and the flow rate of oxygen is 10 sccm in the film deposition process; YO (Yo) y The flow rate of argon is 15sccm and the flow rate of oxygen is 15sccm in the film deposition process;
preparation of continuous WO x /YO y /WO x /YO y A dielectric storage layer of the thin film layer.
3) And adopting a physical vapor deposition process to deposit a tungsten conductive film on the dielectric storage layer as an upper electrode, wherein the thickness of the upper electrode is 100 nanometers.
Referring to FIG. 1, FIG. 1 is a schematic diagram of a WO-based process prepared in example 1 x /YO y The double heterojunction structure simulates a structural schematic diagram of the memristor, and comprises a substrate, a Pt lower electrode, a double heterojunction structure storage layer and a tungsten upper electrode from bottom to top.
Referring to FIG. 2, FIG. 2 is a diagram of the WO-based preparation of example 1 x /YO y The voltage-current curve diagram of the double heterojunction structure analog memristor can be seen from the graph that the resistance change device presents the analog memristance characteristic.
Referring to FIG. 3, FIG. 3 is a diagram of the WO-based preparation of example 1 x /YO y The double heterojunction structure simulates the conductance curve of the memristor, and the graph shows that the conductance of the device can be continuously changed by regulating and controlling the reset cut-off voltage.
Referring to FIG. 4, FIG. 4 is a diagram of the WO-based preparation of example 1 x /YO y The LTD and LTP test results of the double-heterojunction structure simulation memristor in the pulse mode can be seen from the graph, and the electricity with high symmetry and linearity is obtainedAnd guiding the response result.
Example 2
Based on WO x /YO y The preparation method of the double heterojunction structure simulation memristor comprises the following steps:
1) Physical vapor deposition technology is adopted to deposit SiO 2 And depositing an Au conductive film on the Si substrate as a lower electrode, wherein the thickness of the lower electrode is 80 nanometers.
2) Selecting a metal tungsten target and a metal yttrium target as sputtering sources, and sequentially performing YO on a lower electrode by adopting a radio frequency magnetron sputtering process y 、WO x 、YO y And WO x Film deposition: WO (WO) x The deposition time of the monolayer film is 5 minutes; YO (Yo) y The deposition time of the monolayer film is 1 minute; WO (WO) x Film sputtering power of 100W, YO y The film sputtering power is 100 watts; WO (WO) x And YO y The deposition temperature of the thin film is 250 ℃; WO (WO) x The flow rate of argon is 30 sccm and the flow rate of oxygen is 10 sccm in the film deposition process; YO (Yo) y The flow rate of argon is 15sccm and the flow rate of oxygen is 15sccm in the film deposition process;
preparation of continuous WO x /YO y /WO x /YO y A dielectric storage layer of the thin film layer.
3) And depositing a platinum conductive film on the dielectric storage layer by adopting a physical vapor deposition process as an upper electrode, wherein the thickness of the upper electrode is 80 nanometers.
In the embodiment 2, the lower electrode adopts a gold film with the thickness of 80 nanometers, the upper electrode adopts a platinum film with the thickness of 80 nanometers; the electrode thickness of the device prepared in example 2 was thinned compared to the device prepared in example 1, resulting in deterioration of the stability of the device; the lower electrode is gold and the upper electrode is platinum, resulting in poor device reliability.
Example 3
Based on WO x /YO y The preparation method of the double heterojunction structure simulation memristor comprises the following steps:
1) Physical vapor deposition technology is adopted to deposit SiO 2 Depositing active Cu conductive film on Si substrate as bottom electrode with thickness of150 nm.
2) Selecting a metal tungsten target and a metal yttrium target as sputtering sources, and sequentially performing YO on a lower electrode by adopting a radio frequency magnetron sputtering mode y 、WO x 、YO y And WO x Film deposition: WO (WO) x The deposition time of the monolayer film is 2 minutes; YO (Yo) y The deposition time of the monolayer film is 0.4 minutes; WO (WO) x Film sputtering power of 100W, YO y The film sputtering power is 100 watts; WO (WO) x And YO y The film deposition temperature is 250 ℃; WO (WO) x The flow rate of argon is 30 sccm and the flow rate of oxygen is 10 sccm in the film deposition process; YO (Yo) y The flow rate of argon is 15sccm and the flow rate of oxygen is 15sccm in the film deposition process;
preparation of continuous WO x /YO y /WO x /YO y A dielectric storage layer of the thin film layer.
3) And depositing an inert gold conductive film on the dielectric storage layer by adopting a physical vapor deposition process as an upper electrode, wherein the thickness of the upper electrode is 200 nanometers.
In the embodiment 3, the lower electrode adopts active copper with the thickness of 150 nanometers, the upper electrode adopts inert gold with the thickness of 200 nanometers; WO (WO) x The deposition time of the monolayer film is 2 minutes; YO (Yo) y The monolayer film deposition time was 0.4 minutes. Compared with the device prepared in the embodiment 1, the thickness of the upper electrode and the thickness of the lower electrode of the device prepared in the embodiment 3 are both thickened, the adhesion force between the device electrode and the medium storage layer are poor, and the reliability of the analog memristor is poor; WO (WO) x And YO y The deposition time of the single-layer film is shortened, the thickness of the prepared medium storage layer is reduced, and the reliability of the analog resistance change is deteriorated.
Example 4
Based on WO x /YO y The preparation method of the double heterojunction structure simulation memristor comprises the following steps:
1) Physical vapor deposition technology is adopted to deposit SiO 2 And depositing a Pt conductive film on the Si substrate as a lower electrode, wherein the thickness of the lower electrode is 100 nanometers.
2) Selecting a metal tungsten target and a metal yttrium target as sputtering sources, and adopting radio frequency magnetron sputteringBy sequentially carrying out YO on the lower electrode y 、WO x 、YO y And WO x Film deposition: WO (WO) x The deposition time of the monolayer film is 5 minutes; YO (Yo) y The deposition time of the monolayer film is 1 minute; WO (WO) x Film sputtering power of 20W, YO y The film sputtering power is 50 watts; WO (WO) x The film deposition temperature is 150 ℃; YO (Yo) y The film deposition temperature is 100 ℃; WO (WO) x The flow rate of argon is 30 sccm and the flow rate of oxygen is 10 sccm in the film deposition process; YO (Yo) y The flow rate of argon is 15sccm and the flow rate of oxygen is 15sccm in the film deposition process;
preparation of continuous WO x /YO y /WO x /YO y A dielectric storage layer of the thin film layer.
3) And depositing an active Cu conductive film on the dielectric storage layer by adopting a physical vapor deposition process to serve as an upper electrode, wherein the thickness of the upper electrode is 100 nanometers.
Example 4 active Cu, WO x Film sputtering power of 20W, YO y The film sputtering power is 50 watts; WO (WO) x The film deposition temperature is 150 ℃; YO (Yo) y The film deposition temperature was 100 ℃. Compared with example 1, the too low film radio frequency sputtering power in example 4 results in thin film thickness and poor device performance; too low a film deposition temperature results in poor morphology of the film and poor reliability of the simulated resistance change.
Example 5
Based on WO x /YO y A simulated memristor similar to a superlattice structure and a preparation method thereof comprise the following steps:
1) Physical vapor deposition technology is adopted to deposit SiO 2 And depositing a Pt conductive film on the Si substrate as a lower electrode, wherein the thickness of the lower electrode is 100 nanometers.
2) Selecting a metal tungsten target and a metal yttrium target as sputtering sources, and sequentially performing YO on a lower electrode by adopting a radio frequency magnetron sputtering mode y 、WO x 、YO y And WO x Film deposition: WO (WO) x The deposition time of the monolayer film is 5 minutes; YO (Yo) y The deposition time of the monolayer film is 1 minute; WO (WO) x Film sputtering power of 200W, YO y The film sputtering power is 180 watts; WO (WO) x And YO y The film deposition temperature is 350 ℃; WO (WO) x The flow rate of argon is 20 sccm and the flow rate of oxygen is 5sccm in the film deposition process; YO (Yo) y The flow rate of argon is 10 sccm and the flow rate of oxygen is 5sccm in the film deposition process;
preparation of continuous WO x /YO y /WO x /YO y A dielectric storage layer of the thin film layer.
3) And adopting a physical vapor deposition process to deposit a W conductive film on the dielectric storage layer as an upper electrode, wherein the thickness of the upper electrode is 100 nanometers.
Example 5 WO x Film sputtering power of 200W, YO y The film sputtering power is 180 watts; WO (WO) x And YO y The film deposition temperature is 350 ℃; WO (WO) x The flow rate of argon is 20 sccm and the flow rate of oxygen is 5sccm in the film deposition process; YO (Yo) y The flow rate of argon gas during film deposition was 10 sccm and the flow rate of oxygen gas was 5sccm. In example 5, too high sputtering power resulted in an increase in roughness of the thin film compared to example 1, resulting in deterioration in stability of the device; too high a deposition temperature results in fewer defects in the film, so that the simulated resistance properties are poor; too low argon and oxygen flow rates result in increased roughness, which also deteriorates the stability of the device.
Example 6
Based on WO x /YO y The preparation method of the double heterojunction structure simulation memristor comprises the following steps:
1) Physical vapor deposition technology is adopted to deposit SiO 2 And depositing a Pt conductive film on the Si substrate as a lower electrode, wherein the thickness of the electrode is 100 nanometers.
2) Selecting a metal tungsten target and a metal yttrium target as sputtering sources, and sequentially performing YO on a lower electrode by adopting a radio frequency magnetron sputtering mode y 、WO x 、YO y And WO x Film deposition: WO (WO) x The deposition time of the monolayer film is 5 minutes; YO (Yo) y The deposition time of the monolayer film is 1 minute; WO (WO) x Film sputtering power of 100W, YO y The film sputtering power is 100 watts; WO (WO) x And YO y The deposition temperature of the thin film is 250 ℃; WO (WO) x The flow rate of argon is 40 sccm and the flow rate of oxygen is 20 sccm in the film deposition process; YO (Yo) y The flow rate of argon is 30 sccm and the flow rate of oxygen is 20 sccm in the film deposition process;
preparation of continuous WO x /YO y /WO x /YO y A dielectric storage layer of the thin film layer.
3) And adopting a physical vapor deposition process to deposit a W conductive film on the dielectric storage layer as an upper electrode, wherein the thickness of the upper electrode is 100 nanometers.
Example 6 WO x The flow rate of argon in the film deposition process is 40 sccm, and the flow rate of oxygen is 20 sccm; YO (Yo) y The argon flow rate was 30 sccm and the oxygen flow rate was 20 sccm during the film deposition process. In example 6, the higher argon flow rate and oxygen flow rate resulted in an increase in the thickness of the thin film and a deterioration in the stability of the device as compared with example 1.
In summary, the present invention provides a method based on WO x /YO y The preparation method of the double heterojunction structure simulation memristor has the following characteristics:
1) The invention provides a method based on WO x /YO y The preparation method of the double-heterojunction structure simulation memristor is characterized in that the double-heterojunction structure is designed, so that the prepared device realizes excellent simulation resistance change performance.
2) The invention provides a method based on WO x /YO y The preparation method of the double-heterojunction structure simulation memristor is controllable, is easy to realize scale, realizes controllable adjustment of the conductive channel, changes resistance characteristics from abrupt change to gradual change, effectively improves simulation performance of the memristor, and has good market application prospect in the aspect of neural network calculation.
The above is only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited by this, and any modification made on the basis of the technical scheme according to the technical idea of the present invention falls within the protection scope of the claims of the present invention.
Claims (4)
1. Based on WO x /YO y The preparation method of the double heterojunction structure simulation memristor is characterized by comprising the following steps of:
1) Physical vapor deposition technology is adopted to deposit SiO 2 Depositing a conductive film on the Si substrate as a lower electrode;
2) Deposition of continuous WO on the bottom electrode produced in step 1) using a sputtering process x /YO y /WO x /YO y Film layer, preparation of WO x /YO y The double heterojunction structure is used as a medium storage layer of the analog memristor;
3) Depositing a conductive film on the medium storage layer prepared in the step 2) by adopting a physical vapor deposition process to serve as an upper electrode to obtain a dielectric film based on WO x /YO y Analog memristors of double heterojunction structures;
in step 2), WO x And YO y The films are all deposited by adopting a radio frequency magnetron sputtering mode, and the WO x The sputtering source of the film is tungsten target material, YO y The sputtering source of the film is yttrium target material; said WO x The film radio frequency sputtering power is 50-200 watts, and the YO y The film radio frequency sputtering power is 50-180W, corresponding to WO x The deposition time of the single-layer film is 2-5 minutes, which corresponds to YO y The deposition time of the monolayer film is 0.4-1 min, argon and oxygen are simultaneously introduced in the deposition process, and the WO x The flow rate of argon is 20-40 sccm, the flow rate of oxygen is 5-20 sccm, and the YO y The flow rate of argon is 10-30 sccm and the flow rate of oxygen is 5-20 sccm in the film deposition process, wherein the WO x The film deposition temperature is 150-350 ℃, and the YO y The film deposition temperature is 100-350 ℃.
2. A WO-based according to claim 1 x /YO y The preparation method of the double heterojunction structure analog memristor is characterized in that in the step 1) and the step 3), the upper electrode is an inert gold, platinum, active copper or tungsten conductive film; the lower electrode is an inert gold, platinum or active copper conductive film.
3. A WO-based according to claim 1 x /YO y The preparation method of the double heterojunction structure simulation memristor is characterized in that the thickness of the lower electrode is 80-150 nanometers; the thickness of the upper electrode is 80-200 nanometers.
4. WO-based manufactured by the manufacturing method according to any one of claims 1 to 3 x /YO y Analog memristors of double heterojunction structure.
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