CN116504809A - Semiconductor device with a semiconductor device having a plurality of semiconductor chips - Google Patents
Semiconductor device with a semiconductor device having a plurality of semiconductor chips Download PDFInfo
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- CN116504809A CN116504809A CN202310443425.9A CN202310443425A CN116504809A CN 116504809 A CN116504809 A CN 116504809A CN 202310443425 A CN202310443425 A CN 202310443425A CN 116504809 A CN116504809 A CN 116504809A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 103
- 230000000149 penetrating effect Effects 0.000 claims abstract description 3
- 239000010410 layer Substances 0.000 claims description 150
- 239000011229 interlayer Substances 0.000 claims description 19
- 238000007667 floating Methods 0.000 claims description 5
- 230000003071 parasitic effect Effects 0.000 abstract description 8
- 238000004519 manufacturing process Methods 0.000 description 15
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- 238000002513 implantation Methods 0.000 description 5
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
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- 238000004140 cleaning Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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Abstract
The invention discloses a semiconductor device, comprising: a semiconductor body having a first main surface and a second main surface opposite to the first main surface; a drift layer provided between the first main surface and the second main surface; a well layer provided closer to the first main surface than the drift layer; an emitter layer provided on the first main surface side of the well layer; an emitter electrode electrically connected to the emitter layer; an active trench penetrating the emitter layer and the well layer from the first main surface in the thickness direction of the semiconductor body and reaching the drift layer; the split gate electrode is arranged in the active groove and is electrically connected with the emitter electrode; a gate electrode disposed within the active trench, the gate electrode being disposed on only one of opposite sides of the split gate electrode; the insulating films are arranged at intervals between the gate electrode, the split gate electrode and the inner wall of the active trench and are insulated from each other by the insulating films. The semiconductor device reduces parasitic capacitance, reduces input capacitance and output capacitance of the semiconductor device, and reduces switching loss.
Description
Technical Field
The present invention relates to the field of semiconductor technology, and in particular, to a semiconductor device.
Background
In the trench gate semiconductor device (Insulated Gate Bipolar Transi stor, IGBT) of the related art, a buried field plate (split gate electrode 1) connected to an emitter (or ground) is added under the gate, and as shown in fig. 1, an oxide layer (dielectric layer) is present between the split gate electrode 1 and the gate electrode 2 for isolation. Due to the split gate electrode 1 shorting to the emitter, the capacitance between the gate electrode 2 and the collector (Cgc) is reduced, but the parasitic gate-emitter capacitance Cge is increased inside the device. In addition, the semiconductor device has excessively high saturation current density due to the trench density, so that the short-circuit capability of the semiconductor is degraded, and the parasitic capacitance Cge between the gate and the emitter is increased due to the excessively high trench gate density, so that the switching speed of the device is reduced, and the switching power consumption is increased.
Disclosure of Invention
The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, an object of the present invention is to propose a semiconductor device which reduces parasitic capacitance, reduces input capacitance and output capacitance of the semiconductor device, and reduces switching loss.
In order to achieve the above object, according to an embodiment of the present invention, there is provided a semiconductor device including: a semiconductor body having a first main surface and a second main surface opposite to the first main surface; a drift layer of a first conductivity type provided between the first main surface and the second main surface; a well layer of a second conductivity type provided closer to the first main surface than the drift layer; an emitter layer of a first conductivity type selectively provided on the first main surface side of the well layer; an emitter electrode electrically connected to the emitter layer; an active trench penetrating the emitter layer and the well layer from the first main surface in a thickness direction of the semiconductor body and reaching the drift layer; a split gate electrode provided in the active trench and extending from the first main surface to a lower portion of the active trench, the split gate electrode being electrically connected to the emitter electrode; a gate electrode provided within the active trench and extending from the first main surface to an upper portion of the active trench, the gate electrode being provided only on one of opposite sides of the split gate electrode, the gate electrode bottom surface being located within the drift layer, the gate electrode bottom surface being closer to the first main surface than the split gate electrode bottom surface; and an insulating film, wherein the gate electrode, the split gate electrode and the inner wall of the active trench are arranged at intervals and insulated from each other by the insulating film.
The semiconductor device according to the embodiment of the invention reduces parasitic capacitance, reduces input capacitance and output capacitance of the semiconductor device, and reduces switching loss.
According to some embodiments of the invention, the other of the opposite sides of the split gate electrode is opposite to the well layer and the drift layer via the insulating film, and the side of the gate electrode facing away from the split gate electrode is opposite to the emitter layer, the well layer, and the drift layer via the insulating film.
According to some embodiments of the invention, the semiconductor device further comprises: and an interlayer insulating film provided on the first main surface, wherein the emitter electrode is formed on an upper portion of the active trench through the interlayer insulating film, and the emitter layer and the well layer are in contact with the emitter electrode via contact holes, which are open portions of the interlayer insulating film, and the emitter layer and the well layer are electrically connected to the emitter electrode, respectively.
According to some embodiments of the invention, the active trenches are a plurality of spaced apart; the split gate electrodes are arranged in a plurality of active trenches in a one-to-one correspondence manner; the plurality of gate electrodes are arranged in a plurality of active trenches in a one-to-one correspondence manner; the gate electrode in one of the two adjacent active trenches is arranged adjacent to the split gate electrode in the other active trench; the contact holes are formed between two adjacent active trenches.
According to some embodiments of the invention, the active trenches are a plurality of spaced apart; the split gate electrodes are arranged in a plurality of grooves in a one-to-one correspondence manner; the plurality of gate electrodes are arranged in a plurality of grooves in a one-to-one correspondence manner; the gate electrodes in two adjacent active trenches are arranged adjacently, and/or the split gate electrodes in two adjacent active trenches are arranged adjacently; the interlayer insulating film is integrally arranged between two active trenches adjacent to the split gate electrode without forming the contact hole; the contact hole is formed between two active trenches adjacent to the gate electrode.
According to some embodiments of the invention, the well layer and the drift layer are disposed in a region opposite to each other between two active trenches where the split gate electrodes are disposed adjacently, and the well layer is a floating well layer.
According to some embodiments of the invention, a cross-sectional area of a portion of the split gate electrode opposite to the gate electrode is smaller than a cross-sectional area of the remaining portion of the split gate electrode in a thickness direction perpendicular to the semiconductor substrate.
According to some embodiments of the invention, the cross-sectional area enlargement of the split gate electrode is located below the bottom surface of the gate electrode.
According to some embodiments of the invention, the cross-sectional area of the split gate is constant along the depth of the trench.
According to some embodiments of the invention, the semiconductor device further comprises: a collector layer of a second conductivity type provided on the second main surface side; a cutoff layer of a first conductivity type, the cutoff layer being provided between the collector layer and the drift layer; wherein the cut-off layer and the drift layer have the same ions, and the ion concentration of the cut-off layer is greater than that of the drift layer.
Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The foregoing and/or additional aspects and advantages of the invention will become apparent and may be better understood from the following description of embodiments taken in conjunction with the accompanying drawings in which:
fig. 1 is a schematic structural view of a semiconductor device of the related art.
Fig. 2 is a schematic structural view of a semiconductor device according to an embodiment of the present invention.
Fig. 3 is a schematic structural view of a semiconductor device according to another embodiment of the present invention.
Fig. 4 is a sectional view of a state of a manufacturing process of a semiconductor device according to an embodiment of the present invention.
Fig. 5 is a sectional view of a state of a manufacturing process of a semiconductor device according to an embodiment of the present invention.
Fig. 6 is a sectional view of a state of a manufacturing process of a semiconductor device according to an embodiment of the present invention.
Fig. 7 is a sectional view of a state of a manufacturing process of a semiconductor device according to an embodiment of the present invention.
Fig. 8 is a sectional view of a state of a manufacturing process of a semiconductor device according to an embodiment of the present invention.
Fig. 9 is a sectional view of a state of a manufacturing process of a semiconductor device according to an embodiment of the present invention.
Fig. 10 is a sectional view of a state of a manufacturing process of a semiconductor device according to an embodiment of the present invention.
Fig. 11 is a sectional view of a state of a manufacturing process of a semiconductor device according to an embodiment of the present invention.
Fig. 12 is a sectional view of a state of a manufacturing process of a semiconductor device according to an embodiment of the present invention.
Fig. 13 is a sectional view of a state of a manufacturing process of a semiconductor device according to an embodiment of the present invention.
Fig. 14 is a sectional view of a state of a manufacturing process of a semiconductor device according to an embodiment of the present invention.
Reference numerals:
a semiconductor device 1,
Semiconductor body 100, first main surface 101, second main surface 102, collector layer 110, blocking layer 120,
Drift layer 200, well layer 300, floating well layer 310, emitter layer 400, emitter electrode 500,
An active trench 600, a split gate electrode 610, a cross-sectional area increasing portion 611, a gate electrode 620, an insulating film 630, an interlayer insulating film 700, a contact hole 710, and a collector electrode 800.
Detailed Description
Embodiments of the present invention will be described in detail below, by way of example with reference to the accompanying drawings.
In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or element being referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present invention.
In the description of the present invention, "plurality" means two or more.
A semiconductor device 1 according to an embodiment of the present invention is described below with reference to the drawings. The semiconductor device 1 is, for example, an IGBT (insulated gate bipolar transistor Insulated Gate Bipolar Transistor). In the following description, n and p denote the conductivity type of the semiconductor, and in the present invention, the 1 st conductivity type is referred to as n-type and the 2 nd conductivity type is referred to as p-type. The conductivity type can be reversed.
As shown in fig. 2 to 14, the semiconductor device 1 according to the embodiment of the present invention includes a semiconductor body 100, an N-type drift layer 200, a P-type well layer 300, an N-type emitter layer 400, an emitter electrode 500, an active trench 600, a split gate electrode 610, a gate electrode 620, and an insulating film 630.
The semiconductor body 100 has a first main surface 101 and a main surface opposite to the first main surface 101, that is, a second main surface 102, an n-type drift layer 200 is provided between the first main surface 101 and the second main surface 102, a P-type well layer 300 is provided in the first main surface 101 closer to the first main surface 101 than the drift layer 200, an n-type emitter layer 400 is selectively provided on the first main surface 101 side of the well layer 300, an emitter electrode 500 is electrically connected to the emitter layer 400, an active trench 600 penetrates the emitter layer 400 and the well layer 300 from the first main surface 101 in the thickness direction of the semiconductor body 100 to reach the drift layer 200, a split gate electrode 610 is provided in the active trench 600 and extends from the first main surface 101 to the lower portion of the active trench 600, the split gate electrode 610 is electrically connected to the emitter electrode 500, a gate electrode 620 is provided in the active trench 600 and extends from the first main surface 101 to the upper portion of the active trench 600, a gate electrode 620 is provided only on one of opposite sides of the split gate electrode 610, a gate electrode 620 bottom surface is provided in the drift layer 200, the gate electrode 620 bottom surface is closer to the first main surface 610 than the split gate electrode bottom surface 610, and the gate electrode 610 is provided on the inner wall of the active trench 600 and the gate electrode 600 is insulated from each other by an insulating film 630.
Wherein the length of split gate electrode 610 is greater than the length of gate electrode 620.
According to the semiconductor device 1 of the embodiment of the present invention, the capacitance Cgc between the gate and the collector is reduced by providing the split gate electrode 610 electrically connected to the emitter electrode 500. In addition, since the gate electrode 620 is disposed on only one of the opposite sides of the split gate electrode 610, that is, the other of the opposite sides of the split gate electrode 610 is not disposed with the gate electrode 620, compared with the semiconductor device in which the gate electrodes are disposed on both of the opposite sides of the split gate electrode 610 in the prior art, the semiconductor device 1 of the embodiment of the present invention can reduce the trench gate density, can reduce the parasitic capacitance Cge between the gate and the emitter, on the one hand, improves the shorting capability of the semiconductor device 1, on the other hand, reduces the input capacitance Cies and the output capacitance Coes of the semiconductor device 1, increases the switching speed of the semiconductor device 1, and reduces the switching loss.
In addition, since the semiconductor device 1 of the embodiment of the present invention reduces the number and density of the gate electrodes 620 compared to the semiconductor device of the related art, it is possible to reduce the cost, save the material, and improve the production efficiency.
As such, the semiconductor device 1 according to the embodiment of the present invention reduces parasitic capacitance, reduces input capacitance and output capacitance of the semiconductor device 1, and reduces switching loss.
According to some embodiments of the present invention, as shown in fig. 2, 3 and 14, the other of the opposite sides of the split gate electrode 610 is opposite to the well layer 300 and the drift layer 200 via the insulating film 630, and the side of the gate electrode 620 facing away from the split gate electrode 610 is opposite to the emitter layer 400, the well layer 300 and the drift layer 200 via the insulating film 630. In this way, insulation and separation between the gate electrode 620 and the emitter layer 400, the well layer 300, and the drift layer 200 are achieved by the insulating film 630, and shorting between the gate electrode 620 and the emitter electrode 500 can be avoided. In addition, the emitter layer 400 is only disposed on the side of the active trench 600 having the gate electrode 620, and the emitter layer 400 is omitted on the side of the active trench 600 not having the gate electrode 620, so that the cost can be reduced and the material can be saved.
According to some embodiments of the present invention, as shown in fig. 13 and 14, the semiconductor device 1 further includes an interlayer insulating film 700, the interlayer insulating film 700 is provided on the first main surface 101, the emitter electrode 500 is formed on the upper portion of the active trench 600 through the interlayer insulating film 700, the emitter layer 400 and the well layer 300 are respectively in contact with the emitter electrode 500 through contact holes 710, which are open portions of the interlayer insulating film 700, and the emitter layer 400 and the well layer 300 are respectively electrically connected to the emitter electrode 500.
By providing the interlayer insulating film 700, the emitter electrode 500 and the semiconductor body 100 can be separated from each other, one layer of insulating protection can be formed on the semiconductor device 1, and the contact hole 710 is provided only in a specific portion of the interlayer insulating film 700, so that the emitter layer 400 and the well layer 300 can be electrically connected to the emitter electrode 500, respectively, and normal conduction of the semiconductor device 1 can be achieved.
According to some embodiments of the present invention, as shown in fig. 3, the active trenches 600 are a plurality of spaced apart, the split gate electrodes 610 are a plurality of, the split gate electrodes 610 are disposed in a plurality of active trenches 600 in a one-to-one correspondence, the gate electrodes 620 are a plurality of, the gate electrodes 620 are disposed in a plurality of active trenches 600 in a one-to-one correspondence, the gate electrodes 620 in one active trench 600 of two adjacent active trenches 600 are disposed adjacent to the split gate electrodes 610 in the other active trench 600, and the contact holes 710 are formed between the two adjacent active trenches 600.
Thus, the gate electrode 620 in the same active trench 600 is located on the same side of the split gate electrode 610, which is more convenient for manufacturing and processing, and VCEsat (collector-emitter saturation voltage) is high, which is advantageous for noise reduction.
According to some embodiments of the present invention, as shown in fig. 2 and 14, the active trenches 600 are a plurality of split gate electrodes 610, the plurality of split gate electrodes 610 are arranged in a one-to-one correspondence manner in the plurality of trenches, the plurality of gate electrodes 620 are arranged in a one-to-one correspondence manner in the plurality of trenches, the gate electrodes 620 in two adjacent active trenches 600 are arranged adjacent to each other, and the contact hole 710 is formed between two active trenches 600 in which the gate electrodes 620 are arranged adjacent to each other. That is, the well layer 300 and the emitter layer 400 between two active trenches 600 disposed adjacent to the gate electrode 620 are in contact with the emitter electrode 500 through the contact hole 710 to achieve electrical connection, wherein the emitter electrode 500 passes through the contact hole 710.
Further, the split gate electrodes 610 in the adjacent two active trenches 600 are disposed adjacent to each other, and the interlayer insulating film 700 is entirely disposed between the two active trenches 600 in which the split gate electrodes 610 are disposed adjacent to each other without forming the contact hole 710. That is, the well layer 300 and the emitter electrode 500 between two active trenches 600 disposed adjacent to the split gate electrode 610 are separated by the interlayer insulating film 700.
In this way, the number of the contact holes 710 is smaller, the processing steps can be reduced, the production efficiency can be improved, and VCEsat (collector-emitter saturation voltage) is low, that is, the on-voltage is reduced.
According to some embodiments of the present invention, as shown in fig. 14, the well layer 300 and the drift layer 200 are disposed at the opposite regions between two active trenches 600 where split gate electrodes 610 are adjacently disposed without disposing the emitter layer 400, and the well layer 300 is a floating well layer 300, that is, the floating well layer 300 is not the well layer 300 electrically connected to the emitter layer 400. With this structure, when the semiconductor device 1 is turned on, holes are hardly emitted from the emitter electrode 500, and therefore holes are more likely to accumulate in the drift layer, thereby realizing an IE effect (Injection Enhancement effect: injection enhancement effect) in the conductivity modulation, and reducing VCEsat (collector-emitter saturation voltage), that is, on-voltage drop.
According to some embodiments of the present invention, as shown in fig. 9 to 12, a cross-sectional area of a portion of the split gate electrode 610 opposite to the gate electrode 620 is smaller than a cross-sectional area of the remaining portion of the split gate electrode 610 in a direction perpendicular to a thickness direction of the semiconductor body 100. In this way, the arrangement space required for splitting the portion of the gate electrode 610 opposite to the gate electrode 620 and the entire gate electrode 620 is smaller, so that the volume of the semiconductor device 1 can be reduced, which is advantageous for the miniaturization of the semiconductor device 1.
According to some embodiments of the present invention, as shown in fig. 9-12, the cross-sectional area increase 611 of the split gate electrode 610 is located below the bottom surface of the gate electrode 620. In this way, the capacitance between the gate electrode 620 and the collector, that is, cgc, can be reduced more effectively, so as to reduce the input capacitance Cies and the output capacitance Coes effectively, thereby achieving the purpose of reducing the switching loss of the semiconductor device 1.
According to some embodiments of the present invention, as shown in fig. 2 and 3, the cross-sectional area of the split gate electrode 610 is constant along the depth of the effective trench. In this way, the relative area between the split gate electrode 610 and the gate electrode 620 is smaller, so that the capacitance between the split gate electrode 610 and the gate electrode 620 can be reduced, and the parasitic capacitance Cge is reduced, so that the input capacitance Cies and the output capacitance Coes are further reduced, and the purpose of reducing the switching loss is achieved.
According to some embodiments of the present invention, as shown in fig. 14, the semiconductor device 1 further includes a P-type collector layer 110 and an N-type stop layer 120, the collector layer 110 is disposed on the second main surface 102 side, and the stop layer 120 is disposed between the collector layer 110 and the drift layer 200. The blocking layer 120 and the drift layer 200 have the same ions, and the ion concentration of the blocking layer 120 is greater than that of the drift layer 200. Wherein the collector layer 110 may be connected to the collector electrode 800.
The manufacturing flow of the semiconductor device 1 is described below by way of example with reference to the accompanying drawings:
first, a semiconductor body 100 constituting an N-type drift layer 200 is provided, the N-type impurity concentration contained in the N-type drift layer 200 is appropriately selected according to the withstand voltage of the semiconductor device 1 to be fabricated, for example, the semiconductor device 1 of 1200V, and the resistivity of the N-type drift layer 200 may be 40 to 120 Ω·cm;
as shown in fig. 4, an active trench 600 is formed on the semiconductor substrate 100 through steps of photoresist coating, exposure, development, etching, photoresist removal, and the like;
as shown in fig. 5, the semiconductor substrate 100 is cleaned, and the cleaning is performed at H 2 And 0 (0) 2 Under the atmosphere of 900-1200 ℃, high-temperature oxidation is carried out to form an oxide layer;
as shown in fig. 6 and 7, polysilicon is filled on the oxide layer by a deposition method, then chemical mechanical polishing is used to remove polysilicon and the oxide layer on the surface of the semiconductor substrate 100, and a wafer planarization treatment is performed on the semiconductor substrate 100;
as shown in fig. 8, the oxide layer of the upper half of the active trench 600 is removed using a wet etching method;
as shown in fig. 9, an oxide layer is grown on the semiconductor substrate 100 using hot oxygen, silicon damaged by chemical mechanical polishing on the surface of the semiconductor substrate 100 is repaired or removed, and the thickness of the oxide layer at the bottom of the split gate electrode 610 is greater than that of the oxide layer of the gate electrode 620;
as shown in fig. 10, defining a region where gate polysilicon needs to be deposited by using photolithography, and performing wet etching on the region to remove silicon oxide in the region;
as shown in fig. 11, at H 2 And 0 (0) 2 A gate oxide layer is grown in the temperature range of 900-1200 ℃, the thickness of the gate oxide layer determines the threshold voltage of the semiconductor device 1, the capacitance is changed and other parameters, the thickness of the gate oxide layer can be adjusted between 500-5000 angstrom according to the application of the semiconductor device 1, and after the gate oxide layer and the polysilicon are manufactured, a chemical mechanical polishing method is used for polishing the semiconductor substrateRemoving redundant polysilicon and oxide layers on the surface of the body 100;
as shown in fig. 12, the P-type region and the N-type region to be implanted are defined by photolithography to form the P-type well layer 300 and the N-type emitter layer 400, and the implantation dose is adjusted according to the application of the semiconductor device 1, for example, the implantation dose of the P-type well layer 300 is usually between 12 times and 16 times, and the implantation dose of the N-type emitter layer 400 is usually between 14 times and Fang times;
as shown in fig. 13, an interlayer insulating film 700 is formed on the front surface of the semiconductor substrate 100 using a deposition method, then a contact hole 710 is formed on the interlayer insulating film 700 by photoresist coating, exposing, developing, etching, P-type implantation may be performed at the contact hole 710 to form an ohmic contact, the contact resistance between the emitter electrode 500 and the emitter layer 400 and the well layer 300 is reduced, the P-type implantation dose is between 12 times and 16 times, then metal sputtering is performed to form the emitter electrode 500, and then the semiconductor substrate 100 is thinned, the thinned thickness is adjusted according to the withstand voltage requirement of the semiconductor device 1, and the thickness range of the semiconductor device 1 is between 40um and 300 um;
as shown in fig. 14, an N-type impurity is implanted into the back surface of the semiconductor body 100 to form an N-type stopper layer 120, the N-type impurity concentration of the N-type stopper layer 120 is greater than the N-type impurity concentration of the N-type drift layer 200, a P-type impurity is implanted into the back surface of the semiconductor body 100 to form a P-type collector layer 110, and metal deposition is performed to form a collector electrode 800 electrically connected to the P-type collector layer 110.
Other constructions and operations of the semiconductor device 1 according to the embodiment of the present invention are known to those skilled in the art, and will not be described in detail herein.
In the description of the present specification, reference to the terms "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples.
While embodiments of the present invention have been shown and described, it will be understood by those of ordinary skill in the art that: many changes, modifications, substitutions and variations may be made to the embodiments without departing from the spirit and principles of the invention, the scope of which is defined by the claims and their equivalents.
Claims (10)
1. A semiconductor device, comprising:
a semiconductor body having a first main surface and a second main surface opposite to the first main surface;
a drift layer of a first conductivity type provided between the first main surface and the second main surface;
a well layer of a second conductivity type provided closer to the first main surface than the drift layer;
an emitter layer of a first conductivity type selectively provided on the first main surface side of the well layer;
an emitter electrode electrically connected to the emitter layer;
an active trench penetrating the emitter layer and the well layer from the first main surface in a thickness direction of the semiconductor body and reaching the drift layer;
a split gate electrode provided in the active trench and extending from the first main surface to a lower portion of the active trench, the split gate electrode being electrically connected to the emitter electrode;
a gate electrode provided within the active trench and extending from the first main surface to an upper portion of the active trench, the gate electrode being provided only on one of opposite sides of the split gate electrode, the gate electrode bottom surface being located within the drift layer, the gate electrode bottom surface being closer to the first main surface than the split gate electrode bottom surface;
and an insulating film, wherein the gate electrode, the split gate electrode and the inner wall of the active trench are arranged at intervals and insulated from each other by the insulating film.
2. The semiconductor device according to claim 1, wherein the other of opposite sides of the split gate electrode faces the well layer and the drift layer through the insulating film, and wherein a side of the gate electrode facing away from the split gate electrode faces the emitter layer, the well layer, and the drift layer through the insulating film.
3. The semiconductor device according to claim 2, further comprising:
and an interlayer insulating film provided on the first main surface, wherein the emitter electrode is formed on an upper portion of the active trench through the interlayer insulating film, and the emitter layer and the well layer are in contact with the emitter electrode via contact holes, which are open portions of the interlayer insulating film, and the emitter layer and the well layer are electrically connected to the emitter electrode, respectively.
4. The semiconductor device according to claim 3, wherein the active trenches are provided in a plurality of spaced apart;
the split gate electrodes are arranged in a plurality of active trenches in a one-to-one correspondence manner;
the plurality of gate electrodes are arranged in a plurality of active trenches in a one-to-one correspondence manner;
the gate electrode in one of the two adjacent active trenches is arranged adjacent to the split gate electrode in the other active trench;
the contact holes are formed between two adjacent active trenches.
5. The semiconductor device according to claim 3, wherein the active trenches are provided in a plurality of spaced apart;
the split gate electrodes are arranged in a plurality of grooves in a one-to-one correspondence manner;
the plurality of gate electrodes are arranged in a plurality of grooves in a one-to-one correspondence manner;
the gate electrodes in two adjacent active trenches are arranged adjacently, and/or the split gate electrodes in two adjacent active trenches are arranged adjacently;
the interlayer insulating film is integrally arranged between two active trenches adjacent to the split gate electrode without forming the contact hole;
the contact hole is formed between two active trenches adjacent to the gate electrode.
6. The semiconductor device according to claim 5, wherein the well layer and the drift layer are provided in a region opposed to each other between two active trenches where the split gate electrodes are provided adjacently, and the well layer is a floating well layer, and the emitter layer is not provided.
7. The semiconductor device according to claim 1, wherein a cross-sectional area of a portion of the split gate electrode opposite to the gate electrode in a thickness direction perpendicular to the semiconductor base is smaller than a cross-sectional area of the remaining portion of the split gate electrode.
8. The semiconductor device according to claim 7, wherein the cross-sectional area increasing portion of the split gate electrode is located below a bottom surface of the gate electrode.
9. The semiconductor device according to claim 1, wherein a cross-sectional area of the split gate electrode is constant along a depth direction of the effective trench.
10. The semiconductor device according to any one of claims 1 to 9, further comprising:
a collector layer of a second conductivity type provided on the second main surface side;
and a cutoff layer of the first conductivity type, the cutoff layer being provided between the collector layer and the drift layer, and the cutoff layer having an ion concentration greater than that of the drift layer.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310443425.9A CN116504809A (en) | 2023-04-23 | 2023-04-23 | Semiconductor device with a semiconductor device having a plurality of semiconductor chips |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310443425.9A CN116504809A (en) | 2023-04-23 | 2023-04-23 | Semiconductor device with a semiconductor device having a plurality of semiconductor chips |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105027292A (en) * | 2013-04-11 | 2015-11-04 | 富士电机株式会社 | Semiconductor device and semiconductor device manufacturing method |
| CN107799587A (en) * | 2017-10-20 | 2018-03-13 | 电子科技大学 | A kind of reverse blocking IGBT and its manufacture method |
| CN114256342A (en) * | 2020-09-24 | 2022-03-29 | 比亚迪半导体股份有限公司 | Semiconductor cellular structure, IGBT cellular structure, semiconductor structure and preparation method thereof |
-
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- 2023-04-23 CN CN202310443425.9A patent/CN116504809A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105027292A (en) * | 2013-04-11 | 2015-11-04 | 富士电机株式会社 | Semiconductor device and semiconductor device manufacturing method |
| CN107799587A (en) * | 2017-10-20 | 2018-03-13 | 电子科技大学 | A kind of reverse blocking IGBT and its manufacture method |
| CN114256342A (en) * | 2020-09-24 | 2022-03-29 | 比亚迪半导体股份有限公司 | Semiconductor cellular structure, IGBT cellular structure, semiconductor structure and preparation method thereof |
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