CN116504788A

CN116504788A - Display device and spliced display device

Info

Publication number: CN116504788A
Application number: CN202310082674.XA
Authority: CN
Inventors: 金玄俊; 黄定桓; 李启旭; 全相镇
Original assignee: Samsung Display Co Ltd
Current assignee: Samsung Display Co Ltd
Priority date: 2022-01-26
Filing date: 2023-01-18
Publication date: 2023-07-28

Abstract

The application relates to a display device and a tiled display device. The display device includes: a substrate comprising an emissive region and a non-emissive region; a pixel circuit layer over the substrate and including a transistor and a signal line in a non-emission region and a color conversion pattern in an emission region; a light emitting element over the color conversion pattern and electrically connected to the transistor; an insulating layer covering the light emitting element; and a pad over the insulating layer and electrically connected to the signal line, wherein the color conversion pattern is configured to convert a wavelength band of light incident from the light emitting element.

Description

Display device and spliced display device

Cross Reference to Related Applications

The present application claims priority and rights of korean patent application No. 10-2022-0011507 filed at the korean intellectual property office on 1 month 26 of 2022 and korean patent application No. 10-2022-0055668 filed at the korean intellectual property office on 5 month 4 of 2022, the entire disclosures of which are incorporated herein by reference.

Technical Field

The present disclosure relates generally to display devices and tiled display devices.

Background

With the increasing interest in information display and the demand for portable information media, research and commercialization of display devices have been conducted.

Disclosure of Invention

Embodiments provide a display device having improved yield and no frame.

According to an aspect of the present disclosure, there is provided a display apparatus including: a substrate comprising an emissive region and a non-emissive region; a pixel circuit layer over the substrate and including a transistor and a signal line in a non-emission region and a color conversion pattern in an emission region; a light emitting element over the color conversion pattern and electrically connected to the transistor; an insulating layer covering the light emitting element; and a pad over the insulating layer and electrically connected to the signal line, wherein the color conversion pattern is configured to convert a wavelength band of light incident from the light emitting element.

The color conversion pattern may be in an opening exposing the substrate while passing through the pixel circuit layer formed in the emission region.

The pixel circuit layer may further include a color filter between the substrate and the color conversion pattern in the emission region.

The transistor and the signal line may be separated from an emission region, wherein the light emitting element is configured to emit light through the color filter and the substrate in the emission region.

The light emitting element may comprise a flip-chip micro light emitting diode.

The display device may further comprise sub-pixels comprising light emitting elements for emitting light of the first color and configured to respectively present different individual colors.

The display device may further include a first connection electrode over the light emitting element and electrically connecting the first electrode of the light emitting element to the transistor.

The pixel circuit layer may further include a light blocking layer between the substrate and the transistor in the non-emission region.

The light blocking layer may be separated from the emission region in a plan view.

The display device may further include a fan-out line over the insulating layer, connected to the pad, and electrically connected to the signal line through a contact hole passing through the insulating layer.

The display device may further include pixels including light emitting elements, wherein a distance from an outermost pixel of the pixels to an edge of the substrate in a plan view is shorter than a distance between adjacent pixels of the pixels in the plan view.

According to another aspect of the present disclosure, there is provided a display apparatus including: a substrate comprising an emissive region and a non-emissive region; a transistor, a signal line, and a power line on a non-emission region of the substrate; a light emitting element on an emission region of the substrate; a first connection electrode over the light emitting element and electrically connecting the first electrode of the light emitting element to the transistor; a second connection electrode over the light emitting element and electrically connecting the second electrode of the light emitting element to the power line; an insulating layer over the first connection electrode and the second connection electrode; and a pad electrically connected to the signal line over the insulating layer and including at least a portion overlapping the light emitting element in a plan view.

The display device may further include a color filter between the substrate and the light emitting element in the emission region.

The transistor and the signal line may be separated from an emission region in a plan view, wherein the light emitting element is configured to emit light through the color filter and the substrate in the emission region.

The light emitting element may comprise a flip-chip micro light emitting diode.

The display device may further include a light blocking layer between the substrate and the transistor in the non-emission region.

According to still another aspect of the present disclosure, there is provided a tiled display apparatus including: a plurality of display devices; and an engaging portion between the plurality of display devices, wherein a first display device of the plurality of display devices includes: a substrate comprising an emissive region and a non-emissive region; a pixel circuit layer over the substrate and including a transistor and a signal line in a non-emission region and a color conversion pattern in an emission region; a light emitting element over the color conversion pattern and electrically connected to the transistor; an insulating layer covering the light emitting element; and a pad over the insulating layer and electrically connected to the signal line, wherein the color conversion pattern is configured to convert a wavelength band of light incident from the light emitting element.

The light emitting element may comprise a flip-chip micro light emitting diode.

The substrate may comprise glass.

The display devices may be arranged in a matrix form on M rows and N columns.

Drawings

Embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which, however, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the embodiments to those skilled in the art.

In the drawings, the size may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements or one or more intervening elements may also be present. Like numbers refer to like elements throughout.

Fig. 1 is a plan view illustrating a display device according to one or more embodiments of the present disclosure.

Fig. 2 is a plan view illustrating one or more embodiments of the display device shown in fig. 1.

Fig. 3 is a view showing an example of the pixel shown in fig. 1.

Fig. 4 is a view showing another example of the pixel shown in fig. 1.

Fig. 5 is a plan view illustrating one or more embodiments of the display device shown in fig. 1.

Fig. 6 is a view showing a connection relationship between a pixel circuit and a stage included in the display device shown in fig. 5.

Fig. 7 is a cross-sectional view schematically showing an example of a sub-pixel taken along a line I-I' shown in fig. 3.

Fig. 8 is a view schematically showing a light emitting element included in the sub-pixel shown in fig. 7.

Fig. 9 is a cross-sectional view schematically showing an example of a pixel taken along a line II-II' shown in fig. 3.

Fig. 10 and 11 are cross-sectional views schematically showing other examples of sub-pixels taken along the line I-I' shown in fig. 3.

Fig. 12 is a plan view illustrating a tiled display device including a plurality of display devices according to one or more embodiments of the present disclosure.

Fig. 13 is an enlarged layout diagram showing in detail the area AA shown in fig. 12.

Fig. 14 is a sectional view showing an example of a tiled display device taken along the line J-J' shown in fig. 13.

Fig. 15 and 16 are enlarged layout diagrams showing the region BB shown in fig. 12.

Fig. 17 is an enlarged layout diagram showing the region BB shown in fig. 12 in the display device according to the comparative embodiment.

Fig. 18 is a cross-sectional view illustrating a display device according to a comparative embodiment, taken along line N-N' shown in fig. 17.

Fig. 19 is a block diagram illustrating a display device according to one or more embodiments of the present disclosure.

Detailed Description

Aspects of some embodiments of the disclosure and methods of accomplishing the same may be understood more readily by reference to the detailed description of the embodiments and the accompanying drawings. Hereinafter, embodiments will be described in more detail with reference to the accompanying drawings. However, the described embodiments may be subject to different modifications and may be embodied in various forms and should not be construed as limited to only the embodiments set forth herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey aspects of the disclosure to those skilled in the art, and it should be understood that the present disclosure encompasses all modifications, equivalents, and alternatives falling within the spirit and technical scope of the present disclosure. Thus, processes, elements, and techniques not necessary for a person of ordinary skill in the art to fully understand aspects of the present disclosure may not be described.

Unless otherwise indicated, like reference numerals, or combinations thereof denote like elements throughout the drawings and the written description, and thus, the description thereof will not be repeated. Moreover, portions that are not relevant or relevant to the description may not be shown to make the description clear.

In the drawings, the relative sizes of elements, layers and regions may be exaggerated for clarity. Furthermore, the use of cross-hatching and/or shading in the drawings is often provided to clarify the boundaries between adjacent elements. Thus, unless specified, the presence or absence of cross-hatching or shading does not convey or represent any preference or requirement for a particular material, material property, dimension, proportion, commonality between illustrated elements, and/or any other characteristic, attribute, property, or the like of an element.

Various embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of embodiments and/or intermediate structures. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. In addition, the specific structural or functional descriptions disclosed herein are merely illustrative for purposes of describing embodiments according to the concepts of the disclosure. Accordingly, the embodiments disclosed herein should not be construed as limited to the particular illustrated shapes of regions but are to include deviations in shapes that result, for example, from manufacturing.

For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or gradients of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, an embedded region formed by implantation may result in some implantation in the region between the embedded region and the surface through which implantation occurs.

Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to be limiting. Furthermore, as will be appreciated by those skilled in the art, the described embodiments may be modified in various different ways without departing from the scope of the present disclosure.

In the detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the various embodiments. It may be evident, however, that the various embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring the various embodiments.

Spatially relative terms, such as "below," "beneath," "lower," "below," "above," "upper," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "beneath" can encompass both an orientation of above and below. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Similarly, when a first portion is described as being disposed "on" a second portion, this means that the first portion is disposed at an upper or lower side of the second portion, and is not limited to the upper side of the second portion based on the direction of gravity.

Further, in this specification, the phrase "on a plane" or "plan view" refers to the object portion viewed from the top, and the phrase "on a cross section" refers to a cross section formed by vertically cutting the object portion from the side.

It will be understood that when an element, layer, region or component is referred to as being "on," "connected to" or "coupled to" another element, layer, region or component, it can be directly on, connected to or coupled to the other element, layer, region or component, or be indirectly on, connected to or coupled to the other element, layer, region or component, such that one or more intervening elements, layers, regions or components may be present. Furthermore, this may connote a direct coupling or direct connection or an indirect coupling or indirect connection, an integral coupling or integral connection or a non-integral coupling or non-integral connection. For example, when a layer, region, or component is referred to as being "electrically connected" or "coupled" to another layer, region, or component, it can be directly electrically connected or directly coupled to the other layer, region, or component, or intervening layers, regions, or components may be present. However, "directly connected/directly coupled" or "directly on …" means that one component is directly connected or directly coupled to or directly on another component without intervening components. Further, in this specification, when a part of a layer, a film, a region, a plate, or the like is formed on another part, the forming direction is not limited to the upward direction, but includes forming the part on a side surface or in a downward direction. In contrast, when a portion of a layer, film, region, plate, or the like is formed "under" another portion, this includes not only the case where the portion is "directly under" the other portion but also the case where a further portion is between the portion and the other portion. Meanwhile, other expressions describing the relationship between components (such as "between …", "directly between …" or "adjacent to" and "directly adjacent to") may be similarly interpreted. Furthermore, it will be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

For purposes of this disclosure, a statement such as "at least one of …" when located after an element of a list modifies an element of the entire list without modifying individual elements in the list. For example, "at least one of X, Y and Z" and "at least one selected from the group consisting of X, Y and Z" may be interpreted as any combination of two or more of X only, Y only, Z, X, Y only, and Z (such as XYZ, XYY, YZ and ZZ, for example), or any variation thereof. Similarly, expressions such as "at least one of a and B" may include A, B or a and B. As used herein, "or" generally means "and/or" and the term "and/or" includes any and all combinations of one or more of the associated listed items. For example, expressions such as "a and/or B" may include A, B or a and B.

It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the scope of the present disclosure. Describing an element as a "first" element may not require or imply that a second or other element is present. The terms "first," "second," and the like may also be used herein to distinguish between different classes or groups of elements. For simplicity, the terms "first," "second," and the like may refer to "a first category (or a first group)", "a second category (or a second group)", and the like, respectively.

In an example, the DR1 axis, DR2 axis, and/or DR3 axis are not limited to three axes of a rectangular coordinate system, and may be interpreted in a broader sense. For example, the DR1 axis, DR2 axis, and DR3 axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction and/or the third direction.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," "including," "having," "includes" and "including" when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

As used herein, the terms "substantially," "about," "approximately," and similar terms are used as approximation terms and not as degree terms, and are intended to leave a margin for inherent deviations in measured or calculated values that will be recognized by one of ordinary skill in the art. As used herein, "about" or "approximately" includes the values as well as averages within acceptable deviation limits of the particular values as determined by one of ordinary skill in the art in view of the measurement in question and the error associated with the particular amount of measurement (i.e., limitations of the measurement system). For example, "about" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. In addition, "may" as used in describing embodiments of the present disclosure means "one or more embodiments of the present disclosure.

Furthermore, any numerical range disclosed and/or recited herein is intended to include all sub-ranges subsumed with the same numerical precision within that range. For example, a range of "1.0 to 10.0" is intended to include all subranges between (and including 1.0 and 10.0) the minimum value of 1.0 and the maximum value of 10.0, i.e., having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as, for example, 2.4 to 7.6. Any maximum numerical limitation recited herein is intended to include all lower numerical limitations subsumed therein, and any minimum numerical limitation recited herein is intended to include all higher numerical limitations subsumed therein. Accordingly, applicants reserve the right to modify this specification (including the claims) to expressly state any sub-ranges subsumed within the ranges expressly stated herein.

Some embodiments are depicted in the drawings as related to functional blocks, units, and/or modules. Those skilled in the art will appreciate that such blocks, units, and/or modules are physically implemented by logic circuits, individual components, microprocessors, hard-wired circuits, storage elements, wiring connections, and other electronic circuits. This may be formed using semiconductor-based fabrication techniques or other fabrication techniques. Blocks, units, and/or modules implemented by a microprocessor or other similar hardware may be programmed and controlled using software to perform the various functions discussed herein, and may optionally be driven by firmware and/or software. Furthermore, each block, unit, and/or module may be implemented by dedicated hardware or a combination of dedicated hardware performing some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) performing functions other than the functions of the dedicated hardware. Furthermore, in some implementations, blocks, units, and/or modules may be physically separated into two or more interacting and separate blocks, units, and/or modules without departing from the scope of the disclosure. Furthermore, in some implementations, blocks, units, and/or modules may be physically combined into more complex blocks, units, and/or modules without departing from the scope of the disclosure.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or the present specification and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Fig. 1 is a plan view illustrating a display device according to one or more embodiments of the present disclosure. Fig. 2 is a plan view illustrating one or more embodiments of the display device shown in fig. 1. In fig. 2, a display device 10 comprising a source driving circuit SIC is shown. Fig. 3 is a view showing an example of the pixel shown in fig. 1. Fig. 4 is a view showing another example of the pixel shown in fig. 1.

First, referring to fig. 1, a display device 10 (or display panel) is a device for displaying an image (e.g., a moving image or a still image), and may be used as a display screen of a portable electronic device such as a mobile phone, a smart phone, a tablet Personal Computer (PC), a smart watch, a watch phone, a mobile communication terminal, an electronic notebook, an electronic book, a Portable Multimedia Player (PMP), a navigation system, an Ultra Mobile PC (UMPC), and various products such as a television, a notebook computer, a computer display, a digital billboard, and an internet of things (IoT) device.

The display device 10 may be formed in a rectangular planar shape having a long side in the first direction DR1 and a short side in the second direction DR2 intersecting the first direction DR 1. The corners where the long sides in the first direction DR1 and the short sides in the second direction DR2 intersect each other may be formed at right angles or rounded to have a curvature (e.g., a predetermined curvature). The planar shape of the display device 10 is not limited to a quadrangular shape, and may be formed in another polygonal shape, a circular shape, or an elliptical shape. The display device 10 may be formed flat, but the present disclosure is not limited thereto. For example, the display apparatus 10 may include a curved portion formed at the left/right ends and have a constant curvature or a varying curvature. Further, the display device 10 may be formed to be flexible, bendable, foldable, or rollable.

In order to display an image, the display device 10 may further include pixels PX, scan lines extending in the first direction DR1, and data lines extending in the second direction DR 2. The pixels PX may be arranged in a matrix form in the first direction DR1 and the second direction DR 2.

Referring to fig. 2, the source driving circuit SIC for supplying a data signal (or a data voltage) to the pixels PX through the data lines may be located at the uppermost portion in the third direction DR 3. For example, the source driving circuit SIC may be mounted on a flexible film FPCB, and may be coupled to an upper surface of a display panel (e.g., a panel in which pixels PX and data lines are formed) through the flexible film FPCB. The display device 10 may display an image in a direction opposite to the third direction DR 3. The arrangement of the source driving circuit SIC will be described later with reference to fig. 7 and 16.

As shown in fig. 3 and 4, each of the pixels PX may include a plurality of sub-pixels SPX1 to SPX3. Although a case in which each of the pixels PX includes three sub-pixels SPX1 to SPX3 (e.g., a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX 3) is depicted in fig. 3 and 4, the present disclosure is not limited thereto.

Each of the first, second, and third sub-pixels SPX1, SPX2, and SPX3 may be connected to at least one of the data lines and at least one of the scan lines.

Each of the first, second, and third sub-pixels SPX1, SPX2, and SPX3 may have a rectangular, square, or diamond-shaped planar shape. For example, as shown in fig. 3, each of the first, second, and third sub-pixels SPX1, SPX2, and SPX3 may have a planar shape of a rectangle having a short side in the first direction DR1 and a long side in the second direction DR 2. Alternatively, as shown in fig. 4, each of the first, second, and third sub-pixels SPX1, SPX2, and SPX3 may have a square or diamond-shaped planar shape including sides having the same length in the first and second directions DR1 and DR 2.

As shown in fig. 3, the first, second, and third sub-pixels SPX1, SPX2, and SPX3 may be arranged in the first direction DR 1. Alternatively, any one of the second and third sub-pixels SPX2 and SPX3 and the first sub-pixel SPX1 may be arranged in the first direction DR1, and the other one of the second and third sub-pixels SPX2 and SPX3 and the first sub-pixel SPX1 may be arranged in the second direction DR 2. For example, as shown in fig. 4, the first and second sub-pixels SPX1 and SPX2 may be arranged in the first direction DR1, and the first and third sub-pixels SPX1 and SPX3 may be arranged in the second direction DR 2.

Alternatively, any one of the first and third sub-pixels SPX1 and SPX3 may be arranged in the first direction DR1 with the second sub-pixel SPX2, and the other one of the first and third sub-pixels SPX1 and SPX3 may be arranged in the second direction DR2 with the second sub-pixel SPX 2. Alternatively, any one of the first and second sub-pixels SPX1 and SPX2 may be arranged in the first direction DR1 with the third sub-pixel SPX3, and the other one of the first and second sub-pixels SPX1 and SPX2 may be arranged in the second direction DR2 with the third sub-pixel SPX 3.

The first subpixel SPX1 may emit first light, the second subpixel SPX2 may emit second light, and the third subpixel SPX3 may emit third light. The first light may be light of a red wavelength band, the second light may be light of a green wavelength band, and the third light may be light of a blue wavelength band. The red wavelength band may be a wavelength band of about 600nm to about 750nm, the green wavelength band may be a wavelength band of about 480nm to about 560nm, and the blue wavelength band may be a wavelength band of about 370nm to about 460 nm. However, the present disclosure is not limited thereto.

Each of the first, second, and third sub-pixels SPX1, SPX2, and SPX3 is a light emitting element for emitting light, and may include an inorganic light emitting element having an inorganic semiconductor. For example, the inorganic light emitting element may be a flip chip type Light Emitting Diode (LED), but the present disclosure is not limited thereto.

As shown in fig. 3 and 4, the area of the first subpixel SPX1, the area of the second subpixel SPX2, and the area of the third subpixel SPX3 may be substantially the same, but the present disclosure is not limited thereto. At least one of the area of the first subpixel SPX1, the area of the second subpixel SPX2, and the area of the third subpixel SPX3 may be different from the area of the other subpixel. Alternatively, two of the area of the first subpixel SPX1, the area of the second subpixel SPX2, and the area of the third subpixel SPX3 may be substantially the same, and the area of the other may be different from the areas of the two. Alternatively, the area of the first subpixel SPX1, the area of the second subpixel SPX2, and the area of the third subpixel SPX3 may be different from each other.

Fig. 5 is a plan view illustrating one or more embodiments of the display device shown in fig. 1. Fig. 6 is a view showing a connection relationship between a pixel circuit and a stage included in the display device shown in fig. 5. The plurality of stages may constitute at least one gate driver (or scan driver).

Referring to fig. 1 to 5, a display device 10 (or a display panel) may include pixels PX, and the pixels PX may include a first subpixel SPX1, a second subpixel SPX2, and a third subpixel SPX3.

The first subpixel SPX1 may include a first light emitting element LD1 and a first pixel circuit PC1, and the first pixel circuit PC1 may supply a driving current to the first light emitting element LD1. The first pixel circuit PC1 may be located in the second direction DR2 with respect to the first light emitting element LD1, and may be electrically connected to the first light emitting element LD1. The second subpixel SPX2 may include a second light emitting element LD2 and a second pixel circuit PC2, and the second pixel circuit PC2 may supply a driving current to the second light emitting element LD2. The second pixel circuit PC2 may be located in the second direction DR2 with respect to the second light emitting element LD2, and may be electrically connected to the second light emitting element LD2. The third subpixel SPX3 may include a third light emitting element LD3 and a third pixel circuit PC3, and the third pixel circuit PC3 may supply a driving current to the third light emitting element LD3. The third pixel circuit PC3 may be located in the second direction DR2 with respect to the third light emitting element LD3, and may be electrically connected to the third light emitting element LD3. Each of the pixel circuits PC1 to PC3 may include at least one transistor (see "TFT" shown in fig. 7) and at least one capacitor.

In some embodiments, each of the sub-pixels SPX1 to SPX3 may include two light emitting elements. For example, each of the sub-pixels SPX1 to SPX3 may include a main light emitting element and a repair light emitting element, but the disclosure is not limited thereto. In another example, each of the sub-pixels SPX1 to SPX3 may include three or more light emitting elements.

The pixels PX may be arranged to have a uniform pixel pitch with respect to the light emitting elements LD1 to LD 3. The light emitting elements LD1 to LD3 may be arranged along a plurality of pixel rows. For example, the light emitting elements LD1 to LD3 may be arranged along the kth pixel row prox to the (k+5) th pixel row prox+5 (k is a positive integer). The pixel circuits PC1 to PC3 may be arranged along a plurality of circuit rows. The pixel circuits PC1 to PC3 may be arranged along the kth circuit row CROWk to the (k+5) th circuit row crowk+5.

The kth pixel row prox may be adjacent to the kth circuit row CROWk in a direction opposite to the second direction DR2, and the (k+1) th pixel row prox+1 may be adjacent to the (k+1) th circuit row crowk+1 in the second direction DR 2. The kth circuit row CROWk and the (k+1) th circuit row crowk+1 may be located between the kth pixel row prox and the (k+1) th pixel row prox+1. Similarly, the (k+2) th pixel row prox+2 may be adjacent to the (k+2) th circuit row crowk+2 in a direction opposite to the second direction DR2, and the (k+3) th pixel row prox+3 may be adjacent to the (k+3) th circuit row crowk+3 in the second direction DR 2. The (k+2) th and (k+3) th circuit rows crowk+2 and crowk+3 may be located between the (k+2) th and (k+3) th pixel rows prox+2 and prox+3. Similarly, the (k+4) th pixel row prox+4 may be adjacent to the (k+4) th circuit row crowk+4 in a direction opposite to the second direction DR2, and the (k+5) th pixel row prox+5 may be adjacent to the (k+5) th circuit row crowk+5 in the second direction DR 2. The (k+4) th circuit row crowk+4 and the (k+5) th circuit row crowk+5 may be located between the (k+4) th pixel row prox+4 and the (k+5) th pixel row prox+5.

As shown in fig. 6, the kth stage STGk may be located at an upper side of the kth circuit row CROWk and the kth pixel row prox. The kth stage STGk may supply gate signals to the kth gate lines GLk of the pixel circuits PC1 to PC3 connected to the kth circuit row CROWk. The kth stage STGk may be connected to the kth gate line GLk through a connection line CL. The kth stage STGk may be connected to the kth gate line GLk through a first connection line CL1 extending in the first direction DR1 and a second connection line CL2 extending in the second direction DR 2.

The (k+1) th stage stgk+1 and the (k+2) th stage stgk+2 may be located between the (k+1) th pixel row prox+1 and the (k+2) th pixel row prox+2. The (k+1) -th stage stgk+1 may be located at the lower side of the (k+1) -th circuit row crowk+1 and the (k+1) -th pixel row promwk+1. The (k+1) -th stage stgk+1 may supply a gate signal to the (k+1) -th gate line glk+1 of the pixel circuit PC connected to the (k+1) -th circuit row crowk+1. The (k+1) -th stage stgk+1 may be connected to the (k+1) -th gate line glk+1 through a connection line CL.

The (k+2) -th stage stgk+2 may be located at an upper side of the (k+2) -th circuit row crowk+2 and the (k+2) -th pixel row prox+2. The (k+2) -th stage stgk+2 may supply a gate signal to the (k+2) -th gate line glk+2 of the pixel circuit PC connected to the (k+2) -th circuit row crowk+2. The (k+2) -th stage stgk+2 may be connected to the (k+2) -th gate line glk+2 through a connection line CL.

The (k+3) th stage stgk+3 and the (k+4) th stage stgk+4 may be located between the (k+3) th pixel row prox+3 and the (k+4) th pixel row prox+4. The (k+3) -th stage stgk+3 may be located at the lower side of the (k+3) -th circuit row crowk+3 and the (k+3) -th pixel row prox+3. The (k+3) -th stage stgk+3 may supply a gate signal to the (k+3) -th gate line glk+3 of the pixel circuit PC connected to the (k+3) -th circuit row crowk+3. The (k+3) -th stage stgk+3 may be connected to the (k+3) -th gate line glk+3 through a connection line CL.

The (k+4) -th stage stgk+4 may be located at an upper side of the (k+4) -th circuit row crowk+4 and the (k+4) -th pixel row prox+4. The (k+4) -th stage stgk+4 may supply a gate signal to the (k+4) -th gate line glk+4 of the pixel circuit PC connected to the (k+4) -th circuit row crowk+4. The (k+4) -th stage stgk+4 may be connected to the (k+4) -th gate line glk+4 through a connection line CL.

The (k+5) -th stage stgk+5 may be located at the lower side of the (k+5) -th circuit row crowk+5 and the (k+5) -th pixel row prox+5. The (k+5) -th stage stgk+5 may supply a gate signal to the (k+5) -th gate line glk+5 of the pixel circuit PC connected to the (k+5) -th circuit row crowk+5. The (k+5) -th stage stgk+5 may be connected to the (k+5) -th gate line glk+5 through a connection line CL.

The data lines DL may include data lines DL1 to DL3. The first data line DL1 may supply data signals to a plurality of first pixel circuits PC1 located on the same column. The second data line DL2 may supply a data signal to the plurality of second pixel circuits PC2 located on the same column. The third data line DL3 may supply a data signal to the plurality of third pixel circuits PC3 located on the same column.

Fig. 7 is a cross-sectional view schematically showing an example of a sub-pixel taken along a line I-I' shown in fig. 3. The sub-pixels SPX1 to SPX3 shown in fig. 3 are substantially identical or similar to each other. Accordingly, the sub-pixels SPX1 to SPX3 shown in fig. 3 are commonly designated as sub-pixels SPX. Hereinafter, the sub-pixel SPX will be described.

Referring to fig. 1 to 7, the SUB-pixel SPX (or the display device 10 (see fig. 1)) may include a substrate SUB, a buffer layer BF, a light blocking layer BM (or a light blocking pattern), an active layer ACT (or an active pattern), a first gate insulating layer GI1, a first gate layer GAT1, a second gate insulating layer GI2, a second gate layer GAT2, an interlayer insulating layer ILD, a first source metal layer SD1, a first VIA layer VIA1 (or a first insulating layer), a second source metal layer SD2, a second VIA layer VIA2 (or a second insulating layer), a third source metal layer SD3, a third VIA layer VIA3 (or a third insulating layer), a fourth source metal layer SD4, a fourth VIA layer VIA4 (or a fourth insulating layer), and a protective layer PVX. In addition, the sub-pixel SPX (or the display device 10 (see fig. 1)) may include a light conversion pattern LCP and a light emitting element LD. For convenience of description, a component from the buffer layer BF on which the thin film transistor TFT is formed to the third source metal layer SD3 may be referred to as a pixel circuit layer.

In one or more embodiments of the present disclosure, the term "formed and/or disposed in the same layer" may mean formed in the same process, and the term "formed and/or disposed in different layers" may mean formed in different processes, so long as no other description is provided.

The substrate SUB may be a base substrate or a base member for supporting the display device 10. The substrate SUB may be a rigid substrate made of glass. Alternatively, the substrate SUB may be a flexible substrate to be bendable, foldable, rollable, or the like. The substrate SUB may include an insulating material including a polymer resin such as Polyimide (PI).

With respect to one SUB-pixel SPX, the substrate SUB may include an emission area EA and a non-emission area NEA. The emission area EA may be an area through which light is transmitted, and the non-emission area NEA may be an area in which transmission of light is blocked. In a plane, the light conversion pattern LCP and the light emitting element LD may be disposed in the emission area EA, and the thin film transistor TFT (or transistor) and the signal line (e.g., the data line DL and the power line VSL) may be located in the non-emission area NEA. Further, driving circuits (e.g., signal splitters, electrostatic discharge protection circuits, etc.) including the stages STGk to stgk+5 described with reference to fig. 5 may be located in the non-emission area NEA. The thin film transistor TFT and the signal line are not located in the emission area EA.

The light blocking layer BM may be located on one surface of the substrate SUB. The light blocking layer BM may be substantially located in the non-emission region NEA and may define the emission region EA. The light blocking layer BM may be located between the substrate SUB and the thin film transistor TFT. The light blocking layer BM may include/define an opening corresponding to the emission area EA. In other words, the light blocking layer BM may not substantially overlap with the emission area EA in a plane. The light blocking layer BM may include a light blocking material. In an example, the light blocking layer BM may be a black matrix. The light blocking layer BM may reduce or prevent light leakage defect in which light (or light beam) leaks between the sub-pixel SPX and the sub-pixel SPX adjacent thereto, and may reduce or prevent color mixing of light.

The buffer layer BF may be located on the light blocking layer BM. The buffer layer BF may be a layer for reducing or preventing air or moisture penetration. The buffer layer BF may be configured with a plurality of inorganic layers alternately stacked. For example, the buffer layer BF may be formed in a multilayer in which one or more inorganic layers of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked. In some embodiments, the buffer layer BF may be omitted. The buffer layer BF may include/define an opening corresponding to the emission area EA.

In one or more embodiments, the lower electrode layer BML (or lower electrode) may be located on the light blocking layer BM. The lower electrode layer BML may overlap the active layer ACT (or a channel of the thin film transistor TFT) in the third direction DR 3. The lower electrode layer BML may block light irradiated onto the active layer ACT in the third direction DR3, thereby reducing or minimizing a characteristic change of the thin film transistor TFT caused by the light. The lower electrode layer BML may be formed as a single layer or a plurality of layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or any alloy thereof.

The active layer ACT may be located on the buffer layer BF. The active layer ACT may include a silicon semiconductor such as polysilicon, monocrystalline silicon, low-temperature polysilicon, and amorphous silicon, or an oxide semiconductor.

The active layer ACT may include a channel, a source region, and a drain region of the thin film transistor TFT. The channel of the thin film transistor TFT may be a region overlapping with the gate electrode GE of the thin film transistor TFT in the third direction DR3, which is the thickness direction of the substrate SUB. The source region of the thin film transistor TFT may be located at one side of the channel and the drain region of the thin film transistor TFT may be located at the other side of the channel. The source and drain regions of the thin film transistor TFT may be regions that do not overlap the gate electrode GE in the third direction DR 3. The source and drain regions of the thin film transistor TFT may be regions in which ions are doped to have conductivity in a silicon semiconductor or an oxide semiconductor.

The first gate insulating layer GI1 may be positioned above the active layer ACT. The first gate insulating layer GI1 may be formed as an inorganic layer (e.g., a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer), but the present disclosure is not limited thereto. The first gate insulating layer GI1 may include/define an opening corresponding to the emission area EA.

The first gate layer GAT1 may be located on the first gate insulating layer GI 1. The first gate layer GAT1 may include a gate electrode GE of the thin film transistor TFT and a first capacitor electrode CE1. The first capacitor electrode CE1 may be integrally formed with the gate electrode GE, but the disclosure is not limited thereto. For example, the first capacitor electrode CE1 may be positioned to be spaced apart from the gate electrode GE. The first gate layer GAT1 may be formed as a single layer or a plurality of layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or any alloy thereof.

The second gate insulating layer GI2 may be located on the first gate layer GAT 1. The second gate insulating layer GI2 may be formed as an inorganic layer (e.g., a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer), but the present disclosure is not limited thereto. The second gate insulating layer GI2 may include/define an opening corresponding to the emission area EA.

The second gate layer GAT2 may be located on the second gate insulating layer GI 2. The second gate layer GAT2 may include a second capacitor electrode CE2. The second capacitor electrode CE2 together with the first capacitor electrode CE1 may constitute a capacitor (e.g., a storage capacitor for storing a data signal of the sub-pixel SPX or a voltage corresponding thereto).

The second gate layer GAT2 may be formed as a single layer or a plurality of layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or any alloy thereof.

An interlayer insulating layer ILD may be positioned on the second gate layer GAT 2. The interlayer insulating layer ILD may be formed as an inorganic layer (e.g., a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer), but the present disclosure is not limited thereto. The interlayer insulating layer ILD may include/define an opening corresponding to the emission area EA.

The first source metal layer SD1 may be located on the interlayer insulating layer ILD. The first source metal layer SD1 may include a first transistor electrode SE, a second transistor electrode DE, a bridge pattern BRP0, and a data line DL. The first transistor electrode SE may be connected to a source region of the active layer ACT (e.g., a source region of an active pattern of a thin film transistor TFT) through a contact hole passing through the first gate insulating layer GI1, the interlayer insulating layer ILD, and the second gate insulating layer GI 2. Similarly, the second transistor electrode DE may be connected to a drain region of the active layer ACT (e.g., a drain region of an active pattern of the thin film transistor TFT) through a contact hole passing through the first gate insulating layer GI1, the interlayer insulating layer ILD, and the second gate insulating layer GI 2. The bridge pattern BRP0 may be connected to the gate electrode GE through a contact hole passing through the interlayer insulating layer ILD and the second gate insulating layer GI 2. In some embodiments, the bridge pattern BRP0 may be omitted. The data line DL may be the data line DL described with reference to fig. 6.

The first source metal layer SD1 may be formed as a single layer or a plurality of layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or any alloy thereof.

The first VIA layer VIA1 may be located above the first source metal layer SD 1. The first VIA layer VIA1 may be a first planarization layer for planarizing a step difference caused by the active layer ACT, the first gate layer GAT1, the second gate layer GAT2, and the first source metal layer SD1, but the present disclosure is not limited thereto. For example, the first VIA layer VIA1 may be formed as an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin. In some embodiments, the first VIA layer VIA1 may be formed as an inorganic layer (e.g., a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer). In another example, the first VIA layer VIA1 may be formed as a multilayer including an organic layer and an inorganic layer sequentially stacked. The first VIA layer VIA1 may include/define an opening corresponding to the emission area EA.

The second source metal layer SD2 may be located on the first VIA layer VIA 1. The second source metal layer SD2 may include a first bridge pattern BRP1, a second bridge pattern BRP2, and a third bridge pattern BRP3. The first bridge pattern BRP1 may be connected to the second transistor electrode DE through a contact hole passing through the first VIA layer VIA 1. Similarly, the second bridge pattern BRP2 may be connected to the data line DL through a contact hole passing through the first VIA layer VIA 1. The third bridge pattern BRP3 may be connected to the first transistor electrode SE through a contact hole passing through the first VIA layer VIA 1.

The second source metal layer SD2 may be formed as a single layer or a plurality of layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or any alloy thereof.

The second VIA layer VIA2 may be located above the second source metal layer SD2. The second VIA layer VIA2 may be a second planarization layer for planarizing a step difference caused by the second source metal layer SD2, but the disclosure is not limited thereto. Similar to the first VIA layer VIA1, the second VIA layer VIA2 may be formed as a single layer or multiple layers including an organic layer and/or an inorganic layer. The second VIA layer VIA2 may include/define an opening corresponding to the emission area EA.

In some embodiments, the second VIA layer VIA2 and the second source metal layer SD2 may be omitted.

The third source metal layer SD3 may be formed on the second VIA layer VIA 2. The third source metal layer SD3 may include a first bridge electrode BRE1, a second bridge electrode BRE2, and a power line VSL. The first bridge electrode BRE1 may be connected to the first bridge pattern BRP1 through a contact hole passing through the second VIA layer VIA2, and the second bridge electrode BRE2 may be connected to the second bridge pattern BRP2 through a contact hole passing through the second VIA layer VIA 2. A power voltage (e.g., a low power voltage or a driving power supply) suitable for driving the sub-pixels SPX may be applied to the power line VSL.

The third source metal layer SD3 may be formed as a single layer or a plurality of layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or any alloy thereof.

In an embodiment, in the emission region EA, an opening OP exposing the substrate SUB while passing through the buffer layer BF, the first gate insulating layer GI1, the second gate insulating layer GI2, the interlayer insulating layer ILD, the first VIA layer VIA1, and the second VIA layer VIA2 (e.g., pixel circuit layers from the buffer layer BF to the second VIA layer VIA 2) may be formed. For example, the opening of the buffer layer BF, the opening of the first gate insulating layer GI1, the opening of the second gate insulating layer GI2, the opening of the interlayer insulating layer ILD, the opening of the first VIA layer VIA1, and the opening of the second VIA layer VIA2 may overlap with each other, thereby forming the opening OP. However, the present disclosure is not limited thereto. For example, the opening OP may be formed by commonly etching the buffer layer BF, the first gate insulating layer GI1, the second gate insulating layer GI2, the interlayer insulating layer ILD, the first VIA layer VIA1, and the second VIA layer VIA 2. The method of forming the opening OP is not particularly limited.

The light conversion pattern LCP may be located or disposed in the opening OP. For example, after the third source metal layer SD3 is formed, a light conversion pattern LCP may be formed in the opening OP. The light conversion pattern LCP may include color conversion particles QD and/or color filters CF. For example, the light conversion pattern LCP may include a color filter CF, and may further include color conversion particles QD. However, the present disclosure is not limited thereto. In another example, the light conversion pattern LCP may include only color conversion particles QD.

The light conversion pattern LCP may change or convert the wavelength (or color) of light emitted from the light emitting element LD by using the color conversion particles QD (or quantum dots), and may allow light of a corresponding wavelength (or a corresponding color) to be selectively transmitted therethrough by using the color filter CF. Light may be emitted from the light emitting element LD (e.g., in the opposite direction to the third direction DR 3) to the outside through the light conversion pattern LCP and the substrate SUB. That is, the sub-pixel SPX (and the display apparatus 10 including the sub-pixel SPX (see fig. 1)) may have a bottom emission structure.

Meanwhile, although a case where the height of the upper surface of the light conversion pattern LCP and the height of the upper surface of the second VIA layer VIA2 are the same with respect to the substrate SUB is illustrated in fig. 7, the present disclosure is not limited thereto. For example, the height of the upper surface of the light conversion pattern LCP may be lower than the height of the upper surface of the second VIA layer VIA 2. In another example, the height of the upper surface of the light conversion pattern LCP may be higher than the height of the upper surface of the second VIA layer VIA 2. Further, although a case where the upper surface of the light conversion pattern LCP is flat is illustrated in fig. 7, the present disclosure is not limited thereto. For example, the upper surface of the light conversion pattern LCP may have a cross-sectional shape recessed toward the substrate SUB. The thickness and the sectional shape of the light-converting pattern LCP are not particularly limited in the range where the light-converting pattern LCP is located within the opening OP.

In the emission area EA, the light emitting element LD may be located on the light conversion pattern LCP. The light emitting element LD is depicted as a flip chip micro LED in which the first contact electrode ELT1 and the second contact electrode ELT2 are positioned facing the third direction DR 3. The light emitting element LD may be formed of an inorganic material such as GaN. Each of the length of the light emitting element LD in the second direction DR2 (and the length of the light emitting element LD in the first direction DR1 (see fig. 3)) and the length of the light emitting element LD in the third direction DR3 may be several tens to several hundreds of micrometers. For example, each of the length of the light emitting element LD in the second direction DR2 (and the length of the light emitting element LD in the first direction DR 1) and the length of the light emitting element LD in the third direction DR3 may be about 100 μm or less. The light emitting element LD will be described later with reference to fig. 8. Each of the light emitting elements LD1 to LD3 shown in fig. 5 may correspond to the light emitting element LD, and may be substantially identical to each other.

The light emitting element LD may be formed by growing on a semiconductor substrate such as a silicon wafer. The light emitting element LD may be transferred from a silicon wafer onto the light conversion pattern LCP. Alternatively, the light emitting element LD may be transferred onto the light conversion pattern LCP by an electrostatic process using an electrostatic head or a stamp process using a polymer material having elasticity (such as PDMS or silicone) as a transfer substrate.

The third VIA layer VIA3 may be located over the third source metal layer SD3 and the light emitting element LD. The third VIA layer VIA3 may be a third planarization layer for planarizing a step difference caused by the third source metal layer SD3 and the light emitting element LD, but the disclosure is not limited thereto. Similar to the first VIA layer VIA1, the third VIA layer VIA3 may be formed as a single layer or multiple layers including an organic layer and/or an inorganic layer.

Although a case where the light emitting element LD is located in the opening of the third VIA layer VIA3 is shown in fig. 7, the present disclosure is not limited thereto. For example, the height of the upper surface of the third VIA layer VIA3 may be higher than the height of the upper surface of the light emitting element LD with respect to the substrate SUB, and the third VIA layer VIA3 may substantially cover the light emitting element LD.

The connection electrode layer ITOL may be located on the third VIA layer VIA 3. The connection electrode layer ITOL may include a first connection electrode CNE1 (or a first pixel electrode) and a second connection electrode CNE2 (or a second pixel electrode). The first connection electrode CNE1 may be designated as an anode electrode, and the second connection electrode CNE2 may be designated as a cathode electrode. However, the present disclosure is not limited thereto.

The first connection electrode CNE1 may be connected to the first bridge electrode BRE1 through a contact hole passing through the third VIA layer VIA3, and may be connected to the first contact electrode ELT1 exposed by the third VIA layer VIA 3. The first connection electrode CNE1 may electrically connect the first contact electrode ELT1 of the light emitting element LD and the thin film transistor TFT to each other. Accordingly, a pixel voltage or an anode voltage controlled by the thin film transistor TFT may be applied to the light emitting element LD.

Similarly, the second connection electrode CNE2 may be connected to the electric power line VSL through a contact hole passing through the third VIA layer VIA3, and may be connected to the second contact electrode ELT2 exposed by the third VIA layer VIA 3. The second connection electrode CNE2 may electrically connect the second contact electrode ELT2 of the light emitting element LD and the power line VSL to each other. Accordingly, the power voltage of the power line VSL can be applied to the light emitting element LD.

The connection electrode layer ITOL may include a transparent conductive material (TCO), such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO), but the present disclosure is not limited thereto. For example, the connection electrode layer ITOL may include a metal material having high reflectivity, such as a stacked structure of aluminum and titanium (Ti/Al/Ti), a stacked structure of aluminum and ITO (ITO/Al/ITO), an APC alloy, and a stacked structure of APC alloy and ITO (ITO/APC/ITO). The APC alloy is an alloy of silver (Ag), palladium (Pd), and copper (Cu).

The fourth VIA layer VIA4 may be located above the connection electrode layer ITOL. The fourth VIA layer VIA4 may be a fourth planarization layer for planarizing a step difference caused by the connection electrode layer ITOL, but the present disclosure is not limited thereto. The fourth VIA layer VIA4 may cover the connection electrode layer ITOL and the light emitting element LD. Similar to the first VIA layer VIA1, the fourth VIA layer VIA4 may be formed as a single layer or multiple layers including an organic layer and/or an inorganic layer.

The fourth source metal layer SD4 may be formed on the fourth VIA layer VIA 4. The fourth source metal layer SD4 may include a fan-out line for and a PAD. The fanout line sol may be connected to the second bridge electrode BRE2 through a contact hole CH passing through the fourth VIA layer VIA4 and the third VIA layer VIA 3. The fan out line sol may be electrically connected to the data line DL. The PAD may be electrically connected to the fan-out line for. The PAD may be electrically connected to the data line DL through the fan-out line sol. In some embodiments, the PAD may be integrally formed with the fan-out line FOL. For example, the PAD may be an end region of the fan-out line sol exposed by the protective layer PVX. In plan, the PAD may be positioned to overlap the sub-pixel SPX (or the emission area EA).

The fourth source metal layer SD4 may be formed as a single layer or a plurality of layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or any alloy thereof.

The protection layer PVX may be located on the fourth source metal layer SD 4. The protective layer PVX may be formed as a single layer or multiple layers including an organic layer and/or an inorganic layer. The protective layer PVX may cover the lower member including the light emitting element LD. The protective layer PVX may reduce or prevent penetration of moisture or air into the lower member. Further, the protective layer PVX may protect the above-described lower member from foreign matter such as dust.

The flexible film FPCB on which the active driving circuit SIC is mounted may be positioned on the protective layer PVX. The source driving circuit SIC may be connected to a PAD (e.g., a PAD exposed by the protective layer PVX) through a flexible film FPCB. The source driving circuit SIC may be electrically connected to the data line DL. Although a case where the source driving circuit SIC has a chip-on-film structure is illustrated in fig. 7, the present disclosure is not limited thereto.

As described above, the thin film transistor TFT and the light conversion pattern LCP are located in substantially the same layer, the light emitting element LD is located on the light conversion pattern LCP, and the PAD is located on the fourth VIA layer VIA4 covering the light emitting element LD. The PAD is connected to the source driving circuit SIC located at the uppermost portion of the display device 10 (see fig. 2). That is, all components of the display device 10 may be formed on one surface of the substrate SUB through a continuous process. The yield of the display device 10 in which a pattern is formed on only one surface of the substrate SUB can be improved as compared with a display device according to a comparative embodiment (e.g., a display device in which patterns are formed on both surfaces of the substrate SUB) which will be described later with reference to fig. 18.

Further, the display device 10 (or sub-pixel SPX) includes a light conversion pattern LCP, so that a full-color image can be presented by using only light emitting elements LD of a single color (e.g., light emitting elements that emit blue light). The transfer efficiency of the light emitting element LD can be improved as compared with the display device according to the comparative embodiment including light emitting elements of several colors (accordingly, the light emitting elements of several colors are individually transferred).

Further, a PAD (and a fan-out line sol) is formed in the uppermost layer of the display device 10. In other words, any non-emission area or bezel for the PAD (and the fan-out line FOL) is unnecessary, so that a borderless display device can be realized.

Referring to fig. 8, the light emitting element LD may be a light emitting structure including a first semiconductor layer 11 (or a first semiconductor), an active layer 12 (or a light emitting layer), a second semiconductor layer 13 (or a second semiconductor), a first contact electrode ELT1, and a second contact electrode ELT 2. In some embodiments, the light emitting element LD may further include a base substrate 14 located at the lowermost portion. The base substrate 14 may be a sapphire substrate, but the present disclosure is not limited thereto.

The first semiconductor layer 11 may be located on one surface of the active layer 12. The first semiconductor layer 11 may be made of GaN doped with a p-type conductive dopant such as Mg, zn, ca, or Ba.

The active layer 12 may be located on a portion of one surface of the second semiconductor layer 13. The active layer 12 may include a material having a single quantum well structure or a multiple quantum well structure. When the active layer 12 includes a material having a multi-quantum well structure, the active layer 12 may have a structure in which a plurality of well layers and a plurality of barrier layers are alternately stacked. The well layer may be formed of InGaN, and the barrier layer may be formed of GaN or AlGaN. However, the present disclosure is not limited thereto. Alternatively, the active layer 12 may have a structure in which semiconductor materials having a high energy band gap and semiconductor materials having a low energy band gap are alternately stacked, and include other group III to group V semiconductor materials according to a wavelength band of the emitted light.

When the active layer 12 includes InGaN, the color of the emitted light may vary according to the content of indium (In). For example, as the content of indium (In) increases, the wavelength band of light emitted from the active layer 12 may be shifted to a red wavelength band. As the content of indium (In) decreases, the wavelength band of light emitted from the active layer 12 may shift to a blue wavelength band. That is, the color (or wavelength band) of light emitted from the light emitting element LD may be determined according to the content of indium (In) of the active layer 12.

The second semiconductor layer 13 may be located on the other surface of the active layer 12 or between the active layer 12 and the base substrate 14. For example, the second semiconductor layer 13 may be made of GaN doped with an n-type conductive dopant such as Si, ge, se, or Sn.

The first contact electrode ELT1 may be located on one surface of the first semiconductor layer 11, and the second contact electrode ELT2 may be located on one surface of the second semiconductor layer 13.

The first contact electrode ELT1 and the first connection electrode CNE1 may be adhered to each other by a conductive adhesive member such as an Anisotropic Conductive Film (ACF) or an Anisotropic Conductive Paste (ACP). Alternatively, the first contact electrode ELT1 and the first connection electrode CNE1 may be adhered to each other through a welding process.

In an embodiment, the light emitting element LD may have a mesa structure for a flip chip type. For example, the light emitting element LD may have a mesa region in which the other of the first semiconductor layer 11 and the second semiconductor layer 13 is partially exposed by one of the first semiconductor layer 11 and the second semiconductor layer 13. For example, in the light emitting element LD, the first semiconductor layer 11 may have a shape protruding on one surface of the second semiconductor layer 13, and one surface of the second semiconductor layer 13 or a portion thereof may be partially exposed by the first semiconductor layer 11. However, the present disclosure is not limited thereto.

Referring to fig. 1 to 9, each of the sub-pixels SPX1 to SPX3 included in the pixel PX is substantially the same as or similar to the sub-pixel SPX shown in fig. 7, and thus, overlapping description will not be repeated.

The pixel PX may include light emitting elements LD1 to LD3 disposed in the sub emission areas ea_s1 to ea_s3. For example, the first light emitting element LD1 may be disposed in the first sub-emission area ea_s1, the second light emitting element LD2 may be disposed in the second sub-emission area ea_s2, and the third light emitting element LD3 may be disposed in the third sub-emission area ea_s3.

In an embodiment, the light emitting elements LD1 to LD3 may emit the same single color (or wavelength band) light. For example, each of the light emitting elements LD1 to LD3 may be a blue light emitting element for emitting blue light, but the present disclosure is not limited thereto.

In the first sub-emission area ea_s1, the first light conversion pattern LCP1 for the first sub-pixel SPX1 may be located or disposed in the opening OP 1. The first light conversion pattern LCP1 may include a first color filter CF1 and a first color conversion pattern CCP1 located on the first color filter CF 1. In the second sub-emission area ea_s2, a second light-converting pattern LCP2 for the second sub-pixel SPX2 may be located or disposed in the opening OP 2. The second light conversion pattern LCP2 may include a second color filter CF2 and a second color conversion pattern CCP2 on the second color filter CF 2. In the third sub-emission area ea_s3, a third light-converting pattern LCP3 for the third sub-pixel SPX3 may be located or disposed in the opening OP 3. The third light conversion pattern LCP3 may include a third color filter CF3 and a third color conversion pattern CCP3 located on the third color filter CF 3.

The first, second and third color conversion patterns CCP1, CCP2 and CCP3 may include a base resin BR, color conversion particles QD and light scattering particles SCT.

The base resin BR may have high light transmittance and excellent dispersion characteristics for the color conversion particles QD. For example, the base resin BR may include an organic material such as an epoxy resin, an acrylic resin, a card poly (cardo) resin, or an imide resin.

The color conversion particles QD may convert light of a color (or wavelength band) emitted from the light emitting elements LD1 to LD3 (or the light emitting element LD (see fig. 7)) into light of a corresponding color (or a corresponding wavelength band). In an example, when the first subpixel SPX1 is a red pixel, the first color conversion pattern CCP1 may include first color conversion particles QD1 of red quantum dots, which convert light emitted from the first light emitting element LD1 into red (or red wavelength band) light. In another example, when the second subpixel SPX2 is a green pixel, the second color conversion pattern CCP2 may include second color conversion particles QD2 of green quantum dots, which convert light emitted from the second light emitting element LD2 into light of green (or a green wavelength band). In still another example, when the third subpixel SPX3 is a blue pixel, the third color conversion pattern CCP3 may include third color conversion particles QD3 of blue quantum dots, which convert light emitted from the third light emitting element LD3 into light of blue (or blue wavelength band). Alternatively, when the third light emitting element LD3 emits blue light, the third color conversion pattern CCP3 may not include the third color conversion particles QD3.

The color conversion particles QD may have a shape such as a spherical shape, a pyramid shape, a multi-arm shape, a cubic nanoparticle, a nanowire, a nanofabric, or a nano-plate particle. However, the present disclosure is not necessarily limited thereto, and the shape of the color conversion particles QD may be variously changed.

In one or more embodiments, blue light having a relatively short wavelength in the visible light band is incident into the first and second color conversion particles QD1 and QD2, so that the absorption coefficients of the first and second color conversion particles QD1 and QD2 may be increased. Accordingly, the efficiency of light finally emitted from the first and second sub-pixels SPX1 and SPX2 can be improved, and excellent color reproduction can be ensured. Further, by configuring the pixel units of the first, second, and third sub-pixels SPX1, SPX2, and SPX3 using the light emitting elements LD1 to LD3 of the same color (e.g., blue light emitting elements), it is made possible to improve the manufacturing efficiency of the display device 10.

The light scattering particles SCT may have a refractive index different from that of the base resin BR and form an optical interface with the base resin BR. The light scattering particles SCT may be metal oxide particles or organic particles. In some embodiments, the light scattering particles SCT may be omitted.

In some embodiments, the capping layer may be located at an upper portion and/or a lower portion of each of the first, second, and third color conversion patterns CCP1, CCP2, and CCP 3. The capping layer may seal (or cover) each of the first, second, and third color conversion patterns CCP1, CCP2, and CCP3, and may reduce or prevent the possibility of damaging or contaminating the first, second, and third color conversion patterns CCP1, CCP2, and CCP3 due to penetration of impurities (or solutions used in subsequent processes) such as moisture or air from the outside. The capping layer may be configured as a single layer or multiple layers including silicon oxide (SiO _x ) Silicon nitride (SiN) _x ) Silicon oxynitride (SiO) _x N _y ) Alumina (AlO) _x ) And titanium oxide (TiO) _x ) But the present disclosure is not limited thereto.

The color filters CF1 to CF3 may be located on the bottoms of the color conversion patterns CCP1 to CCP 3. The color filters CF1 to CF3 may include a color filter material for allowing light of the corresponding color converted by the color conversion patterns CCP1 to CCP3 to be selectively transmitted therethrough. The color filters CF1 to CF3 may include red, green, and blue color filters. In an example, when the first subpixel SPX1 is a red pixel, a first color filter CF1 allowing red light to transmit therethrough may be located on the bottom of the first color conversion pattern CCP 1. When the second subpixel SPX2 is a green pixel, a second color filter CF2 allowing green light to transmit therethrough may be located on the bottom of the second color conversion pattern CCP 2. When the third subpixel SPX3 is a blue pixel, a third color filter CF3 allowing blue light to transmit therethrough may be located on the bottom of the third color conversion pattern CCP 3.

Although a case where the color filters CF1 to CF3 and the color conversion patterns CCP1 to CCP3 are in contact with each other is illustrated in fig. 9, the present disclosure is not limited thereto. In some embodiments, at least one component may be further included between the color filters CF1 to CF3 and the color conversion patterns CCP1 to CCP 3. For example, the first light conversion pattern LCP1 may further include a low refractive layer between the first color filter CF1 and the first color conversion pattern CCP1, and the low refractive layer may allow light provided from the first color conversion pattern CCP1 to be recycled through total reflection, thereby improving light efficiency (e.g., external quantum efficiency or light emission efficiency). Each of the second and third light conversion patterns LCP2 and LCP3 may further include a refractive layer.

As described above, the pixel PX (or the display device 10 (see fig. 3)) can improve light emission efficiency, and can ensure excellent color reproduction by using the color conversion particles QD. Further, the pixel PX (or the display device 10 (see fig. 3)) includes only the light emitting elements LD1 to LD3 (e.g., blue light emitting elements) of the same color, so that the manufacturing efficiency of the display device 10 can be improved.

Referring to fig. 3, 7, 10 and 11, each of the sub-pixel spx_1 shown in fig. 10 and the sub-pixel spx_2 shown in fig. 11 may be substantially the same as or similar to the sub-pixel SPX shown in fig. 7 except for the reflective partition wall RMTL and the light conversion pattern LCP. Therefore, overlapping descriptions will not be repeated.

As shown in fig. 10, the sub-pixel spx_1 may further include a reflective partition wall RMTL.

The reflective dividing wall RMTL may be positioned or formed to cover at least a portion of the sidewall of the opening OP/at least a portion of the sidewall defined by the opening OP. The reflective partition wall RMTL may allow light emitted from the light emitting element LD to advance in an image display direction (e.g., an opposite direction of the third direction DR 3) of the display apparatus 10. For this purpose, the reflective partition wall RMTL may be configured with a material having a constant reflectivity. For example, the reflective separation wall RMTL may include an opaque metal such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), or any alloy thereof.

In one or more embodiments, the reflective separation wall RMTL may be formed by using at least one of the first gate layer GAT1, the second gate layer GAT2, the first source metal layer SD1, the second source metal layer SD2, and the third source metal layer SD 3. For example, after forming the opening in the second VIA layer VIA2, the reflective partition wall RMTL may be formed by using only the third source metal layer SD 3. In another example (similar to the second transistor electrode DE, the first bridge pattern BRP1, and the first bridge electrode BRE 1), the reflective separation wall RMTL may be formed by using the first, second, and third source metal layers SD1, SD2, and SD 3.

The same function as the reflective dividing wall RMTL can be performed with a structure (e.g., a structure located near the opening OP) in which the second transistor electrode DE, the first bridge pattern BRP1, and the first bridge electrode BRE1 are configured. The reflective dividing wall RMTL may be omitted.

As shown in fig. 11, the sub-pixel spx_2 may omit the light conversion pattern LCP (see fig. 7). According to product specifications, the color filter CF (see fig. 7) for reducing or preventing external light reflection and the color conversion particles QD (see fig. 7) for improving luminous efficiency may be omitted. The light emitting element LD may emit light of different colors for each sub-pixel spx_2. An example will be described with reference to fig. 3. The light emitting element LD of the first subpixel SPX1 may emit light of a first color (e.g., red), the light emitting element LD of the second subpixel SPX2 may emit light of a second color (e.g., green), and the light emitting element LD of the third subpixel SPX3 may emit light of a third color (e.g., blue). The yield of the display device 10 (see fig. 3) in which the pattern is formed on only one surface of the substrate SUB can be improved, and a borderless display device can be realized.

Referring to fig. 12, the tiled display device TD may include a plurality of display devices 10_1 to 10_4 and an engaging portion SM. For example, the tiled display device TD may include a first display device 10_1, a second display device 10_2, a third display device 10_3, and a fourth display device 10_4.

The display devices 10_1 to 10_4 may be arranged in a mesh form. The display devices 10_1 to 10_4 may be arranged in a matrix form on M rows and N columns. For example, the first display device 10_1 and the second display device 10_2 may be adjacent to each other in the first direction DR 1. The first display device 10_1 and the third display device 10_3 may be adjacent to each other in the second direction DR 2. The third display device 10_3 and the fourth display device 10_4 may be adjacent to each other in the first direction DR 1. The second display device 10_2 and the fourth display device 10_4 may be adjacent to each other in the second direction DR 2.

However, the number and arrangement of the display devices 10_1 to 10_4 in the tiled display device TD are not limited to those shown in fig. 12. The number and arrangement of the display devices 10_1 to 10_4 in the tiled display device TD may be determined according to the size of each of the display device 10 and the tiled display device TD and the shape of the tiled display device TD.

The display devices 10_1 to 10_4 may have the same size, but the present disclosure is not limited thereto. For example, in some embodiments, the display devices 10_1 to 10_4 may have different sizes.

Each of the display devices 10_1 to 10_4 may have a rectangular shape including long sides and short sides. The display devices 10_1 to 10_4 may be positioned such that long sides or short sides are connected to each other. Some or all of the display devices 10_1 to 10_4 may be located at edges of the tiled display device TD, and may form one side of the tiled display device TD. At least one of the display devices 10_1 to 10_4 may be located at least one corner of the tiled display device TD, and two adjacent sides of the tiled display device TD may be formed. At least one of the display devices 10_1 to 10_4 may be surrounded by other display devices.

Each of the display devices 10_1 to 10_4 may be substantially the same as the display device 10 described in connection with fig. 1 to 6. Accordingly, a repetitive description of each of the display devices 10_1 to 10_4 will be omitted.

The engagement portion SM may include a coupling member or an adhesive member. The display devices 10_1 to 10_4 may be connected to each other by a coupling member or an adhesive member of the joint portion SM. The engaging portion SM may be located between the first display device 10_1 and the second display device 10_2, between the first display device 10_1 and the third display device 10_3, between the second display device 10_2 and the fourth display device 10_4, and between the third display device 10_3 and the fourth display device 10_4.

Referring to fig. 13, the joining portion SM may have a plane shape of a cross or a plus sign in a central region of the tiled display device TD in which the first display device 10_1, the second display device 10_2, the third display device 10_3, and the fourth display device 10_4 are adjacent to each other. The engaging portion SM may be located between the first display device 10_1 and the second display device 10_2, between the first display device 10_1 and the third display device 10_3, between the second display device 10_2 and the fourth display device 10_4, and between the third display device 10_3 and the fourth display device 10_4.

The first display device 10_1 may include first pixels PX1 arranged in a matrix form in the first direction DR1 and the second direction DR2 to display an image. The second display device 10_2 may include second pixels PX2 arranged in a matrix form in the first direction DR1 and the second direction DR2 to display an image. The third display device 10_3 may include third pixels PX3 arranged in a matrix form in the first direction DR1 and the second direction DR2 to display an image. The fourth display device 10_4 may include fourth pixels PX4 arranged in a matrix form in the first direction DR1 and the second direction DR2 to display an image. Each of the pixels PX1 to PX4 may be substantially the same as or similar to the pixel PX described with reference to fig. 3 and 4.

The minimum distance between the first pixels PX1 adjacent to each other in the first direction DR1 may be defined as a first horizontal separation distance GH1, and the minimum distance between the second pixels PX2 adjacent to each other in the first direction DR1 may be defined as a second horizontal separation distance GH2. The first horizontal separation distance GH1 and the second horizontal separation distance GH2 may be substantially the same.

The joint portion SM may be located between the first pixel PX1 and the second pixel PX2 adjacent to each other in the first direction DR 1. The minimum distance GG1 between the first pixel PX1 and the second pixel PX2 adjacent to each other in the first direction DR1 may be a sum of the minimum distance GHS1 between the first pixel PX1 and the bonding section SM in the first direction DR1, the minimum distance GHS2 between the second pixel PX2 and the bonding section SM in the first direction DR1, and the width GSM1 of the bonding section SM in the first direction DR 1.

The minimum distance GG1, the first horizontal separation distance GH1, and the second horizontal separation distance GH2 between the first pixel PX1 and the second pixel PX2 adjacent to each other in the first direction DR1 may be substantially the same. For this, a minimum distance GHS1 between the first pixel PX1 and the bonding portion SM in the first direction DR1 (e.g., a distance from the first pixel PX1 located at the outermost portion of the first display device 10_1 to an edge of the first display device 10_1) may be smaller than the first horizontal spacing distance GH1, and a minimum distance GHS2 between the second pixel PX2 and the bonding portion SM in the first direction DR1 may be smaller than the second horizontal spacing distance GH2. Further, the width GSM1 of the engagement portion SM in the first direction DR1 may be smaller than the first horizontal spacing distance GH1 or the second horizontal spacing distance GH2.

The minimum distance between the third pixels PX3 adjacent to each other in the first direction DR1 may be defined as a third horizontal separation distance GH3, and the minimum distance between the fourth pixels PX4 adjacent to each other in the first direction DR1 may be defined as a fourth horizontal separation distance GH4. The third horizontal separation distance GH3 and the fourth horizontal separation distance GH4 may be substantially the same.

The joint portion SM may be located between the third pixel PX3 and the fourth pixel PX4 adjacent to each other in the first direction DR 1. The minimum distance GG4 between the third pixel PX3 and the fourth pixel PX4 adjacent to each other in the first direction DR1 may be a sum of the minimum distance GHS3 between the third pixel PX3 and the bonding section SM in the first direction DR1, the minimum distance GHS4 between the fourth pixel PX4 and the bonding section SM in the first direction DR1, and the width GSM1 of the bonding section SM in the first direction DR 1.

The minimum distance GG4, the third horizontal separation distance GH3, and the fourth horizontal separation distance GH4 between the third pixel PX3 and the fourth pixel PX4 adjacent to each other in the first direction DR1 may be substantially the same. For this, a minimum distance GHS3 between the third pixel PX3 and the bonding section SM in the first direction DR1 may be smaller than the third horizontal spacing distance GH3, and a minimum distance GHS4 between the fourth pixel PX4 and the bonding section SM in the first direction DR1 may be smaller than the fourth horizontal spacing distance GH4. Further, the width GSM1 of the engagement portion SM in the first direction DR1 may be smaller than the third horizontal spacing distance GH3 or the fourth horizontal spacing distance GH4.

The minimum distance between the first pixels PX1 adjacent to each other in the second direction DR2 may be defined as a first vertical separation distance GV1, and the minimum distance between the third pixels PX3 adjacent to each other in the second direction DR2 may be defined as a third vertical separation distance GV3. The first and third vertical separation distances GV1 and GV3 may be substantially the same.

The joint portion SM may be located between the first pixel PX1 and the third pixel PX3 adjacent to each other in the second direction DR 2. The minimum distance GG2 between the first pixel PX1 and the third pixel PX3 adjacent to each other in the second direction DR2 may be a sum of the minimum distance GVS1 between the first pixel PX1 and the bonding section SM in the second direction DR2, the minimum distance GVS3 between the third pixel PX3 and the bonding section SM in the second direction DR2, and the width GSM2 of the bonding section SM in the second direction DR 2.

The minimum distance GG2, the first vertical separation distance GV1, and the third vertical separation distance GV3 between the first pixel PX1 and the third pixel PX3 adjacent to each other in the second direction DR2 may be substantially the same. For this, the minimum distance GVS1 between the first pixel PX1 and the bonding portion SM in the second direction DR2 may be smaller than the first vertical spacing distance GV1, and the minimum distance GVS3 between the third pixel PX3 and the bonding portion SM in the second direction DR2 may be smaller than the third vertical spacing distance GV3. Further, the width GSM2 of the engagement portion SM in the second direction DR2 may be smaller than the first vertical spacing distance GV1 or the third vertical spacing distance GV3.

The minimum distance between the second pixels PX2 adjacent to each other in the second direction DR2 may be defined as a second vertical separation distance GV2, and the minimum distance between the fourth pixels PX4 adjacent to each other in the second direction DR2 may be defined as a fourth vertical separation distance GV4. The second vertical separation distance GV2 and the fourth vertical separation distance GV4 may be substantially the same.

The bonding portion SM may be located between the second pixel PX2 and the fourth pixel PX4 adjacent to each other in the second direction DR 2. The minimum distance GG3 between the second pixel PX2 and the fourth pixel PX4 adjacent to each other in the second direction DR2 may be a sum of the minimum distance GVS2 between the second pixel PX2 and the bonding section SM in the second direction DR2, the minimum distance GVS4 between the fourth pixel PX4 and the bonding section SM in the second direction DR2, and the width GSM2 of the bonding section SM in the second direction DR 2.

The minimum distance GG3, the second vertical separation distance GV2, and the fourth vertical separation distance GV4 between the second pixel PX2 and the fourth pixel PX4 adjacent to each other in the second direction DR2 may be substantially the same. For this, the minimum distance GVS2 in the second direction DR2 between the second pixel PX2 and the bonding portion SM may be smaller than the second vertical spacing distance GV2, and the minimum distance GVS4 in the second direction DR2 between the fourth pixel PX4 and the bonding portion SM may be smaller than the fourth vertical spacing distance GV4. Further, the width GSM2 of the engagement portion SM in the second direction DR2 may be smaller than the second vertical spacing distance GV2 or the fourth vertical spacing distance GV4.

As shown in fig. 13, in order to allow the joint portion SM not to be observed between the respective images displayed by the display devices 10_1 to 10_4, the minimum distance between the pixels of the display devices adjacent to each other may be substantially the same as the minimum distance between the pixels of each of the display devices.

Referring to fig. 14, each of the first display device 10_1 and the second display device 10_2 includes a substrate SUB, a thin film transistor layer TFTL (or a pixel circuit layer), and a light emitting element layer EML. The thin film transistor layer TFTL and the light emitting element layer EML have been described in detail with reference to fig. 7. In fig. 14, a description repeated with the description of fig. 7 will be omitted.

The thin film transistor layer TFTL may further include a first protective layer PAS1 and a second protective layer PAS2, and the light emitting element layer EML may include a third protective layer PAS3. The first protective layer PAS1 may be located on the first VIA layer VIA1, the second protective layer PAS2 may be located on the second VIA layer VIA2, and the third protective layer PAS3 may be located on the third VIA layer VIA 3. When each of the first, second, and third VIA layers VIA1, VIA2, and VIA3 is formed as an organic layer, each of the first, second, and third protective layers PAS1, PAS2, and PAS3 may be formed as an inorganic layer (e.g., a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer).

The substrate SUB may include a first surface 41 on which the thin film transistor layer TFTL is located, a second surface 42 facing the first surface 41, and a first side surface 43 located between the first surface 41 and the second surface 42. The first surface 41 may be a front or top surface of the substrate SUB, and the second surface 42 may be a rear or bottom surface of the substrate SUB.

In addition, substrate SUB may further include chamfer surfaces 44_1 and 44_2 between first surface 41 and first side surface 43 and between second surface 42 and first side surface 43, respectively. The thin film transistor layer TFTL and the light emitting element layer EML may not be located on the chamfer surfaces 44_1 and 44_2. Due to the chamfer surfaces 44_1 and 44_2, the possibility of the substrate SUB of the first display device 10_1 and the substrate SUB of the second display device 10_2 being damaged when colliding with each other can be reduced or prevented.

Chamfer surfaces 44_1 and 44_2 may even be located between first surface 41 and other side surfaces than first side surface 43 and between second surface 42 and other side surfaces than first side surface 43. For example, as shown in fig. 12, when the first and second display devices 10_1 and 10_2 have rectangular planar shapes, the chamfer surfaces 44_1 and 44_2 may be located between the first surface 41 and each of the second, third, and fourth side surfaces, and between the second surface 42 and each of the second, third, and fourth side surfaces.

In some embodiments, at least one functional layer may be located on the bottom of the substrate SUB. For example, the functional layer may be attached to the bottom of the substrate SUB by a transparent adhesive member such as an optically transparent adhesive film or an optically transparent adhesive resin. For example, the functional layer may include an anti-glare layer and/or a light transmittance adjusting layer. The anti-glare layer may be designed such that external light is diffusely reflected to reduce or prevent degradation of visibility of an image when external light is reflected as it is. The contrast of the images displayed by the first display device 10_1 and the second display device 10_2 may be increased by the anti-glare layer. The light transmittance adjustment layer may be designed to reduce the transmittance of external light or light reflected from the first display device 10_1 and the second display device 10_2. The distance GSUB between the substrate SUB of the first display device 10_1 and the substrate SUB of the second display device 10_2 can be reduced or prevented from being visible from the outside. The anti-glare layer may be implemented as a polarizer, and the light transmittance adjusting layer may be implemented as a retarder. However, the present disclosure is not limited thereto.

Meanwhile, an example of the tiled display device TD taken along the lines K-K ', L-L', and M-M 'is substantially the same as the example of the tiled display device TD taken along the line J-J' described in connection with fig. 14, and thus a description thereof will be omitted.

Fig. 15 and 16 are enlarged layout diagrams showing the region BB shown in fig. 12. In fig. 15, the first display device 10_1 is schematically shown based on the thin film transistor layer TFTL shown in fig. 14. In fig. 16, the first display device 10_1 is schematically shown based on components (e.g., fan-out line sol and PAD) on top of the light emitting element layer EML shown in fig. 14. For convenience of description, the first pixel PX1 is shown. The second display device 10_2, the third display device 10_3, and the fourth display device 10_4 have substantially the same configuration as the first display device 10_1, and thus, duplicate descriptions will be omitted.

Referring to fig. 15 and 16, the contact hole CH may be located at an upper edge of the first display device 10_1. When the data line DL (e.g., the power line PL or another signal line) of the first display device 10_1 extends in the second direction DR2, the contact holes CH may be located at the upper and lower edges of the first display device 10_1. Alternatively, when the data line DL of the first display device 10_1 extends in the first direction DR1, the contact holes CH may be located at left and right edges of the first display device 10_1. However, this is merely illustrative, and the position of the contact hole CH is not limited thereto. The position of the contact hole CH may be freely changed within a range overlapping with or connected to the data line DL.

As shown in fig. 16, the fanout line sol and the PAD may be located in the uppermost layer of the first display device 10_1. The PAD may be located in one area (e.g., a central area) of the first display device 10_1, and the fan-out line sol may extend from the PAD to the contact hole CH. The fan-out line sol may electrically connect the data line DL (e.g., the power line PL or another signal line) and the PAD to each other through the contact hole CH.

Fig. 17 is an enlarged layout diagram showing the region BB shown in fig. 12 in the display device according to the comparative embodiment. For convenience of description, a PAD pad_c and a first pixel PX1_c located at an upper side of the display device 10_c according to the comparative embodiment are shown in fig. 17.

Referring to fig. 17, the PAD pad_c may be located at an upper edge of the display device 10_c according to the comparative embodiment.

Each PAD pad_c may be connected to a data line on the upper surface of the substrate SUB. Further, each PAD pad_c may be connected to a side surface line (see "SSL" shown in fig. 18). The side surface lines SSL may be located on the top surface, one side surface, and the bottom surface (or rear surface) of the substrate SUB. The side surface lines SSL may be connected to lower connection lines (see "CCL" shown in fig. 18) on the bottom surface of the substrate SUB.

Fig. 18 is a cross-sectional view showing the display device 10_c taken along the line N-N' shown in fig. 17 according to the comparative embodiment. In fig. 18, the same components as those of the cross-sectional views shown in fig. 14 and 7 are denoted by the same reference numerals, and the description repeated with the description of fig. 14 and 7 will be omitted.

Referring to fig. 18, a pixel electrode AND (or a first pixel electrode) AND a common electrode COM (or a second pixel electrode) may be located on the second protective layer PAS 2. The pixel electrode AND the common electrode COM may correspond to the first AND second connection electrodes CNE1 AND CNE2, respectively, shown in fig. 7.

The light emitting element LD may be located on the pixel electrode AND the common electrode COM which are not covered with the third VIA layer VIA3 AND the third protective layer PAS 3.

The PAD pad_c may be located on the first protective layer PAS 1. A portion of the PAD pad_c is not covered by the second protective layer PAS2 and the third protective layer PAS3, and may instead be exposed. The PAD pad_c may include the same material as the pixel electrode AND the common electrode COM.

The PAD pad_c may be connected to the data line DL through a thirty-fifth contact hole CT35 passing through the first protective layer PAS 1. The PAD pad_c is located at the edge of the display device 10_c and does not overlap the light emitting element LD.

The lower connection line CCL may be located on the bottom surface of the substrate SUB. The lower connection line CCL may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or any alloy thereof.

The fifth VIA layer VIA5 may be located on a portion of the lower connection line CCL. The fifth VIA layer VIA5 may be formed as an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

The fifth protective layer PAS5 may be located above/below the fifth VIA layer VIA 5. The fifth protective layer PAS5 may be formed as an inorganic layer (e.g., a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer).

The side surface lines SSL may be located on the top surface edge, side surface and bottom surface edge of the substrate SUB. One end of the side surface line SSL may be connected to the PAD pad_c. One end of the side surface line SSL may be connected to the PAD pad_c through a thirty-sixth contact hole CT36 passing through the third protective layer PAS 3. The other end of the side surface line SSL may be connected to the lower connection line CCL.

The side surface line SSL may be located on a side surface of the substrate SUB, a side surface of the buffer layer BF, a side surface of the first gate insulating layer GI1, a side surface of the second gate insulating layer GI2, a side surface of the interlayer insulating layer ILD, a side surface of the first protective layer PAS1, and a side surface of the third VIA layer VIA3 (and/or the second VIA layer VIA 2).

Since the PAD pad_c formed at the top surface edge of the substrate SUB and the lower connection line CCL formed at the bottom surface edge of the substrate SUB are connected to each other by the side surface line SSL, a coating pattern surrounding the edge region (or the side surface line SSL) may be formed to protect the side surface line SSL exposed to the outside from moisture and oxygen and reduce or prevent the possibility that the side surface line SSL exposed to the outside is observed from the outside by a user.

The flexible film FPCB may be located on the bottom surface of the fifth protective layer PAS 5. The flexible film FPCB may be connected to the lower connection line CCL through a thirty-seventh contact hole CT37 passing through the fifth VIA layer VIA5 and the fifth protective layer PAS5 by using a conductive adhesive member CAM. A source driving circuit for supplying a data signal to the data line DL may be located on the bottom surface of the flexible film FPCB. The conductive adhesive member CAM may be an anisotropic conductive film or an anisotropic conductive paste.

As described above, in the display device 10_c according to the comparative embodiment, the source driving circuit of the flexible film FPCB on the bottom of the substrate SUB may be connected to the data line DL through the lower connection line CCL, the side surface line SSL, and the PAD pad_c on the bottom of the substrate SUB. The source driving circuit is located on the bottom of the substrate SUB so that pixels can be formed even at the edge of the substrate SUB. However, in addition to the process of forming the thin film transistor TFT on the top of the substrate SUB, the process of forming the lower connection line CCL and the side surface line SSL on the bottom and side surfaces of the substrate SUB is also applicable, and the manufacturing process of the display device 10_c may be relatively complicated. On the other hand, all of the components of the SUB-pixel SPX shown in fig. 7 (and the display device 10 including the SUB-pixel SPX (see fig. 1 and 2)) may be formed on one surface of the substrate SUB by a continuous process. Accordingly, compared to the display device 10_c according to the comparative embodiment, the manufacturing process of the display device 10 including the sub-pixel SPX shown in fig. 7 is relatively simplified, and the yield of the display device 10 can be relatively improved.

Fig. 19 is a block diagram illustrating a display device according to one or more embodiments of the present disclosure. For convenience of description, the first display device 10_1 and the HOST system HOST are shown in fig. 19.

Referring to fig. 12 and 19, the tiled display device TD according to the present disclosure may include a HOST system HOST, a broadcast tuner 210, a signal processor 220, a display unit 230, a speaker 240, a user input unit 250, a Hard Disk Drive (HDD) 260, a network communication unit 270, a User Interface (UI) generator 280, and a controller 290.

HOST system HOST may be implemented as any one of a television system, a home theater system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a Personal Computer (PC), a mobile phone system, and a tablet PC.

The user's command may be entered into HOST system HOST in various forms. For example, a command according to a touch input by a user may be input to HOST system HOST. Alternatively, a user's command according to a keyboard input or a button input of the remote controller may be input to the HOST system HOST.

The HOST system HOST may receive original video data corresponding to an original image input from the outside. HOST system HOST may divide the original video data into video data, the number of which corresponds to the number of display devices. For example, the HOST system HOST may divide the original video data into first video data corresponding to a first image, second video data corresponding to a second image, third video data corresponding to a third image, and fourth video data corresponding to a fourth image corresponding to the first display device 10_1, the second display device 10_2, the third display device 10_3, and the fourth display device 10_4. The HOST system HOST may transmit the first video data to the first display device 10_1, the second video data to the second display device 10_2, the third video data to the third display device 10_3, and the fourth video data to the fourth display device 10_4.

The first display device 10_1 may display a first image according to first video data, the second display device 10_2 may display a second image according to second video data, the third display device 10_3 may display a third image according to third video data, and the fourth display device 10_4 may display a fourth image according to fourth video data. Accordingly, the user can view the original images obtained by combining the first to fourth images displayed in the first to fourth display devices 10_1 to 10_4.

The first display device 10_1 may include a broadcast tuner 210, a signal processor 220, a display unit 230, a speaker 240, a user input unit 250, an HDD 260, a network communication unit 270, a UI generator 280, and a controller 290.

By tuning a channel frequency (e.g., a predetermined channel frequency) under the control of the controller 290, the broadcast tuner 210 may receive a broadcast signal of a corresponding channel through an antenna. The broadcast tuner 210 may include a channel detection module and an RF demodulation module.

The broadcast signal demodulated by the broadcast tuner 210 may be processed by the signal processor 220 and output to the display unit 230 and the speaker 240. The signal processor 220 may include a demultiplexer 221, a video decoder 222, a video processor 223, an audio decoder 224, and an additional data processor 225.

The signal separator 221 separates the demodulated broadcast signal into a video signal, an audio signal, and additional data. The separated video signal, audio signal and additional data are restored by the video decoder 222, audio decoder 224 and additional data processor 225, respectively. When the broadcast signal is transmitted, the video decoder 222, the audio decoder 224, and the additional data processor 225 restore the video signal, the audio signal, and the additional data in a decoding format corresponding to the encoding format.

Meanwhile, the decoded video signal is converted by the video processor 223 to satisfy a vertical frequency, resolution, aspect ratio, etc. applicable to an output standard of the display unit 230, and the decoded audio signal is output to the speaker 240.

The display unit 230 may include a display panel for displaying an image and a panel driver for controlling driving of the display panel.

User input unit 250 may receive signals transmitted from HOST system HOST. The user input unit 250 may be configured to input data related to not only selection of a channel transmitted from the HOST system HOST and selection and operation of a UI menu, but also data related to user selection and input of a command for communication with another display device.

The HDD 260 is used to store various software programs including OS programs, recorded broadcast programs, moving images, photographs, and other data. The HDD 260 may be configured as a storage medium such as a hard disk or a nonvolatile memory.

The network communication unit 270 is for performing near field communication with the HOST system HOST and another display device, and may be implemented as a communication module including an antenna pattern capable of realizing mobile communication, data communication, bluetooth, RF, ethernet, and the like.

The network communication unit 270 may transmit a signal to the mobile communication terminal according to a technical standard or a communication method for mobile communication (e.g., global system for mobile communication (GSM), code Division Multiple Access (CDMA), code division multiple access 2000 (CDMA 2000) ^TM ) Enhanced voice data optimized or enhanced voice data only (EV-DO), wideband CDMA (WCDMA), high Speed Downlink Packet Access (HSDPA), high Speed Uplink Packet Access (HSUPA), long Term Evolution (LTE), long term evolution advanced (LTE-a), 5G, etc.), transmitting/receiving wireless signals to/from at least one of a base station, an external terminal, and a server.

The network communication unit 270 may transmit/receive wireless signals in a communication network according to a wireless internet technology through an antenna pattern to be described later. Wireless internet technologies may include, for example, wireless LAN (WLAN), wireless fidelity (Wi-Fi), direct Wi-Fi, digital Living Network Alliance (DLNA), wireless broadband (WiBro), worldwide Interoperability for Microwave Access (WiMAX), high Speed Downlink Packet Access (HSDPA), high Speed Uplink Packet Access (HSUPA), long Term Evolution (LTE), long term evolution-advanced (LTE-a), and the like. The antenna pattern transmits/receives data according to at least one wireless internet technology within a range including internet technologies not listed above.

The UI generator 280 is for generating a UI menu for communicating with the HOST system HOST and another display device, and may be implemented by an algorithm code and an OSD IC. The UI menu for communicating with the HOST system HOST and another display device may be a menu for designating a desired opponent digital TV and selecting a desired function.

The controller 290 is for taking charge of overall control of the first display device 10_1 and taking charge of communication control of the HOST system HOST and the second display device 10_2, the third display device 10_3, and the fourth display device 10_4. The controller 290 may be implemented by a Micro Control Unit (MCU) in which a corresponding algorithm code for control is stored and executed.

The controller 290 controls corresponding control commands and corresponding data transmitted to the HOST system HOST and the second, third and fourth display devices 10_2, 10_3 and 10_4 through the network communication unit 270 according to the input and selection of the user input unit 250. When a control command (e.g., a predetermined control command) and data (e.g., predetermined data) are input from the HOST system HOST and the second, third, and fourth display devices 10_2, 10_3, and 10_4, operations are performed according to the respective control commands.

Meanwhile, the block diagram of the second display device 10_2, the block diagram of the third display device 10_3, and the block diagram of the fourth display device 10_4 are substantially the same as the block diagram of the first display device 10_1 described in connection with fig. 19, and thus, their descriptions will be omitted.

According to the present disclosure, all components of a display device and a tiled display device are formed on one surface of a substrate by a continuous process. Accordingly, the yield of the display device can be improved as compared with a display device in which patterns are formed on both surfaces of a substrate.

Further, according to the present disclosure, the display device and the tiled display device include a light conversion pattern (e.g., color conversion particles for converting the wavelength of incident light and emitting light), so that a full color image can be presented by using only light emitting elements of a single color (e.g., blue light emitting elements). The transfer efficiency of the light emitting element can be improved compared to a display device including light emitting elements of several colors.

Further, the pads and fan-out lines of the display device and the tiled display device are formed in the uppermost layer. Thus, any non-emissive areas or rims for bonding pads and fanout lines are not necessary, and thus a rimless display may be implemented.

Embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some cases, as will be apparent to one of ordinary skill in the art at the time of filing this application, features, characteristics, and/or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics, and/or elements described in connection with other embodiments unless specifically stated otherwise. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the present disclosure as set forth in the appended claims and the functional equivalents thereof included therein.

Claims

1. A display device, comprising:

a substrate comprising an emissive region and a non-emissive region;

a pixel circuit layer over the substrate and including transistors and signal lines in the non-emission region and a color conversion pattern in the emission region;

a light emitting element over the color conversion pattern and electrically connected to the transistor;

an insulating layer covering the light emitting element; and

A pad over the insulating layer and electrically connected to the signal line,

wherein the color conversion pattern is configured to convert a wavelength band of light incident from the light emitting element.

2. The display device according to claim 1, wherein the color conversion pattern is in an opening exposing the substrate while passing through the pixel circuit layer formed in the emission region.

3. The display device of claim 2, wherein the pixel circuit layer further comprises a color filter between the substrate and the color conversion pattern in the emission region,

wherein the transistor and the signal line are separated from the emission region, an

Wherein the light emitting element is configured to emit light through the color filter and the substrate in the emission region.

4. The display device of claim 3, further comprising:

a sub-pixel including the light emitting elements for emitting light of a first color and configured to respectively present different individual colors; and

a first connection electrode over the light emitting element and electrically connecting the first electrode of the light emitting element to the transistor,

wherein the light emitting element comprises a flip chip type micro light emitting diode.

5. The display device according to claim 1, wherein the pixel circuit layer further comprises a light blocking layer between the substrate and the transistor in the non-emission region, and

wherein the light blocking layer defines the emission region.

6. The display device of claim 1, further comprising a fan-out line over the insulating layer, connected to the pad, and electrically connected to the signal line through a contact hole passing through the insulating layer.

7. The display device according to claim 1, further comprising a pixel including the light emitting element,

wherein a distance from an outermost pixel of the pixels to an edge of the substrate in a plan view is shorter than a distance between adjacent pixels of the pixels in a plan view.

8. A display device, comprising:

a substrate comprising an emissive region and a non-emissive region;

a transistor, a signal line, and a power line on the non-emission region of the substrate;

a light emitting element on the emission region of the substrate;

a first connection electrode over the light emitting element and electrically connecting the first electrode of the light emitting element to the transistor;

A second connection electrode over the light emitting element and electrically connecting the second electrode of the light emitting element to the power line;

an insulating layer over the first connection electrode and the second connection electrode; and

and a pad electrically connected to the signal line over the insulating layer and including at least a portion overlapping the light emitting element in a plan view.

9. The display device according to claim 8, further comprising a color filter between the substrate and the light-emitting element in the emission region,

wherein the transistor and the signal line are separated from the emission region in a plan view, an

10. A tiled display device comprising:

a plurality of display devices; and

an engaging portion that, between the plurality of display devices,

wherein a first display device of the plurality of display devices comprises:

a substrate comprising an emissive region and a non-emissive region;

an insulating layer covering the light emitting element; and

a pad over the insulating layer and electrically connected to the signal line,