CN116500856B

CN116500856B - Method and system for verifying layout of front photomask and back mask of wafer

Info

Publication number: CN116500856B
Application number: CN202310761553.8A
Authority: CN
Inventors: 刘坤明; 叶益修; 侯汉成; 宋嘉铭; 茆同海
Original assignee: Huatong Xindian Nanchang Electronic Technology Co ltd
Current assignee: Huatong Xindian Nanchang Electronic Technology Co ltd
Priority date: 2023-06-27
Filing date: 2023-06-27
Publication date: 2023-08-22
Anticipated expiration: 2043-06-27
Also published as: CN116500856A

Abstract

The application provides a method and a system for verifying the layout of a front photomask and a back mask of a wafer, belonging to the field of wafer photolithography processes; drawing the front photomask layout and the back mask layout of the wafer according to the area where the chip is required to be laid out; repeating lithography on the front surface of the wafer in sequence by adopting a step exposure mode based on the lithography pattern in the front surface photomask layout so as to divide the wafer into a plurality of subareas with the same size by meshing; photoetching the back of the wafer by adopting a whole-surface coverage mode based on the layout of the back mask plate; defining an alignment area on the back of the wafer after photoetching according to processing equipment of a subsequent wafer offline process; based on the photoetching layout and the back mask plate layout of the front surface of the gridded wafer, back exposure judges whether at least two PCM regions exist on the front surface of the wafer in the alignment region; and correspondingly adjusting according to the judgment condition. The application can be used for checking the design layout of the front mask and the back mask of the wafer.

Description

Method and system for verifying layout of front photomask and back mask of wafer

Technical Field

The application belongs to the technical field of wafer photolithography processes, and particularly relates to a method and a system for verifying the layout of a front mask and a back mask of a wafer.

Background

With the continuous progress of integrated circuit manufacturing process, the line width is continuously reduced, the area of semiconductor devices is becoming smaller and smaller, and the layout of semiconductors has been changed from a common single-function separation device to an integrated circuit integrating high-density and multiple functions. Considering the complexity of process development, long-term and high cost, how to obtain as many effective chips on the same silicon wafer as possible will be more and more appreciated by chip designers and manufacturers. In semiconductor fabrication, a mask acts as a carrier by which photolithography enables a designer's idea to be implemented on a silicon wafer, allowing the semiconductor to perform various functions. In addition, the photomask is a carrier for image transmission, the designed circuit pattern is exposed on the photoresist through the electronic laser equipment, the exposed area is developed to form the circuit pattern, the circuit pattern becomes a mask plate similar to a negative film after exposure, and then the mask plate is applied to projection positioning of an integrated circuit, and the projected circuit is etched through an integrated circuit photoetching machine.

The semiconductor wafer process generally includes a wafer front side process and a wafer back side process, and the mask alignment mark of the wafer front side process and the mask alignment mark of the wafer back side process can complete the whole process flow within the identifiable range of the wafer back side process exposure machine. In the current semiconductor wafer manufacturing process, the design and manufacturing process of the photomask and the mask are also very important links, and the layout and the size of the photomask and the mask must be consistent with the manufacturing process and the design of the wafer, otherwise, the subsequent wire-down process is adversely affected. Therefore, in the semiconductor wafer process, the design layout of the photomask and the mask plate must be comprehensively verified to ensure that the wafer process and the design meet the requirements. However, in the semiconductor wafer manufacturing process in the prior art, there is no process for checking the design layout of the front mask and the back mask of the wafer, which results in higher rejection rate of the wafer in the wire-down process.

Disclosure of Invention

In order to solve the technical problems, the application provides a method and a system for verifying the layout of a front mask and a back mask of a wafer.

In one aspect, the application provides a method for verifying the layout of a front mask and a back mask of a wafer, comprising the following steps:

drawing the front photomask layout and the back mask layout of the wafer according to the area where the chip is required to be laid out;

designing a photoetching pattern in the front-side photomask layout according to a preset requirement, wherein the layout of the photoetching pattern comprises pure chip areas and PCM areas with different sizes;

repeating lithography on the front surface of the wafer in sequence in a stepping mode based on the lithography patterns in the front surface photomask layout, so that the wafer is divided into a plurality of subareas with the same size by meshing, and each subarea comprises a pure chip area and a PCM area with different sizes;

photoetching the back of the wafer by adopting a whole-surface coverage mode based on the layout of the back mask plate;

defining an alignment area on the back of the wafer after photoetching according to processing equipment of a subsequent wafer offline process, and forming the back of the wafer with the alignment area;

judging whether at least two PCM regions exist in the alignment region or not based on the photoetching layout of the front side of the gridded wafer and the layout of the back mask plate;

if not, adjusting the position of the whole photoetching pattern where the PCM region in the photoetching pattern is located or adjusting the drawing reference of the back mask plate layout so that at least two PCM regions exist in the alignment region;

if yes, feeding back the drawn information of the front photomask layout and the back mask layout meeting the design requirements.

Compared with the prior art, the application has the beneficial effects that: the front photomask layout and the back mask layout of the wafer are carried out through the chip areas required to be laid on the wafer, the front surface of the meshed wafer and the back surface of the wafer with the alignment areas are processed according to the front photomask layout and the back mask layout, the front surface of the meshed wafer and the back surface of the wafer with the alignment areas are overlapped and arranged based on the center of the wafer to judge whether at least two PCM areas exist in the alignment areas, corresponding adjustment and feedback are carried out according to judgment results, comprehensive verification can be carried out at an early stage before the processing of the downlink procedure of the wafer, rationality of drawing of the front photomask layout and the back mask layout is detected, the manufacturing precision and the stability of the wafer are improved, and the rejection rate of the downlink procedure of the wafer is reduced.

Preferably, the front-side photomask layout uses CAD software to form a photolithography pattern in the front-side photomask layout with a center point of a boundary line of a wafer area to be laid in the X-axis direction as a starting point and with the preset requirement as a rectangular area.

Preferably, the PCM region is located at an edge position of the sub-region, and an area of the PCM region is smaller than an area of the microchip region.

Preferably, the position of the whole photoetching pattern where the PCM region in the photoetching pattern is located is adjusted by adopting CAD software, the PCM region in the photoetching pattern is adjusted along the X-axis or Y-axis direction, and an updated front photomask layout is formed based on the adjusted photoetching pattern.

Preferably, the drawing reference of the back mask layout is adjusted, specifically, the drawing reference is adjusted along the X-axis or Y-axis direction through CAD software, and an updated back mask layout is formed based on the adjusted drawing reference.

Preferably, the chiplet region and the PCM region do not overlap each other and both are distributed throughout the front side reticle layout.

Preferably, when the wafer photolithography process is performed, the same photolithography parameters are set for the pure chip area and the PCM area, so as to realize the representativeness of PCM monitoring to the chip performance parameters.

In another aspect, the application provides a wafer front-side reticle and back-side mask layout verification system comprising:

the drawing module is used for drawing the front photomask layout and the back mask layout of the wafer according to the area where the chip is required to be laid out;

the design module is used for designing the photoetching patterns in the front photomask layout according to preset requirements, wherein the layout of the photoetching patterns comprises pure chip areas and PCM areas with different sizes;

the sequential photoetching module is used for sequentially carrying out repeated photoetching on the front surface of the wafer in a stepping mode based on the photoetching patterns in the front surface photomask layout, so that the wafer is divided into a plurality of subareas with the same size by meshing, and each subarea comprises a pure chip area and a PCM area with different sizes;

the overlay lithography module is used for carrying out lithography on the back of the wafer by adopting a whole-surface overlay mode based on the layout of the back mask plate;

the defining module is used for defining an alignment area on the back of the wafer after photoetching according to processing equipment of a subsequent wafer offline process to form the back of the wafer with the alignment area;

the judging module is used for judging whether at least two PCM regions exist in the alignment region or not based on the photoetching layout of the front side of the gridded wafer and the layout of the back mask plate;

the adjusting module is used for adjusting the position of the whole photoetching pattern where the PCM region in the photoetching pattern is located or adjusting the drawing reference of the back mask plate layout if at least two PCM regions do not exist in the alignment region, so that at least two PCM regions exist in the alignment region;

and the feedback module is used for feeding back the drawn information of the front photomask layout and the back mask layout meeting the design requirement if at least two PCM regions exist in the alignment area.

Compared with the prior art, the application has the beneficial effects that: the verification system is based on the verification method, can carry out comprehensive verification at an early stage before the processing of the wafer in the wire-down process, detects the rationality of the front photomask layout and the back mask layout drawing, improves the precision and the stability of the wafer manufacturing, and reduces the rejection rate of the wafer in the wire-down process.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a flow chart of a layout verification method for a front mask and a back mask of a wafer according to embodiment 1 of the present application;

fig. 2 is a schematic diagram of a wafer surface layout chip according to embodiment 1 of the present application;

FIG. 3 is a schematic diagram of a chip area layout required for drawing a wafer by CAD software according to embodiment 1 of the present application;

FIG. 4 is a schematic diagram of a design lithography pattern in a chip area required for layout of a wafer according to embodiment 1 of the present application;

FIG. 5 is a schematic diagram of a photolithography pattern provided in embodiment 1 of the present application to cover the area of chips required for the whole wafer;

FIG. 6 is an enlarged schematic view of a portion of the symbol A of FIG. 5;

fig. 7 is a schematic layout design diagram of a back mask provided in embodiment 1 of the present application;

FIG. 8 is a block diagram of a layout verification system for front side masks and back side masks of a wafer according to embodiment 2 of the present application, which corresponds to the method of embodiment 1;

fig. 9 is a flow chart of a method for verifying the layout of a front mask and a back mask of a wafer according to embodiment 3 of the present application;

fig. 10 is a block diagram of a layout verification system for front-side masks and back-side masks of a wafer corresponding to the method of embodiment 3 according to embodiment 4 of the present application.

Reference numerals illustrate:

10-wafer;

20-chip;

30-wafer contour lines, 31-bending closing lines and 32-photoetching patterns;

40-subregion, 41-pure chip region, 42-PCM region;

50-back mask layout, 51-alignment area;

61-drawing module, 62-design module, 63-sequential lithography module, 64-overlay lithography module, 65-definition module, 66-judgment module, 67-adjustment module, 68-feedback module.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the application are shown in the drawings, it should be understood that the application may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present application. It will be apparent, however, to one skilled in the art that the application may be practiced without one or more of these details. In other instances, well-known features have not been described in detail so as not to obscure the application; that is, not all features of an actual implementation are described in detail herein, and well-known functions and constructions are not described in detail.

The flow diagrams depicted in the figures are exemplary only and not necessarily all steps are included. For example, some steps may be decomposed, and some steps may be combined or partially combined, so that the order of actual execution may be changed according to actual situations.

It should be noted that the subsequent down-line process referred to in the present application refers to the final step of designing an Integrated Circuit (IC) or a Printed Circuit Board (PCB), that is, delivery manufacturing. In the early stage, final data, such as Layout (Layout) and Mask (Mask) of electronic circuits, which are submitted to the subsequent stage of production, are stored in a tape; tape out is also named accordingly.

In the prior art, the substrate to be evaporated is a transparent glass substrate, so that an image of the alignment mark on the mask plate can be acquired through the glass substrate by using an image acquisition device (such as an optical camera) in an optical alignment mode, and then the alignment mark on the substrate to be evaporated and the alignment mark on the mask plate are aligned by adjusting the relative position between the substrate to be evaporated and the mask plate, so that the alignment of the substrate to be evaporated and the mask plate is realized. The optical alignment mode is simple to operate and has higher alignment precision. However, for a non-transparent substrate to be evaporated, such as a Wafer (Wafer) substrate, the image capturing device cannot capture an image of the alignment mark of the mask through the non-transparent Wafer substrate, so that alignment between the non-transparent Wafer substrate and the mask cannot be achieved; therefore, in the wafer process of the prior art, there is no process for checking the design layout of the front mask and the back mask of the wafer, and it is often found that the design layout of the front mask and/or the back mask of the wafer is not within the discernable range of the process exposure machine after the wafer product is bad after the wafer product is delivered and manufactured.

Example 1

Specifically, fig. 1 is a schematic flow chart of a layout verification method for a front mask and a back mask of a wafer according to the present embodiment.

As shown in fig. 1, the layout verification method for the front mask and the back mask of the wafer in this embodiment includes the following steps:

s101, drawing the front photomask layout and the back mask layout of the wafer according to the area where the chips are required to be laid out.

Specifically, as shown in fig. 2, the area of the wafer where the chips 20 occupy is set according to the requirements of the customer, and the ratio of the area of the wafer where the chips are required to occupy the whole area of the wafer is the maximum in the design process, so that the effective utilization rate is improved. As shown in fig. 3, according to the requirements of the customer, CAD software is used to draw the wafer outline 30 and the bend seal line 31, wherein the region included in the bend seal line 31 in the wafer outline 30 is the area where the wafer needs to be laid out in the present embodiment.

S102, designing a photoetching pattern in the front-side photomask layout according to preset requirements, wherein the layout of the photoetching pattern comprises pure chip areas and PCM areas with different sizes.

And the front photomask layout adopts CAD software, takes the central point of a boundary line of the wafer area required to be laid in the X-axis direction as a starting point, and takes the preset requirement as the rectangular area size to form the photoetching graph in the front photomask layout.

Specifically, as shown in fig. 4, the photolithographic pattern 32 of the front mask layout in which the rectangular frame having the rectangular area size according to the preset requirement is the smallest is set with the center point of the limit of the lowest end of the bending closing line 31 shown in fig. 3 as the starting point. In specific practice, the preset requirement refers to designing a corresponding photolithography pattern by taking a plurality of adjacent chip specifications as a minimum photolithography unit according to the chip specification size required by the customer, wherein the outer edges of the adjacent chips are rectangular.

And S103, performing repeated photoetching on the front surface of the wafer in sequence in a stepping mode based on the photoetching patterns in the front surface photomask layout, so that the wafer is divided into a plurality of subareas with the same size by meshing, and each subarea comprises a pure chip area and a PCM area with different sizes.

Specifically, taking the center point of the lowest limit of the bending closing line 31 shown in fig. 3 as a starting point, the photolithography patterns 32 are distributed along the X-axis direction first, and then distributed sequentially along the moving direction of the Y-axis direction until the whole wafer is distributed to the chip area required to be distributed, and the photolithography patterns 32 are distributed to the chip area required to be distributed to the whole wafer can be referred to as fig. 5.

As shown in fig. 6, the pure chip region 41 (hollow white region in the figure) and the PCM region 42 (hatched region in the figure) do not overlap each other, and both are distributed throughout the front mask layout. When the wafer photolithography process is performed, the same photolithography parameters are set for the pure chip region 41 and the PCM region 42, so as to realize representative PCM monitoring on chip performance parameters. In particular practice, PCM block refers to a monitoring system for manufacturing process control, which is commonly used in the semiconductor manufacturing and other high precision manufacturing industries to monitor various parameters of the manufacturing process to ensure quality and consistency of the product. PCM systems can detect various parameters in the manufacturing process including resistance, inductance, capacitance, current, voltage, etc., which can be collected by sensors or monitoring devices and then analyzed and processed to determine if the manufacturing process is operating properly. If the PCM system detects that the manufacturing process is abnormal, such as overlarge resistance or abnormal current, the process personnel can be informed to adjust, so that errors and defects in the manufacturing process can be effectively reduced, and the quality and stability of the product are improved.

Further, the PCM region 42 is located at an edge position of the sub-region 40, and an area of the PCM region 42 is smaller than an area of the microchip region 41. In particular practice, the PCM region is only used to detect parameters in the manufacturing process in the sub-region, and by measuring the relevant parameters in the PCM region, it is able to know whether all the chip process parameters in the sub-region are normal, without the need of overall detection of the sub-region, thereby improving the process rate of chips in the wafer. As long as the parameters detected by the PCM region are acceptable, it means that the chip process of the pure chip region in the sub-region is satisfactory.

S104, photoetching is conducted on the back of the wafer in a whole-surface coverage mode based on the layout of the back mask plate.

Specifically, the back mask layout 50 shown in fig. 7 is used to perform one-time lithography for covering the entire back surface of the wafer, and the wafer mask needs to perform repeated lithography to cover the entire front surface area of the wafer, and the mask only needs one-time lithography to cover the entire back surface area of the wafer because the typical ratio of the wafer mask to the mask is 5:1 or 4:1.

S105, defining an alignment area on the back of the wafer after photoetching according to the processing equipment of the subsequent wafer offline process, and forming the back of the wafer with the alignment area.

Specifically, as shown in fig. 7, according to the processing equipment of the subsequent wafer offline process, an alignment area 51 is defined on the back surface of the wafer after photolithography, and the alignment area can be used for checking the design layout of the front mask and the back mask of the wafer.

And S106, judging whether at least two PCM regions exist in the alignment region based on the photoetching layout of the front side of the gridded wafer and the layout of the back mask plate.

Specifically, as shown in fig. 7, the alignment area of the present embodiment has two alignment areas according to the processing equipment of the subsequent wafer offline process, so as long as it is determined whether at least one PCM area exists in each alignment area, the determination condition for determining whether at least two PCM areas exist in the alignment area can be met.

And S107, if not, adjusting the position of the whole photoetching pattern where the PCM region in the photoetching pattern is located or adjusting the drawing standard of the layout of the back mask plate so that at least two PCM regions exist in the alignment region.

Specifically, adjusting the position of the whole photoetching pattern where the PCM region in the photoetching pattern is located specifically adopts CAD software to adjust the PCM region in the photoetching pattern along the X-axis or Y-axis direction, and forms an updated front photomask layout based on the adjusted photoetching pattern. And adjusting the drawing reference of the back mask plate layout, specifically adjusting the drawing reference along the X-axis or Y-axis direction through CAD software, and forming an updated back mask plate layout based on the adjusted drawing reference.

In summary, the front-side photomask layout and the back-side mask layout of the wafer are performed by arranging the chip areas in the wafer, the front-side and the back-side of the wafer are processed according to the front-side photomask layout and the back-side mask layout to obtain the front side of the grid-shaped wafer and the back side of the wafer with the alignment areas, the front-side and the back side of the grid-shaped wafer are overlapped based on the center of the wafer to determine whether at least two PCM areas exist in the alignment areas, and corresponding adjustment and feedback are performed according to the determination result.

Example 2

This embodiment provides a block diagram of a system corresponding to the method described in embodiment 1. Fig. 8 is a block diagram of a layout verification system for front-side masks and back-side masks of a wafer according to the present embodiment, and as shown in fig. 8, the system includes:

a drawing module 61, configured to draw a front mask layout and a back mask layout of the wafer according to a region where the wafer needs to be laid out with chips;

the design module 62 is configured to design a photolithography pattern in the front-side photomask layout according to a preset requirement, where the layout of the photolithography pattern includes pure chip areas and PCM areas with different sizes;

a sequential photolithography module 63, configured to sequentially perform repeated photolithography on the front surface of the wafer in a step-by-step manner based on the photolithography pattern in the front surface photomask layout, so that the wafer is gridded into a plurality of sub-areas with the same size, and each sub-area includes a pure chip area and a PCM area with different sizes;

a cover lithography module 64, configured to perform lithography on the back surface of the wafer by using a full-face cover manner based on the layout of the back mask;

a defining module 65, configured to define an alignment area on the back surface of the wafer after photolithography according to a process device of a subsequent wafer offline process, so as to form a back surface of the wafer with the alignment area;

a judging module 66, configured to judge whether at least two PCM areas exist in the alignment area based on the lithographic layout of the front side of the gridded wafer and the layout of the back mask;

and the adjusting module 67 is configured to adjust a position of the entire photolithography pattern where the PCM area in the photolithography pattern is located if at least two PCM areas do not exist in the alignment area, or adjust a drawing reference of the back mask layout, so that at least two PCM areas exist in the alignment area.

The above-described respective modules may be functional modules or program modules, and may be implemented by software or hardware. For modules implemented in hardware, the various modules described above may be located in the same processor; or the above modules may be located in different processors in any combination.

Example 3

As shown in fig. 9, the present embodiment is different from embodiment 1 in that after step S106 of embodiment 1: step S207 of the present embodiment: if yes, feeding back the drawn information of the front photomask layout and the back mask layout meeting the design requirements.

Example 4

As shown in fig. 10, the difference between the present embodiment and embodiment 2 is that after the judging module of embodiment 2: the present embodiment further includes: and a feedback module 68, configured to feedback information that the drawn front mask layout and the back mask layout meet design requirements if at least two PCM regions exist in the alignment area.

The foregoing description of the preferred embodiments of the application is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the application.

Claims

1. The method for verifying the layout of the front photomask and the back mask of the wafer is characterized by comprising the following steps of:

2. The method according to claim 1, wherein the front mask layout uses CAD software to form a photolithography pattern in the front mask layout with a center point of a boundary line of a region of the wafer to be laid as a starting point in the X-axis direction, and with the predetermined requirement as a rectangular area.

3. The method of claim 2, wherein the PCM region is located at an edge of the sub-region, and the PCM region has an area smaller than an area of the pure die region.

4. The method for verifying the layout of the front mask and the back mask of the wafer as set forth in claim 3, wherein the adjusting the position of the entire photolithography pattern where the PCM area in the photolithography pattern is located is specifically performed by using CAD software to adjust the PCM area in the photolithography pattern along the X-axis or Y-axis direction, and an updated front mask layout is formed based on the adjusted photolithography pattern.

5. The method for verifying the layout of the front mask and the back mask of the wafer according to claim 1, wherein the drawing reference for adjusting the layout of the back mask is specifically adjusted along the X-axis or Y-axis direction by CAD software, and an updated layout of the back mask is formed based on the adjusted drawing reference.

6. The method of claim 1, wherein the pure chip region and the PCM region do not overlap each other and are distributed throughout the front side mask layout.

7. The method of claim 1, wherein the same lithography parameters are set for the pure chip area and the PCM area during the wafer lithography process to achieve PCM monitoring representative of chip performance parameters.

8. A wafer front-side photomask and back-side mask layout verification system is characterized by comprising: