CN116488434A - Buck-boost converter and control circuit thereof - Google Patents
Buck-boost converter and control circuit thereof Download PDFInfo
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- CN116488434A CN116488434A CN202310281340.5A CN202310281340A CN116488434A CN 116488434 A CN116488434 A CN 116488434A CN 202310281340 A CN202310281340 A CN 202310281340A CN 116488434 A CN116488434 A CN 116488434A
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- 230000006641 stabilisation Effects 0.000 abstract description 5
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- 238000010586 diagram Methods 0.000 description 25
- 238000000034 method Methods 0.000 description 9
- 239000003990 capacitor Substances 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 230000009471 action Effects 0.000 description 3
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- 230000007423 decrease Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0038—Circuits or arrangements for suppressing, e.g. by masking incorrect turn-on or turn-off signals, e.g. due to current spikes in current mode control
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/157—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
- H02M3/1582—Buck-boost converters
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The invention discloses a buck-boost converter and a control circuit thereof. The loop control circuit is used for generating a loop control signal for controlling output voltage stabilization, the reference voltage generating circuit is used for generating a reference voltage according to input voltage and output voltage, the mode switching circuit is used for comparing the loop control signal with the reference voltage and providing the loop control signal or the reference voltage to the PWM/PFM controller according to a comparison result, and the PWM/PFM controller compares a received signal with a slope signal and controls the buck-boost converter to work in a normal working mode or a light load working mode according to the comparison result. By binding the information of the input voltage and the output voltage in the reference voltage, fluctuation in slope compensation when the input voltage and the output voltage change is compensated, so that fluctuation of load current when the system is switched in a mode is reduced, and the stability of the system is improved.
Description
Technical Field
The invention relates to the technical field of electronic circuits, in particular to a buck-boost converter and a control circuit thereof.
Background
Modern portable electronic devices are often provided with a power source, such as a battery, which serves as the Direct Current (DC) for the various electronic components within the device. However, typically these components will have different voltage requirements, and so such devices typically employ one or more voltage converters that reduce the nominal voltage associated with the power supply to a voltage suitable for the different electronic components.
Existing DC/DC converters with wide input voltages include cascaded buck-boost converters, H-bridge buck-boost converters, kuke converters, SEPIC (Single Enable Primary Inductance Converter, single ended primary inductor converters) and the like. Wherein the H-bridge buck-boost converter (single inductor or non-inverting buck-boost converter) has good performance.
Fig. 1 shows a schematic circuit diagram of a conventional buck-boost converter. As shown in fig. 1, the buck-boost converter converts an input voltage Vin to an output voltage Vout, and includes power switches Q1 to Q4, an inductor L, an output capacitor Cout, and a control circuit 100. When the power switches Q1, Q3 are on and the power switches Q2, Q4 are off, the inductor L stores energy. When the power switches Q1, Q3 are off and the power switches Q2, Q4 are on, the energy stored by the inductor L is provided to the load.
The control circuit 100 is used to control the power switches Q1 to Q4 to be turned on and off, so as to control the inductor L to output energy in discontinuous pulses. In order to improve the operating efficiency of the buck-boost converter, the conventional control circuit 100 has two modes of operation, a normal mode of operation and a light load mode of operation. Specifically, the normal operation mode is a pulse width modulation (Pulse Width Modulation, PWM) operation mode, and the light load operation mode is a pulse frequency modulation (Pulse Frequency Modulation, PFM) operation mode. The control circuit 100 includes a loop control circuit 101, a mode switching circuit 102, a buck comparator 103, a boost comparator 104, and a logic and drive circuit 105. The loop Control circuit 101 is configured to generate a Voltage loop Control signal (Voltage Control) Vc according to the output Voltage Vout of the buck-boost converter, where the loop Control signal Vc is a variable Voltage signal that is used to Control the stabilization of the output Voltage Vout. The signal Vc output from the loop control circuit 101 is supplied to the mode switching circuit 102, and the mode switching circuit 102 divides the signal Vc into two signals, namely, a boost loop control signal vc_boost and a buck loop control signal vc_buck. The mode switching circuit 102 compares the buck loop control signal vc_buck with the first reference voltage Vref1, and compares the boost loop control signal vc_boost with the second reference voltage Vref2, and controls whether the buck-boost converter operates in the PWM operation mode or the PFM operation mode according to the comparison result.
For example, when the input voltage Vin is far greater than the output voltage Vout, the BUCK-boost converter operates in a BUCK period (BUCK period), and when the BUCK loop control signal vc_buck is greater than the first reference voltage Vref1, the mode switching circuit 102 provides the BUCK loop control signal to the positive input terminal of the BUCK comparator 103, and when the BUCK-boost converter operates in the PWM operation mode, the BUCK comparator 103 generates the BUCK duty ratio information BK according to the intersection between the BUCK loop control signal and the BUCK ramp (BUCK ramp) in the BUCK period; when the BUCK loop control signal is smaller than the first reference voltage Vref1, the mode switching circuit 102 provides the first reference voltage Vref1 to the positive input terminal of the BUCK comparator 103, and at this time, the BUCK comparator 103 generates the BUCK duty ratio information BK according to the intersection between the first reference voltage Vref1 and the BUCK slope when the BUCK converter operates in the PFM operation mode.
When the input voltage Vin is far smaller than the output voltage Vout, the buck-BOOST converter operates in a BOOST period (BOOST period), and when the BOOST loop control signal is greater than the second reference voltage Vref2, the mode switching circuit 102 provides the BOOST loop control signal to the positive input terminal of the BOOST comparator 104, and the BOOST comparator 104 generates BOOST duty cycle information BST according to the intersection between the BOOST loop control signal and a BOOST ramp (BOOST ramp) in the BOOST period; when the BOOST loop control signal is smaller than the second reference voltage Vref2, the mode switching circuit 102 provides the second reference voltage Vref2 to the positive input terminal of the BOOST comparator 104, and at this time, the BOOST comparator 104 generates the BOOST duty ratio information BST according to the intersection between the second reference voltage Vref2 and the BOOST ramp when the BOOST converter operates in the PFM operation mode.
When the input voltage Vin is close to the output voltage Vout, the BUCK-BOOST converter operates in a BUCK-BOOST period (BUCK-BOOST period), and the system alternately switches between the PWM operation mode and the PFM operation mode.
For the BUCK period, the load current when the system is ready to enter PFM mode of operation is equal to half the inductor peak current, i.e., iout=0.5×ipeak, which can be expressed by the following equation: ipeak ri=vref 1-Vslope, where Ri is the ratio of current samples, vslope is the harmonic compensation signal, which is related to the input voltage Vin and the output voltage Vout of the system.
For the BOOST period, the system is ready to enter PFM mode of operation with load current iout=0.5×ipeak (1-D), and ipeak×ri=vref 2-Vslope, where D represents the switching duty cycle.
As can be seen from the above description, in the conventional buck-boost converter, the first reference voltages Vref1 and Vref2 are fixed values, and the harmonic compensation signal is related to the input voltage Vin and the output voltage Vout of the system, so that the load current of the circuit of the conventional buck-boost converter fluctuates greatly when the system enters the PFM operation mode under the condition that the input voltage Vin and the output voltage Vout fluctuate, and the stability of the system is reduced.
Disclosure of Invention
In view of the above, the present invention aims to provide a buck-boost converter and a control circuit thereof, which solve the problem that when the input voltage and the output voltage of the circuit change, the fluctuation of the load current of the circuit changes greatly when the system enters the PFM operation mode.
According to an aspect of an embodiment of the present invention, there is provided a control circuit for a buck-boost converter, including a loop control circuit, a reference voltage generating circuit, a mode switching circuit, and a PWM/PFM controller, wherein the loop control circuit is configured to generate a loop control signal according to an output voltage of the buck-boost converter; the reference voltage generation circuit is used for generating a reference voltage; the mode switching circuit is used for comparing the loop control signal with the reference voltage and providing the loop control signal or the reference voltage to the PWM/PFM controller according to a comparison result; the PWM/PFM controller is used for comparing the loop control signal or the reference voltage with a slope signal so as to control the buck-boost converter to work in a normal working mode or a light-load working mode, wherein the reference voltage is related to the input voltage and the output voltage of the buck-boost converter.
Optionally, the mode switching circuit is configured to provide the loop control signal to the PWM/PFM controller to control the buck-boost converter to operate in the normal operation mode when the loop control signal is greater than the reference voltage; and when the loop control signal is smaller than the reference voltage, providing the reference voltage to the PWM/PFM controller so as to control the buck-boost converter to work in the light load working mode.
Optionally, the reference voltage includes a first reference voltage and a second reference voltage, when the buck-boost converter works in a buck period, the mode switching circuit compares a buck loop control signal with the first reference voltage, and provides the buck loop control signal or the first reference voltage to the PWM/PFM controller according to a comparison result; when the buck-boost converter works in a boost period, the mode switching circuit compares a boost loop control signal with the second reference voltage, and provides the boost loop control signal or the second reference voltage to the PWM/PFM controller according to a comparison result.
Optionally, when the input voltage is smaller than the output voltage, the first reference voltage is equal to a fixed first voltage value, the second reference voltage is positively correlated with a difference between the output voltage and the input voltage, and when the input voltage is larger than the output voltage, the first reference voltage is negatively correlated with a difference between the input voltage and the output voltage, and the second reference voltage is equal to a fixed second voltage value.
Optionally, the reference voltage generating circuit includes a first reference voltage generating module and a second reference voltage generating module, and the first reference voltage generating module includes: a first transistor and a first current source connected in series between the output voltage and ground, the control terminal and the second terminal of the first transistor being shorted together; a first resistor, a second transistor and a third transistor connected in series between the input voltage and ground, a control terminal of the second transistor being connected to a control terminal of the first transistor; the positive input end of the first operational amplifier is used for receiving a first voltage signal, the first voltage signal has the first voltage value, and the negative input end of the first operational amplifier is connected with the output end; and a second resistor and a fourth transistor connected in series between an output terminal of the first operational amplifier and ground, a control terminal of the fourth transistor being connected to a control terminal and a first terminal of the third transistor to constitute a current mirror, a common connection node of the second resistor and the fourth transistor being used for outputting the first reference voltage, the second reference voltage generating module comprising: a fifth transistor and a second current source connected in series between the input voltage and ground, the control terminal and the second terminal of the fifth transistor being shorted together; the positive input end of the second operational amplifier is used for receiving a second voltage signal, the second voltage signal has the second voltage value, and the negative input end of the second operational amplifier is connected with the output end; and a third resistor, a sixth transistor and a fourth resistor connected in series between the output voltage and the output terminal of the second operational amplifier, wherein the control terminal of the sixth transistor is connected with the control terminal of the fifth transistor, and a common connection node of the sixth transistor and the fourth resistor is used for outputting the second reference voltage.
Optionally, the mode switching circuit includes: a first switch having a first input for receiving the first reference voltage, a second input for receiving the buck loop control signal, and an output for providing a first output signal selected from one of the buck loop control signal and the first reference voltage; a second switch having a first input for receiving the second reference voltage, a second input for receiving the boost loop control signal, and an output for providing a second output signal selected from one of the boost loop control signal and the second reference voltage; the first comparator is used for comparing the first reference voltage with the step-down loop control signal and controlling the switching of the first switch according to a comparison result; and a second comparator for comparing the second reference voltage with the boost loop control signal and controlling the switching of the second switch according to the comparison result.
Optionally, the PWM/PFM controller includes: a third comparator for comparing the buck loop control signal or the first reference voltage with the ramp signal to generate a first control signal; a fourth comparator for comparing the boost loop control signal or the second reference voltage with the ramp signal to generate a second control signal; a fifth comparator for comparing the loop control signal with a third reference voltage to generate an enable signal; the AND gate circuit is used for performing AND logic operation on the enabling signal and a clock signal to generate a third control signal; and the logic and driving module is used for generating a plurality of switch driving signals for controlling the working states of a plurality of power switches in the buck-boost converter according to the first control signal, the second control signal and the third control signal.
Optionally, when the buck-boost converter is operated in the normal operation mode, the third control signal is set to an inactive state, the first control signal is used to control a duty cycle of a high-voltage side power switch of a buck converter portion of the buck-boost converter during a buck period, the second control signal is used to control a duty cycle of a low-voltage side power switch of a boost converter portion of the buck-boost converter during a boost period, and when the buck-boost converter is operated in the light-load operation mode, the third control signal is used to apply a driving signal of the high-voltage side power switch of the buck converter portion and an on edge of a driving signal of the low-voltage side power switch of the boost converter portion, the first control signal is used to control an off edge of the driving signal applied to the high-voltage side power switch of the buck converter portion, and the second control signal is used to control an off edge of the driving signal applied to the low-voltage side power switch of the boost converter portion.
Optionally, the ramp signal is related to or simulates an inductor current of the buck-boost converter, and the control circuit further includes a ramp generating circuit, including: a current sampling module for sampling a current flowing through an inductor of the buck-boost converter to generate a current sampling signal; and the adder module is used for overlapping the current sampling signal and the harmonic compensation signal to obtain the ramp signal.
According to another aspect of an embodiment of the present invention, there is provided a buck-boost converter including: a buck converter section including a first high side power switch and a first low side power switch connected in series between an input voltage and ground; a boost converter section including a second high-side power switch and a second low-side power switch connected in series between the output voltage and ground; an inductor connected between a common node of the first high side power switch and the first low side power switch and a common node of the second high side power switch and the second low side power switch; and the control circuit.
The buck-boost converter and the control circuit thereof in the embodiment of the invention comprise a loop control circuit, a reference voltage generation circuit, a mode switching circuit and a PWM/PFM controller. The loop control circuit is used for generating a loop control signal for controlling output voltage stabilization, the reference voltage generating circuit is used for generating a reference voltage according to input voltage and output voltage, the mode switching circuit is used for comparing the loop control signal with the reference voltage and providing the loop control signal or the reference voltage to the PWM/PFM controller according to a comparison result, and the PWM/PFM controller compares the loop control signal or the reference voltage with a slope signal and controls the buck-boost converter to work in a PWM working mode or a PFM working mode according to the comparison result. According to the embodiment, the information of the input voltage and the output voltage is bound in the reference voltage, so that fluctuation in slope compensation when the input voltage and the output voltage change can be well compensated, fluctuation of load current of the system when the buck-boost converter enters the PFM from the PWM working mode is reduced, and stability of the system is improved.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings.
Fig. 1 shows a schematic circuit diagram of a conventional buck-boost converter.
Fig. 2 shows a schematic circuit diagram of a buck-boost converter according to an embodiment of the invention.
Fig. 3 shows a schematic circuit diagram of a loop control circuit in a buck-boost converter according to an embodiment of the invention.
Fig. 4 shows a schematic circuit diagram of a mode switching circuit in a buck-boost converter according to an embodiment of the invention.
Fig. 5 shows a schematic circuit diagram of a PWM/PFM controller in a buck-boost converter according to an embodiment of the present invention.
Fig. 6 shows a schematic circuit diagram of a ramp generation circuit in a buck-boost converter according to an embodiment of the invention.
Fig. 7 shows a schematic circuit diagram of a first reference voltage generation module in a buck-boost converter according to an embodiment of the invention.
Fig. 8 shows a waveform diagram of a first reference voltage according to an embodiment of the present invention according to an input voltage and an output voltage.
Fig. 9 shows a schematic circuit diagram of a second reference voltage generation module in a buck-boost converter according to an embodiment of the invention.
Fig. 10 shows a waveform diagram of a second reference voltage according to an embodiment of the present invention according to an input voltage and an output voltage.
Fig. 11 shows an operation waveform diagram of the BUCK-boost converter according to the embodiment of the present invention in the PFM operation mode in the BUCK period.
Fig. 12 shows waveforms of operation of the buck-BOOST converter in PFM operation mode in BOOST period according to an embodiment of the present invention.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements are denoted by like reference numerals throughout the various figures. For clarity, the various features of the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown in the drawings.
Numerous specific details of the invention, such as construction, materials, dimensions, processing techniques and technologies, may be set forth in the following description in order to provide a thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
It should be understood that in the following description, "circuit" refers to an electrically conductive loop formed by at least one element or sub-circuit through electrical or electromagnetic connection. When an element or circuit is referred to as being "connected to" another element or being "connected between" two nodes, it can be directly coupled or connected to the other element or intervening elements may be present, the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled to" or "directly connected to" another element, it means that there are no intervening elements present between the two. In addition, the transistors present in pairs according to the invention are matched transistors, the dimensions and/or types being identical, unless otherwise specified.
In the context of the present invention, a transistor blocks current and/or does not substantially conduct current when the transistor is in an "off (off) state" or "off". Conversely, when the transistor is never in an "on (on) state" or "conducting", the transistor is able to conduct current significantly. For example, in one embodiment, the high voltage transistor comprises an N-channel metal oxide semiconductor (NMOS) Field Effect Transistor (FET), wherein the high voltage is provided between a first terminal (i.e., drain) and a second terminal (i.e., source) of the transistor. In some embodiments, an integrated controller circuit may be used to drive the power switch when regulating the energy provided to the load. In addition, for purposes of this disclosure, "ground" or "ground potential" in this disclosure refers to a reference voltage or potential with respect to which all other voltages or potentials of an electronic circuit or Integrated Circuit (IC) are defined or measured.
Fig. 2 shows a schematic circuit diagram of a buck-boost converter according to an embodiment of the invention. The buck-boost converter of the present embodiment includes a control circuit 200 and an external power circuit. Wherein the power circuit includes one or more switch and filter elements (e.g., inductors, capacitors, etc.) configured to regulate the transfer of electrical energy from the input to the output of the switching converter in response to one or more switch drive signals from the controller 300. In some embodiments, one or more switches in the power circuit are integrated with the controller 210 to form an integrated circuit chip.
As shown in fig. 2, the power circuit includes power switches Q1 to Q4, an inductor L, and an output capacitor Cout. The power switch Q1 has a first terminal coupled to the input voltage Vin, a second terminal and a control terminal. The power switch Q2 has a first terminal coupled to the second terminal of the power switch Q1, a second terminal coupled to the reference ground, and a control terminal. The inductor L has a first terminal and a second terminal, the common terminal of the power switches Q1 and Q2 forming a first switching node SW1, the first terminal of the inductor L being coupled to the first switching node SW 1. The power switch Q3 has a first terminal, a second terminal and a control terminal, the second terminal of which is connected to the reference ground. The power switch Q4 has a first terminal coupled to the first terminal of the power switch Q3, a second terminal coupled to the output voltage Vout, and a control terminal. The output capacitor Cout is coupled between the second terminal of the power switch Q4 and ground. The common terminal of the power switch Q3 and the power switch Q4 forms a second switch node SW2, and the second terminal of the inductor L is coupled to the second switch node SW 2. In some embodiments, the power switches Q1-Q4 may be any controllable semiconductor switching device, such as Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), insulated Gate Bipolar Transistors (IGBTs), or the like. The power switches Q1 and Q2 are high side power MOSFETs and low side MOSFETs, respectively, of the buck converter portion of the buck-boost converter; the power switches Q4 and Q3 are high side power MOSFETs and low side MOSFETs, respectively, of the boost converter portion of the buck-boost converter. The control circuit 200 is used to control the on and off of the switching elements Q1 to Q4 to control the inductor L to output energy in discrete pulses.
The buck-boost converter of this embodiment has two modes of operation, a normal mode of operation and a light load mode of operation. Specifically, the normal operation mode is a pulse width modulation (Pulse Width Modulation, PWM) operation mode, and the light load operation mode is a pulse frequency modulation (Pulse Frequency Modulation, PFM) operation mode. When the BUCK-boost converter works in the PWM working mode, the input voltage Vin is far greater than the output voltage Vout, and the BUCK-boost converter works in a BUCK period (BUCK period); the input voltage Vin is far smaller than the output voltage Vout, and the buck-BOOST converter works in a BOOST period (BOOST period); when the input voltage Vin approaches the output voltage Vout, the BUCK-BOOST converter operates in a BUCK-BOOST period (BUCK-BOOST period), and the BOOST period and the BUCK period alternately operate.
As shown in fig. 2, the control circuit 200 of the buck-boost converter of the present embodiment includes a loop control circuit 201, a reference voltage generation circuit 202, a mode switching circuit 203, and a PWM/PFM controller 204. The loop control circuit 201 generates the loop control signal Vc based on the output voltage Vout, and the loop control signal is a variable voltage signal for controlling the stabilization of the output voltage Vout. The reference voltage generating circuit 202 is configured to generate a reference voltage Vref according to an input voltage Vin and the output voltage Vout. The loop control signal Vc is provided to the mode switching circuit 203, the mode switching circuit 203 is configured to compare the loop control signal Vc with the reference voltage Vref, and provide the loop control signal Vc or the reference voltage Vref to the PWM/PFM controller 204 according to the comparison result, and the PWM/PFM controller 204 compares the loop control signal Vc or the reference voltage Vref with a ramp signal Vramp, and controls the buck-boost converter to operate in the PWM operation mode or the PFM operation mode according to the comparison result. For example, when the loop control signal Vc is greater than the reference voltage Vref, the mode switching circuit 203 provides the loop control signal Vc to the PWM/PFM controller 204, the system operates in the PWM operation mode, and the PWM/PFM controller 204 generates the BUCK and/or BOOST duty cycle in the BUCK-BOOST converter according to the intersection of the loop control signal Vc and the ramp signal Vramp; when the loop control signal Vc is smaller than the reference voltage Vref, the mode switching circuit 203 provides the reference voltage Vref to the PWM/PFM controller 204, and the PWM/PFM controller 204 generates a BUCK and/or BOOST duty cycle in the BUCK-BOOST converter according to the intersection of the reference voltage Vref and the ramp signal Vramp.
In an exemplary embodiment, the ramp signal Vramp is a ramp signal that emulates the electrical characteristics of the inductor current IL of the buck-boost converter (e.g., without limitation, the slope, transition point or phase, etc. of the inductor current IL). In addition, the reference voltage Vref is related to the input voltage Vin and the output voltage Vout of the buck-boost converter. The generation manner of the ramp signal Vramp and the reference voltage Vref will be described in detail below.
In accordance with the teachings of the present embodiments, buck-boost converters may operate and transition over multiple cycles including, but not limited to, buck, boost, and buck-boost cycles. The mode switching circuit 203 is configured to divide the received loop control signal Vc into two signals, namely, a boost loop control signal vc_boost and a buck loop control signal vc_buck, and the reference voltage generating circuit 202 is configured to generate two reference voltages, namely, a first reference voltage Vref1 and a second reference voltage Vref2. When the input voltage Vin is far greater than the output voltage Vout, the BUCK-boost converter operates in a BUCK period, the mode switching circuit 203 compares the BUCK loop control signal vc_buck with the first reference voltage Vref1, and when the BUCK loop control signal vc_buck is greater than the first reference voltage Vref1, the mode switching circuit 203 provides the BUCK loop control signal vc_buck to the PWM/PFM controller 204, and the PWM/PFM controller 204 generates duty ratio information (i.e., BUCK duty ratio information) of the BUCK converter portion in the BUCK-boost converter according to the intersection between the BUCK loop control signal vc_buck and the ramp signal Vramp; when the buck loop control signal vc_buck is smaller than the first reference voltage Vref1, the mode switching circuit 203 provides the first reference voltage Vref1 to the PWM/PFM controller 204, and the PWM/PFM controller 204 generates the buck duty ratio information according to the first reference voltage Vref1 and the ramp signal Vramp. When the input voltage Vin is far smaller than the output voltage Vout, the buck-BOOST converter operates in a BOOST period, the mode switching circuit 203 compares the BOOST loop control signal vc_boost with the second reference voltage Vref2, and when the BOOST loop control signal vc_boost is greater than the second reference voltage Vref2, the mode switching circuit 203 provides the BOOST loop control signal vc_boost to the PWM/PFM controller 204, and the PWM/PFM controller 204 generates duty ratio information (i.e., BOOST duty ratio information) of the BOOST converter portion of the buck-BOOST converter according to an intersection between the BOOST loop control signal vc_boost and the ramp signal Vramp; when the boost loop control signal vc_boost is smaller than the second reference voltage Vref2, the mode switching circuit 203 provides the second reference voltage Vref2 to the PWM/PFM controller 204, and the PWM/PFM controller 204 generates the boost duty ratio information according to the second reference voltage Vref2 and the ramp signal Vramp. When the input voltage Vin is close to the output voltage Vout, the BUCK-BOOST converter operates in a BUCK-BOOST period (BUCK-BOOST period), and the system alternately switches between the PWM operation mode and the PFM operation mode.
As described above, the first reference voltages Vref1 and Vref2 of the present embodiment are both related to the input voltage Vin and the output voltage Vout of the buck-boost converter. In addition, when the BUCK-boost converter operates in the BUCK period, the first reference voltage Vref1 is inversely related to the difference between the input voltage Vin and the output voltage Vout, i.e., the larger the difference between the input voltage Vin and the output voltage Vout is, the smaller the first reference voltage Vref1 is. When the buck-BOOST converter operates in the BOOST period, the second reference voltage Vref2 is positively correlated with the difference between the input voltage Vin and the output voltage Vout, i.e., the larger the difference between the output voltage Vout and the input voltage Vin, the larger the second reference voltage Vref 2.
Moreover, as can be seen from the foregoing description, when the buck-boost converter enters the PFM operation mode from the PWM operation mode, the load current of the system is related to the peak current of the inductance, and the peak current of the inductance is related to the first reference voltage Vref1 and the slope compensation of the system, and the slope compensation fluctuates with the change of the input voltage Vin and the output voltage Vout of the system.
Fig. 3 shows a schematic circuit diagram of a loop control circuit in a buck-boost converter according to an embodiment of the invention. As shown in fig. 3, the loop control circuit 201 includes an error amplifier 211, where the error amplifier 211 has a positive input terminal, a negative input terminal, and an output terminal, and the positive input terminal receives a feedback signal Vfb of the output voltage Vout due to receiving a reference voltage Vbg, and the negative input terminal receives the feedback signal Vfb of the output voltage Vout, and by way of example, a resistor voltage dividing network formed by voltage dividing resistors Ra and Rb, where the voltage dividing resistors Ra and Rb are connected in series between the output voltage Vout and a reference ground, and the feedback signal Vfb is generated at a common node of the two and is connected to the negative input terminal of the error amplifier 211, and the error amplifier 211 is configured to compare the feedback signal Vfb with the reference voltage Vbg, and generate the loop control signal Vc at the output terminal.
Typically, a compensation network 212 consisting of a resistor and a capacitor is also provided between the output of the error amplifier 211 and the reference ground. In addition, although the embodiment shown in FIG. 3 employs error amplifier 211, those skilled in the art will recognize that other suitable analog or digital circuits are equally suitable as long as the error amplification function is achieved.
Fig. 4 shows a schematic circuit diagram of a mode switching circuit in a buck-boost converter according to an embodiment of the invention. As shown in fig. 4, the mode switching circuit 203 of the present embodiment includes a comparator 231, a comparator 232, a voltage source 233, and switches S1 and S2. The switches S1 and S2 are, for example, single-pole double-throw analog switches (also referred to as single-pole double-throw switches), and each has two input terminals and one output terminal, as shown in fig. 4, one input terminal 301 of the switch S1 is connected to the first reference voltage Vref1, the other input terminal 302 is connected to the step-down loop control signal vc_buck, which is the same as the loop control signal Vc, and the output terminal thereof is used for outputting the signal Va. One input terminal 304 of the switch S2 is connected to the boost loop control signal vc_boost, and by way of example, the loop control signal Vc is connected to the voltage source 233, the voltage source 233 obtains the boost loop control signal vc_boost by appropriately shifting the loop control signal Vc, and the other input terminal 305 of the switch S2 is connected to the second reference voltage Vref2, and the output terminal of the switch S2 is used for outputting the signal Vb. The comparator 231 has a positive input terminal for receiving the first reference voltage Vref1, a negative input terminal for receiving the buck loop control signal vc_buck, and an output terminal for controlling the switching of the switch S1. The comparator 232 has a positive input for receiving the second reference voltage Vref2, a negative input for receiving the boost loop control signal vc_boost, and an output for controlling the switching of the switch S2. For example, when the buck loop control signal vc_buck is greater than the first reference voltage Vref1, the comparator 231 connects the input terminal 302 and the output terminal 303 of the switch S1, and the signal Va is equal to the buck loop control signal vc_buck, and when the buck loop control signal vc_buck is less than the first reference voltage Vref1, the comparator 231 connects the input terminal 301 and the output terminal 303 of the switch S1, and the signal Va is equal to the first reference voltage Vref1. Similarly, when the boost loop control signal vc_boost is greater than the second reference voltage Vref2, the comparator 232 connects the input terminal 304 of the switch S2 with the output terminal 306, and the signal Vb is equal to the boost loop control signal vc_boost, and when the boost loop control signal vc_boost is less than the second reference voltage Vref2, the comparator 232 connects the input terminal 305 of the switch S2 with the output terminal 306, and the signal Vb is equal to the second reference voltage Vref2. In addition, while single pole double throw switches are used to illustrate switches S1 and S2 in FIG. 4, those skilled in the art will appreciate that discrete switches may be used to implement switches S1 and S2, as the invention is not limited in this regard.
Fig. 5 shows a schematic circuit diagram of a PWM/PFM controller in a buck-boost converter according to an embodiment of the present invention. As shown in fig. 5, the PWM/PFM controller 204 of the present embodiment includes comparators 241 to 243, an and gate 244, and a logic and driving module 245. The comparator 241 has a positive input terminal for receiving the signal Va, for example, the above-mentioned buck loop control signal vc_buck or the first reference voltage Vref1, a negative input terminal for receiving the ramp signal Vramp, and an output terminal, and the comparator 241 is for comparing the signal Va with the ramp signal Vramp and generating the control signal BK according to the comparison result. The comparator 242 has a positive input terminal, a negative input terminal and an output terminal, the positive input terminal is used for receiving the signal Vb, for example, the boost loop control signal vc_boost or the second reference voltage Vref2, and the comparator 242 is used for comparing the signal Vb with the ramp signal Vramp and generating the control signal BST according to the comparison result. The comparator 243 has a positive input terminal for receiving the loop control signal Vc, a negative input terminal for receiving the third reference voltage Vref3, and an output terminal, and the comparator 243 is for comparing the loop control signal Vc with the third reference voltage Vref3 and generating an enable signal PFM according to the comparison result. The and circuit 244 is configured to perform an and logic operation on the enable signal PFM and a clock signal CLK to generate a control signal SET, wherein the clock signal CLK provides an internal clock for the circuit to switch timing (e.g., by generating a plurality of narrow pulses at constant frequency, adjacent pulses defining a clock cycle). The logic circuit 245 is used for realizing a logic control function of the system, and processes logic signals (such as signals BK, BST, and SET) of each module for controlling the operation states of the switching elements Q1 to Q4, and generates switching drive signals DRV1 to DRV4 to be supplied to the switching elements Q1 to Q4.
As described above, the BUCK-BOOST converter of the present embodiment may operate in the PWM operation mode or the PFM operation mode, when the BUCK-BOOST converter operates in the PWM operation mode, the loop control signal Vc is smaller than the third reference voltage Vref3, the enable signal PFM is SET in an inactive state (e.g., logic low level), and the control signal SET is also SET in an inactive state of low level, and the comparators 241 and 242 respectively compare the BUCK loop control signal vc_buck with the ramp signal Vramp (in the BUCK period) and the BOOST loop control signal vc_boost with the ramp signal Vramp (in the BOOST period), and generate the control signal BK or BST according to the intersection of the two, wherein the control signal BK is used to define the duty ratio of the high-side power switch of the BUCK converter portion in the BUCK period, and the control signal BST is used to define the duty ratio of the low-side power switch of the BOOST converter portion in the BOOST period. When the buck-boost converter operates in the PFM operation mode, the loop control signal Vc is greater than the third reference voltage Vref3, the enable signal PFM is SET to an active state of a logic high level, at which time the control signal SET is also SET to an active state of a logic high level, at which time the control signal SET is used to determine an on edge of a drive signal of a high-side power switch of a buck converter section and a drive signal of a low-side power switch of a boost converter section applied in the buck-boost converter, the control signal BK generated by the comparator 241 is used to determine an off edge of the drive signal applied to the high-side power switch of the buck converter section, and the control signal BST generated by the comparator 242 is used to determine an off edge of the drive signal applied to the low-side power switch of the boost converter section.
Fig. 6 shows a schematic circuit diagram of a ramp generation circuit in a buck-boost converter according to an embodiment of the invention. In some exemplary implementations, the control circuit 200 of the buck-boost converter according to the embodiments of the present invention further includes a ramp generating circuit 205, where the ramp generating circuit 205 is configured to generate the ramp signal Vramp. Illustratively, the ramp generation circuit 205 includes a current sampling module 251, an adder module 252, and a harmonic compensation module 252. Wherein the current sampling module samples the current flowing through the inductor L to generate a current sampling signal Isense. The above-described sampling may be implemented by a sampling resistor, a current transformer, a current mirror, or the like, and the current sampling mok251 may also estimate the current flowing through the inductor L by sampling the current flowing through each switching element (e.g., the power switch Q1) and acquire a current sampling signal Isense. The adder block 252 is configured to add the harmonic compensation signal VSLOPE provided by the harmonic compensation block 252 and the current sampling signal Isense to obtain the ramp signal Vramp.
In an exemplary embodiment, the reference voltage generating circuit 202 includes a first reference voltage generating module 221 for generating the first reference voltage Vref1 and a second reference voltage generating module 222 for generating the second reference voltage Vref 2.
As an exemplary implementation, fig. 7 shows a schematic circuit diagram of the first reference voltage generation module 221 in the buck-boost converter according to an embodiment of the present invention, and fig. 8 shows a waveform diagram of the first reference voltage Vref1 according to an embodiment of the present invention as a function of the input voltage Vin and the output voltage Vout. As shown in fig. 7, the first reference voltage generating module 221 includes PMOS transistors MP0 and MP1, NMOS transistors MN0 and MN1, a current source I1, resistors R1 and R2, and an operational amplifier 2201. The source of the PMOS transistor MP0 is connected to the output voltage Vout, the gate and the drain of the PMOS transistor MP0 are shorted to each other, the drain of the PMOS transistor MP0 is further connected to one end of the current source I1, and the other end of the current source I1 is grounded. The first end of the resistor R1 is connected with the input voltage Vin, the second end is connected with the source electrode of the PMOS transistor MP1, the grid electrode of the PMOS transistor MP1 is connected with the grid electrode of the PMOS transistor MP0, the drain electrode of the PMOS transistor MP1 is connected with the drain electrode and the grid electrode of the NMOS transistor MN1, and the source electrode of the NMOS transistor MN1 is grounded. The positive input end of the operational amplifier 2201 is used for receiving a first voltage signal V1, the negative input end and the output end of the operational amplifier 2201 are connected together, the first end of the resistor R2 is connected with the output end of the operational amplifier 2201, the second end of the resistor R2 is connected with the drain electrode of the NMOS transistor MN0, the gate electrode of the NMOS transistor MN0 is connected with the gate electrode of the NMOS transistor MN1, the source electrode of the NMOS transistor MN0 is grounded, and the common connection node of the resistor R2 and the NMOS transistor MN0 is used for outputting the first reference voltage Vref1. The NMOS transistors MN1 and MN0 form a current mirror structure, and the first voltage signal V1 has a fixed voltage value.
In this embodiment, the ratio between the PMOS transistors MP0 and MP1 is set to 1:k, where k is an integer greater than 0, and the current mirror ratio between the NMOS transistors MN0 and MN1 is set to 1:1, so that the expression of the first reference voltage Vref1 can be obtained as follows:
when the input voltage Vin is smaller than the output voltage Vout, the first reference voltage Vref1 is equal to the first voltage signal V1 and is a fixed voltage value; as can be seen from the above equation, when the input voltage Vin is greater than the output voltage Vout, the first reference voltage Vref1 is inversely related to the difference between the input voltage Vin and the output voltage Vout, i.e., when the difference between the input voltage Vin and the output voltage Vout gradually increases, the first reference voltage Vref1 gradually decreases, and the waveform diagram thereof is shown in fig. 8.
As an exemplary implementation, fig. 9 shows a schematic circuit diagram of the second reference voltage generation module 222 in the buck-boost converter according to an embodiment of the present invention, and fig. 10 shows a waveform diagram of the second reference voltage Vref2 according to an embodiment of the present invention as a function of the input voltage Vin and the output voltage Vout. As shown in fig. 9, the second reference voltage generation module 222 includes PMOS transistors MP2 and MP3, a current source I2, resistors R3 and R4, and an operational amplifier 2202. The source of the PMOS transistor MP2 is connected to the input voltage Vin, the gate and the drain of the PMOS transistor MP2 are shorted to each other, the drain of the PMOS transistor MP2 is also connected to one end of the current source I2, and the other end of the current source I2 is grounded. The first end of the resistor R3 is connected to the output voltage Vout, the second end is connected to the source of the PMOS transistor MP3, the gate of the PMOS transistor MP3 is connected to the gate of the PMOS transistor MP2, the drain of the PMOS transistor MP3 is connected to the first end of the resistor R4, the second end of the resistor R4 is connected to the output end of the operational amplifier 2202, the positive input end of the operational amplifier 2202 is used for receiving a second voltage signal V2, the negative input end and the output end of the operational amplifier 2202 are connected together, and the common connection node of the resistor R4 and the PMOS transistor MP3 is used for outputting the second reference voltage Vref2. The second voltage signal V2 has a fixed voltage value.
In this embodiment, the ratio between the PMOS transistors MP2 and MP3 is 1:k, where k is an integer greater than 0, and the expression for obtaining the second reference voltage Vref2 is:
when the input voltage Vin is greater than the output voltage Vout, the second reference voltage Vref2 is equal to the second voltage signal V2, and is a fixed voltage value; as can be seen from the above equation, when the input voltage Vin is smaller than the output voltage Vout, the second reference voltage Vref2 is positively correlated with the difference between the output voltage Vout and the input voltage Vin, that is, when the difference between the output voltage Vout and the input voltage Vin becomes larger, the second reference voltage Vref 1=2 becomes larger, and the waveform diagram thereof is shown in fig. 10.
Fig. 11 shows an operation waveform diagram of the BUCK-BOOST converter according to the embodiment of the present invention in the PFM operation mode in the BUCK period, and fig. 12 shows an operation waveform diagram of the BUCK-BOOST converter according to the embodiment of the present invention in the PFM operation mode in the BOOST period. The operation principle of the buck-boost converter of the present embodiment in the PFM operation mode is described below with reference to fig. 11, where K represents the voltage division coefficient of the voltage dividing resistor network, vout represents the output voltage of the buck-boost converter, IL represents the inductor current waveform in the inductor L, PFM represents the enable signal output by the comparator 243, Q1 and Q2 represent the driving signals of the high-voltage side power switch and the low-voltage side power switch of the buck-boost converter, respectively, and CLK represents the waveform of the clock signal.
At time t1, the enable signal PFM toggles to a logic high active state, the control signal SET is asserted, and the control signal SET follows the waveform change of the clock signal CLK, at time t2, a pulse of the clock signal CLK arrives, the high side power switch Q1 of the buck converter section is turned on, and the inductor current IL gradually increases. As the inductor current IL increases gradually, the ramp signal Vramp also increases gradually, and at time t3, the ramp signal Vramp reaches the first reference voltage Vref1, the control signal BK output by the comparator 241 turns over, the high-side power switch Q1 of the buck converter section turns off, and after a suitable delay, the low-side power switch Q2 is turned on, and as a result of the low-side power switch Q2 being turned on, the inductor current IL decreases gradually at times t3 to t 4. At time t4, another pulse of the clock signal CLK arrives, the low side power switch Q2 is turned off, and then another switching cycle begins and the circuit repeats the process of rising times t2 through t 4.
If the enable signal PFM is SET to a logic low state before the pulse of the clock signal CLK arrives, the control signal SET is SET to be inactive, i.e. it is no longer changed with the waveform of the clock signal CLK, for example, at time t5, the enable signal PFM is SET to a logic low level, after the inductor current IL drops to zero and the low-voltage side power switch Q2 is turned off, the high-voltage side power switch Q1 is turned on no longer following the pulse of the clock signal CLK, at which time both the high-voltage side power switch Q1 and the low-voltage side power switch Q2 in the circuit are turned off, and the low-power operation mode is achieved. The PFM operation mode of the BUCK-BOOST converter in the BOOST period is similar to the PFM operation mode in the BUCK period, and the difference is that the high-side power switch and the low-side power switch of the BOOST converter of the BUCK-BOOST converter are turned on and off, which is not described herein.
In summary, the buck-boost converter and the control circuit thereof according to the embodiments of the present invention include a loop control circuit, a reference voltage generating circuit, a mode switching circuit, and a PWM/PFM controller. The loop control circuit is used for generating a loop control signal for controlling output voltage stabilization, the reference voltage generating circuit is used for generating a reference voltage according to input voltage and output voltage, the mode switching circuit is used for comparing the loop control signal with the reference voltage and providing the loop control signal or the reference voltage to the PWM/PFM controller according to a comparison result, and the PWM/PFM controller compares the loop control signal or the reference voltage with a slope signal and controls the buck-boost converter to work in a PWM working mode or a PFM working mode according to the comparison result. According to the embodiment, the information of the input voltage and the output voltage is bound in the reference voltage, so that fluctuation in slope compensation when the input voltage and the output voltage change can be well compensated, fluctuation of load current of the system when the buck-boost converter enters the PFM from the PWM working mode is reduced, and stability of the system is improved.
It should be noted that in this document relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Embodiments in accordance with the present invention, as described above, are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and the full scope and equivalents thereof.
Claims (10)
1. A control circuit for a buck-boost converter includes a loop control circuit, a reference voltage generation circuit, a mode switching circuit, and a PWM/PFM controller, wherein,
the loop control circuit is used for generating a loop control signal according to the output voltage of the buck-boost converter;
the reference voltage generation circuit is used for generating a reference voltage;
the mode switching circuit is used for comparing the loop control signal with the reference voltage and providing the loop control signal or the reference voltage to the PWM/PFM controller according to a comparison result;
The PWM/PFM controller is used for comparing the loop control signal or the reference voltage with a slope signal so as to control the buck-boost converter to work in a normal working mode or a light load working mode,
the reference voltage is related to the input voltage and the output voltage of the buck-boost converter.
2. The control circuit of claim 1, wherein the mode switching circuit is configured to provide the loop control signal to the PWM/PFM controller to control the buck-boost converter to operate in the normal operating mode when the loop control signal is greater than the reference voltage; and
and when the loop control signal is smaller than the reference voltage, providing the reference voltage to the PWM/PFM controller so as to control the buck-boost converter to work in the light load working mode.
3. The control circuit of claim 2, wherein the reference voltages comprise a first reference voltage and a second reference voltage,
when the buck-boost converter works in a buck period, the mode switching circuit compares a buck loop control signal with the first reference voltage, and provides the buck loop control signal or the first reference voltage to the PWM/PFM controller according to a comparison result;
When the buck-boost converter works in a boost period, the mode switching circuit compares a boost loop control signal with the second reference voltage, and provides the boost loop control signal or the second reference voltage to the PWM/PFM controller according to a comparison result.
4. The control circuit of claim 3, wherein the first reference voltage is equal to a fixed first voltage value when the input voltage is less than the output voltage, the second reference voltage is positively correlated with a difference between the output voltage and the input voltage,
when the input voltage is greater than the output voltage, the first reference voltage is inversely related to the difference between the input voltage and the output voltage, and the second reference voltage is equal to a fixed second voltage value.
5. The control circuit of claim 4, wherein the reference voltage generation circuit comprises a first reference voltage generation module and a second reference voltage generation module,
the first reference voltage generation module includes:
a first transistor and a first current source connected in series between the output voltage and ground, the control terminal and the second terminal of the first transistor being shorted together;
A first resistor, a second transistor and a third transistor connected in series between the input voltage and ground, a control terminal of the second transistor being connected to a control terminal of the first transistor;
the positive input end of the first operational amplifier is used for receiving a first voltage signal, the first voltage signal has the first voltage value, and the negative input end of the first operational amplifier is connected with the output end; and
a second resistor and a fourth transistor connected in series between the output terminal of the first operational amplifier and ground, the control terminal of the fourth transistor being connected to the control terminal and the first terminal of the third transistor to form a current mirror, a common connection node of the second resistor and the fourth transistor being used for outputting the first reference voltage,
the second reference voltage generation module includes:
a fifth transistor and a second current source connected in series between the input voltage and ground, the control terminal and the second terminal of the fifth transistor being shorted together;
the positive input end of the second operational amplifier is used for receiving a second voltage signal, the second voltage signal has the second voltage value, and the negative input end of the second operational amplifier is connected with the output end; and
And a third resistor, a sixth transistor and a fourth resistor which are connected in series between the output voltage and the output end of the second operational amplifier, wherein the control end of the sixth transistor is connected with the control end of the fifth transistor, and a common connection node of the sixth transistor and the fourth resistor is used for outputting the second reference voltage.
6. The control circuit of claim 3, wherein the mode switching circuit comprises:
a first switch having a first input for receiving the first reference voltage, a second input for receiving the buck loop control signal, and an output for providing a first output signal selected from one of the buck loop control signal and the first reference voltage;
a second switch having a first input for receiving the second reference voltage, a second input for receiving the boost loop control signal, and an output for providing a second output signal selected from one of the boost loop control signal and the second reference voltage;
The first comparator is used for comparing the first reference voltage with the step-down loop control signal and controlling the switching of the first switch according to a comparison result; and
and the second comparator is used for comparing the second reference voltage with the boost loop control signal and controlling the switching of the second switch according to a comparison result.
7. A control circuit according to claim 3, wherein the PWM/PFM controller comprises:
a third comparator for comparing the buck loop control signal or the first reference voltage with the ramp signal to generate a first control signal;
a fourth comparator for comparing the boost loop control signal or the second reference voltage with the ramp signal to generate a second control signal;
a fifth comparator for comparing the loop control signal with a third reference voltage to generate an enable signal;
the AND gate circuit is used for performing AND logic operation on the enabling signal and a clock signal to generate a third control signal; and
and the logic and driving module is used for generating a plurality of switch driving signals for controlling the working states of a plurality of power switches in the buck-boost converter according to the first control signal, the second control signal and the third control signal.
8. The control circuit of claim 7, wherein the third control signal is set to an inactive state when the buck-boost converter is operating in a normal operating mode, the first control signal is used to control a duty cycle of a high side power switch of a buck converter portion of the buck-boost converter during a buck period, the second control signal is used to control a duty cycle of a low side power switch of a boost converter portion of the buck-boost converter during a boost period,
when the buck-boost converter is operated in the light load mode of operation, the third control signal is used to apply a drive signal to a high-side power switch of a buck converter section and an on edge of a drive signal to a low-side power switch of a boost converter section in the buck-boost converter, the first control signal is used to control an off edge of the drive signal to the high-side power switch of the buck converter section, and the second control signal is used to control an off edge of the drive signal to the low-side power switch of the boost converter section.
9. The control circuit of claim 1, wherein the ramp signal is related to or simulates an inductor current of the buck-boost converter,
The control circuit further includes a ramp generation circuit including:
a current sampling module for sampling a current flowing through an inductor of the buck-boost converter to generate a current sampling signal;
and the adder module is used for overlapping the current sampling signal and the harmonic compensation signal to obtain the ramp signal.
10. A buck-boost converter comprising:
a buck converter section including a first high side power switch and a first low side power switch connected in series between an input voltage and ground;
a boost converter section including a second high-side power switch and a second low-side power switch connected in series between the output voltage and ground;
an inductor connected between a common node of the first high side power switch and the first low side power switch and a common node of the second high side power switch and the second low side power switch; and
the control circuit of any one of claims 1-9.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117318499A (en) * | 2023-11-29 | 2023-12-29 | 武汉麦格米特电气有限公司 | Voltage regulating method, regulating circuit, power supply circuit and electronic equipment |
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2023
- 2023-03-21 CN CN202310281340.5A patent/CN116488434A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117318499A (en) * | 2023-11-29 | 2023-12-29 | 武汉麦格米特电气有限公司 | Voltage regulating method, regulating circuit, power supply circuit and electronic equipment |
| CN117318499B (en) * | 2023-11-29 | 2024-03-12 | 武汉麦格米特电气有限公司 | Voltage regulating method, regulating circuit, power supply circuit and electronic equipment |
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