CN116482446A - Charge balance type touch capacitance monitoring method - Google Patents
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Abstract
The invention belongs to the technical field of intelligent electronic equipment control and monitoring, and relates to a charge balance type touch capacitance monitoring method; the charge balance type touch capacitance monitoring chip is used for monitoring the touch capacitance CX, and the specific steps are as follows: the method comprises the steps of (1) charging a touch capacitor, (2) discharging the touch capacitor, (3) discharging a capacitor CDC, and (4) counting the number of pulses, and counting the discharge times of the capacitor CDC by using a counter module; (5) average value calculation: the AVERAGE module calculates the AVERAGE value of the pulse number in the period, (6) the difference value is calculated: calculating the difference value between the sampling value and the average value through the inside of the A-B subtracter, (7) judging by touching: when the difference is greater than the threshold LN, the capacitance CX is considered to be touched; the method has excellent electromagnetic compatibility and strong anti-interference performance, the final judgment result is not influenced by the power supply voltage, the sensitivity can be adjusted only by adjusting CDC, and the judgment result is accurate.
Description
Technical field:
the invention belongs to the technical field of intelligent electronic equipment control and monitoring. To a device for monitoring a change in touch capacitance voltage, which is configured to perform operations such as opening and closing of a mechanical device by a change in induced voltage. In particular to a charge balance type touch capacitance monitoring method which can accurately and sensitively sense the change of the touch capacitance.
The background technology is as follows:
the capacitive sensing technique is based on the following principle: when the surface of the object is touched or any other change occurs, the dielectric properties of a region of the object change, thereby changing the capacitance of the object, i.e., the voltage change that occurs to the object. The change in capacitance is very rapid compared to resistive touch technology. The rate of change can also be increased by enhancing the dielectric properties of the surface material. Capacitive sensors can sense various parameters, including electric fields, motion, chemical properties, acceleration, fluid properties, pressure, directly or indirectly. The sensor surface is an electrode surrounding a medium which, with the aid of a detection circuit and an excitation voltage, is able to convert a capacitance change into a changing voltage.
In the prior art, chinese patent publication No. CN114356145a discloses a touch detection circuit, a touch device and an electronic apparatus, the circuit comprising: the delay locked loop comprises a first delay unit, a delay locked loop unit and a detection unit; the delay phase-locked loop unit comprises a phase discrimination module and a second delay module; the first delay unit generates a first clock signal according to the reference clock signal and the capacitor to be tested; a second delay module generates a second clock signal according to the reference clock signal and a variable capacitance; the phase discrimination module is suitable for receiving the first clock signal and the second clock signal and generating corresponding output signals according to the relation between the first delay time of the first clock signal and the second delay time of the second clock signal until the delay phase-locked loop unit reaches a locking state; the detection unit is suitable for determining whether touch occurs according to the output signal of the phase discrimination module. Chinese patent publication No. CN110412348A discloses a count value generating circuit, a physical quantity sensor module, and a structure monitoring device, which can improve the accuracy of the count value. The count value generation circuit includes: a first counting unit that counts edges of a reference signal in synchronization with an input signal and generates a first count value; a time-digital value generation unit that generates a time-digital value corresponding to a phase difference between the reference signal and the input signal; a count integrated value synthesis unit configured to output a difference between the time digital value and an integer multiple of the first count value; and a count value generation unit that generates a count value based on a difference between the first output value and the second output value output from the count integrated value synthesis unit.
At present, the detection of the electrical data of the touch capacitor is easy to receive interference, and the electromagnetic compatibility is poor; the influence of the power supply voltage on the detection of the touch capacitance data is large, and the cost is increased by stabilizing the power supply voltage; therefore, a touch capacitance monitoring device with strong anti-interference capability and no influence of power supply voltage is accumulated and designed.
The invention comprises the following steps:
the invention aims to overcome the defects of the prior art and design a charge balance type touch capacitance monitoring method aiming at the problems of weak anti-interference capability, stability under power supply voltage and the like of the traditional touch capacitance monitoring device or method.
In order to achieve the above object, the method for monitoring the charge balance type touch capacitance according to the present invention uses a charge balance type touch capacitance monitoring chip to monitor the touch capacitance CX, and specifically comprises the following steps:
(1) And (3) charging a touch capacitor: the clock prescaler module periodically controls the switch TI and the switch TII to be opened and closed, and the states of the switch TI and the switch TII are opposite; when the state value of the switch TI is 1, the switch TI is closed, the first power supply is sequentially connected with the switch TI, the touch capacitor CX and the first ground wire in series, and the state value of the switch TI is 0 because the state values of the switch TI and the switch TII are mutually reversed, at the moment, the switch TII is disconnected, namely, a line between the touch capacitor CX and the capacitor CMOD is disconnected, the first power supply charges the touch capacitor CX, and the charge in the touch capacitor CX is gradually increased until the voltage value at two ends of the touch capacitor CX is the voltage VDD of the first power supply; when the state value of the switch TIII is 1, the switch TIII is closed, namely the circuit between the capacitor CMOD and the capacitor CDC is in a communication state; the state of the switch TIII is in reciprocal relation with the state of the switch TIV, when the state value of the switch TIII is 1, the state value of the switch TIV is 0, and the switch TIV is disconnected, namely the capacitor CDC and the fourth ground wire are in a disconnected state;
(2) Touch capacitance discharge: when the state value of the switch TI is 0, the switch TI cuts off a serial circuit of the first power supply and the touch capacitor CX, the state value of the switch TII is 1, the touch capacitor CX is communicated with the capacitor CMOD in series through the switch TII, charges in the touch capacitor CX are charged into the capacitor CMOD, the voltage at two ends of the capacitor CMOD is VMOD, and after the voltage of the charged capacitor CMOD is increased from 0 to the voltage equal to the voltage of the touch capacitor CX, namely, when the voltage values are all 0.5VDD, the charging process is stopped; when the touch capacitance CX and the capacitance CDC reach equilibrium, the touch capacitance CX reaches a steady state, the average value of the voltages at which the capacitance CMOD is located is 0.5VDD, and the average value of the voltages at which the touch capacitance CX is located is 0.5VDD, so that the quantity of charges transferred from the touch capacitance CX into the capacitance CMOD is 0.5vdd×cx;
(3) Capacitor CDC discharge: when the voltage value VMOD at two ends of the capacitor CMOD is too high in charging voltage, the voltage is input to the comparator CMP through a pin p end of the comparator CMP, the comparator CMP outputs a comparison result signal, the comparison result signal is transmitted to the NAND gate module, a judgment result is input to the trigger through a QN end of the NAND gate module, the trigger generates an adjustment signal according to the judgment result, the adjustment signal adjusts and controls the switch TIII through an output line of a QB end of the trigger through the trigger, the state value of the switch TIII becomes 0, and the switch TIII is disconnected, namely, a line between the capacitor CMOD and the capacitor CDC is in a disconnected state; meanwhile, an adjusting signal is input to the second inverter through the QB end of the trigger pin through the trigger, the second inverter outputs a signal CLK-CDC, the state value of the signal CLK-CDC at the moment is output to be 1, the switch TIV is controlled to be closed through the signal CLK-CDC output by the second inverter, namely, the capacitor CDC is in a communication state with the fourth ground wire, and the capacitor CDC discharges and discharges redundant charges;
When the voltage value VMOD at two ends of the capacitor CMOD is lower, the voltage input into the comparator CMP is sequentially processed and output into an adjusting signal through the NAND gate module and the DFF trigger, the state value of the switch TIII is controlled to be 1, the switch TIII is closed, and the voltage VMOD of the capacitor CMOD is equal to the voltage VCDC of the capacitor CDC; the adjusting signal is input to the second inverter through the trigger, the second inverter outputs signals CLK-CDC, the state value output by CLK_CDC is 0, and the switch TIV is opened;
(4) Counting the number of pulses: the signal CLK-CDC output by the second inverter is simultaneously transmitted to a counter module, and the counter module receives a second fixed clock signal; the CLK-CDC and the second fixed clock signal are subjected to internal counting processing by a counter module, the counter module outputs sampling values, and the sampling values are marked as SAMP [11:0];
(5) Average value calculation: the counter module inputs the SAMP [11:0] into an AVERAGE module of the AVERAGE, and the AVERAGE value STD [11:0] of a plurality of sampling periods is obtained through processing;
(6) And (3) calculating a difference value: the AVERAGE value STD [11:0] is input into the A-B subtracter by the AVERAGE module, the SAMP [11:0] is input into the A-B subtracter by the counter module, and the calculated difference value between the SAMP [11:0] and the STD [11:0] through the A-B subtracter is recorded as DLT [11:0];
(7) And (3) touch judgment: comparing the output DLT [11:0] of the A-B module with a set critical value LN, and when the value of DLT [11:0] is larger than the critical value LN, considering that the capacitor CX is touched; the value range of LN is set to 8-30, and the sensitivity of the touch capacitor CX is selected according to the adjusted LN value.
The principle method for monitoring the touch capacitance CX by the charge balance type touch capacitance monitoring chip comprises the following steps:
(1) The states of the switch TIII and the switch TIV are reciprocal, in one clock period, when the state value of the switch TIII is 1, the switch TIII is closed to charge the capacitor CDC, the charged charge quantity is 0.5VDD which is the CDC, at the moment, the capacitor CMOD and the capacitor CDC are connected in parallel, and the voltage VMOD at two ends of the capacitor CMOD and the voltage VCDC at two ends of the capacitor CDC are equal; when the state value of the switch TIII is 0, the switch TIII is opened, the state value of the switch TIV is 1, and the switch TIV is closed, so that the capacitor CDC is in a discharging state;
(2) The capacitor CMOD is used as a charging capacitor, and the amount of charge of the first power supply for charging the capacitor CMOD through the switch TI and the switch TII is equal to the amount of charge discharged through the switch TIII and the switch TIV, that is, the amount of charge charged is equal to the amount of charge discharged; the capacitor CMOD discharge is realized through the capacitor CDC discharge, and the voltage at two ends of the capacitor CMOD is equal to the voltage at two ends of the capacitor CDC, so that the voltage value of the capacitor CDC is reduced, and the voltage value of the capacitor CMOD is also reduced; excess charge in capacitor CMOD is discharged through capacitor CDC; assuming that the number of pulses CLK_PRS for charging the capacitor CMOD is M and the number of pulses CLK_CDC for discharging the capacitor CMOD is N, N is the sampling value SAMP [11:0]; from the conservation of charge, the following equation can be obtained:
0.5vdd×m=0.5 vdd×cdc×n, i.e., cx×m=cdc×n; (1)
CX is the capacitance value of the touch capacitance CX, and CDC is the capacitance value of the capacitance CDC;
under the condition that M is fixed, when the touch capacitance CX changes, N can linearly change along with the capacitance, and information of the touch capacitance CX can be obtained by monitoring N; VDD in equation (1) can be about dropped, eventually making DLT [11:0] independent of VDD, i.e., sensitivity independent of VDD, and as long as CDC is adjusted, the sensitivity of monitoring the sensing of the touch capacitance CX can be adjusted.
The charge balance type touch capacitance monitoring chip comprises a touch channel and a touch judgment module, wherein the touch channel adopts a charge balance type touch capacitance monitor structure, and the touch channel is used for sensing touch; the touch channel is in electrical information connection with the touch judging module, and the touch judging module is used for comparing the data difference value input by the touch channel with a set value, and when the data difference value is larger than the set value, the touch sensing module is judged to be touched.
The charge balance type touch capacitance monitor comprises a main body structure, a control analysis module and a data processing module, wherein the main body structure comprises a touch sensing module; the touch sensing module, the control analysis module and the data processing module are sequentially connected with each other in an orderly manner; wherein the method comprises the steps of
The touch sensing module is used for constructing a sensing circuit by utilizing a charge balance principle through a touch capacitor and outputting a sensing voltage to the outside;
and a control analysis module: the touch sensing module is used for processing and analyzing the voltage input by the touch sensing module, outputting a control signal, controlling the touch sensing module to operate according to the control signal, and transmitting the control signal to the data processing module;
and a data processing module: the control signal input by the statistical control analysis module is processed and calculated to obtain a data difference value, and the data difference value is input into the touch judgment module.
The touch sensing module comprises a first clock signal input end, a clock prescaler module (PRS), a first power supply, a first phase inverter, a switch TI, an input pin board, a touch capacitor CX, a first ground wire, a switch TII, a capacitor CMOD, a second ground wire, a capacitor CDC, a third ground wire, a switch TIV, a fourth ground wire and a switch TIII, wherein the first clock signal input end is connected with the input end of the clock prescaler module, the first clock signal input end inputs the first fixed clock signal into the clock prescaler module, the clock prescaler module processes the first fixed clock signal to obtain CLK_PRS pulses, and the clock prescaler module outputs the CLK_PRS pulses; the output of the clock prescaler module is connected with a first inverter and a first contact end of a switch TII in parallel, the output end of the round end of the first inverter is connected with the first contact end of a switch TI, and the connection end of the switch TI is connected with a first power supply; the second contact end of the switch TI is sequentially connected with the touch capacitor CX and the first ground wire in series, and when the second contact end of the switch TI is connected with the external interface of the touch capacitor CX in a closed mode, the first power supply is sequentially connected with the switch TI, the touch capacitor CX and the first ground wire in series and charges the touch capacitor CX; the external interface of the touch capacitor CX is also connected with the output end of an input pin disc, the input pin disc inputs the input of the whole circuit, and the input pin disc is used for receiving external signals and converting the external signals into the touch capacitor CX, wherein the external signals are external touches; the external interface of the touch capacitor CX is also connected with a second contact end of the switch TII, and the connection end of the switch TII is sequentially connected with the input end of the capacitor CMOD, the connection end of the switch TIII and the p end of the comparator CMP pin of the control analysis module in parallel; the capacitor CMOD is connected with the second ground wire in series, the voltage at two ends of the capacitor CMOD is VMOD, and the capacitor CMOD is a collecting capacitor and plays a role in voltage stabilization; when the first contact end of the switch TIII is connected with the first input end of the capacitor CDC in a closed mode, the capacitor CMOD can be connected with the switch TIII, the capacitor CDC and the third ground wire in sequence to form a series circuit; the second input end of the capacitor CDC is connected with the connecting end of the switch TIV, the first contact end of the switch TIV is connected with the fourth ground wire, when the first contact end of the switch TIV is connected with the fourth ground wire, the first contact end of the switch TIII is disconnected with the first input end of the capacitor CDC, and the capacitor CDC discharges to the fourth ground wire through the switch TIV; the switch TIII and the switch TIV are also respectively connected with the control analysis module and controlled by the control analysis module.
The control analysis module comprises a second power supply, a first resistor, a comparator CMP, a NAND gate module, a fifth ground wire, a trigger, a second inverter, a second resistor, a fifth ground wire and a second clock signal input end, wherein the p end of a pin of the comparator CMP is connected with the connecting end of a switch TII, the N end of a pin of the comparator CMP is connected with the first resistor and the second resistor in parallel, and the resistance values of the first resistor and the second resistor are 100kΩ; the N end of the pin of the comparator CMP obtains the voltage value the same as that of the second resistor; the input end of the first resistor is connected with a second power supply, and the input end of the second resistor is connected with a fifth ground wire in series; the output end of the comparator CMP is connected with the end B of a NAND gate module pin B, the end O of the comparator CMP is the input of the NAND gate module pin B, the end QN of the NAND gate module is connected with the end D of a trigger pin, the output end of the NAND gate module QN is used as the input of the end D of the trigger pin, the end C of the trigger pin is connected with a second clock signal input end, and the second clock signal input end is also connected with the end CLK of a counter module pin of the data processing module; the second clock signal input end and the first clock signal input end receive the same clock signal, and the trigger pin C end receives a second fixed clock signal; the Q end of the trigger is connected with the A end of the pin of the NAND gate module, and the output of the Q end of the trigger is used as the input of the A end of the pin of the NAND gate module; the output of the trigger pin QB end controls the closing state of the switch TIII; the QB end of the trigger pin is also connected with the input end of the second inverter, and the output of the QB end of the trigger pin is processed by the second inverter to obtain a signal CLK-CDC; the output end of the second inverter is connected with the pin INC end of the counter module, and the second inverter inputs CLK_CDC into the pin INC end of the counter module; the output end of the second inverter is also connected with the second contact end of the switch TIV, and the closed state of the switch TIV is controlled through CLK_CDC output by the second inverter.
The data processing module comprises a counter module, an AVERAGE module and an A-B subtracter, wherein a pin CLK (clock signal) of the counter module receives a second fixed clock signal; the two inputs of the counter module are a signal CLK_CDC and a second fixed clock signal respectively, CLK is a clock signal with fixed frequency, the two signals are counted and processed in the counter module, the counter module outputs a sampling value mark as SAMP [11:0], wherein [11:0] represents that the number of bits of sampling is 12; the output end of the counter module is connected with the input end of the AVERAGE module, SAMP [11:0] is used as the input of the AVERAGE module, and the AVERAGE value STD [11:0] of a plurality of sampling periods is obtained through processing; the output end of the AVERAGE module of AVERAGE is connected with pin B end of A-B subtracter, AVERAGE module of AVERAGE inputs AVERAGE STD [11:0] into pin B end of A-B subtracter; the output end of the counter module is also connected with the pin A end of the A-B subtracter, and after being processed by the A-B subtracter, the SAMP [11:0] and the STD [11:0] are output as DLT [11:0].
The switch TI, the switch TII, the switch TIII and the switch TIV are ideal switches.
Further, the charge balance type touch capacitance monitoring chip also comprises a sampling channel and a trimming module, wherein the sampling channel adopts a charge balance type touch capacitance monitor structure, the output ends of the sampling channel and the touch channel are respectively in information connection with the receiving end of the trimming module, and the output end of the trimming module is in information connection with the receiving end of the touch judging module;
The sampling channel is used for acquiring data detected by the charge balance type touch capacitance monitor under the condition of no touch;
the trimming module is used for trimming the data acquired by the touch channel, eliminating interference factors under the condition of no touch, and inputting the trimmed acquired data into the touch judgment module.
The trimming module has the structure that: the trimming module comprises a DIV12BIT module, a MUL12BIT module and a SUB12BIT module, wherein the DIV12BIT module is provided with a pin A and a pin B, the pin A of the DIV12BIT module obtains an input SAMP0_ [11:0], SAMP0_ [11:0] is a current sampling value in a sampling channel, the pin B of the DIV12BIT module obtains an input STD0_ [11:0], STD0_ [11:0] is an average value of current sampling in the sampling channel, and the SAMP0_ [11:0] and the STD0_ [11:0] are output as DIV [12:0] after being internally processed by the DIV12BIT module; the output end of the DIV12BIT module is connected with a pin B of the MUL12BIT module, and the MUL12BIT module is provided with a pin A and a pin B; DIV [12:0] is used as the input of pin B in the MUL12BIT module, and the input of pin A of the MUL12BIT module is the average value STD1_ [11:0] of the touch channel; DIV [12:0], STD1_ [11:0] are internally processed by the MUL12BIT module and then output as STD1_VAL [11:0], and STD1_VAL [11:0] is the average value of the touch channels after trimming; the output end of the MUL12BIT module is connected with a pin B of the SUB12BIT module, STD1_VAL [11:0] is used as the input of the pin B of the SUB12BIT module, the input SAMP1_11:0 of the pin A of the SUB12BIT module is the current sampling value of the touch channel, and after the STD1_VAL [11:0] and the SAMP1_11:0 ] are processed in the SUB12BIT module, DLT1_11:0 is output; the output DLT1_ [11:0] is the difference value of the touch channel after trimming, and the final output difference value is compared with LN to judge whether the touch capacitor CX is touched or not; when DLT1_ [11:0] is larger than LN, touch is considered, the value range of LN is set between 8 and 30, and the trimming module adopts a calculation formula of a trimming algorithm as follows:
DIV[12:0]＝SAMP0_[11:0]/STD0_[11:0]
STD1_VAL[11:0]＝STD1_[11:0]*DIV[12:0]
DLT1_[11:0]＝SAMP01_[11:0]-STD1_VAL[11:0]。
Compared with the prior art, the designed charge balance type touch capacitance monitoring method has the following beneficial effects: 1. the CLK_PRS adopted by the invention is generated by a pseudo-random sequence, and the number of CLK_PRS pulses is fixed in one adopted period, but the period of CLK_PRS pulses is randomly changed, so that the algorithm has great benefits on electromagnetic compatibility and interference resistance. 2. The charge balance adopts capacitor charging and discharging, 0.5VDD CX M=0.5 VDD CDC N, and VDD can be about dropped in the equation, so that DLT [11:0] is independent of VDD, namely the sensitivity is independent of VDD, and the sensitivity can be adjusted only by adjusting CDC. 3. And the interference resistance is further improved by adopting a reference channel trimming algorithm. The designed charge balance type touch capacitance monitor is applied to SC series touch chips, and the charge balance type touch capacitance monitor and the chips thereof can be applied to intelligent equipment fields such as large-scale mechanical touch switches, electronic touch screens, robot body surface touch induction and the like.
Description of the drawings:
fig. 1 is a schematic block diagram of a modular structure of a charge balance type touch capacitance monitoring chip according to the present invention.
Fig. 2 is a schematic structural diagram of a charge balance type touch capacitance monitor according to the present invention.
Fig. 3 is a schematic structural diagram of a touch sensing module according to the present invention.
Fig. 4 is a schematic structural diagram of a control analysis module according to the present invention.
Fig. 5 is a schematic diagram of the structure of a data processing module according to the present invention.
Fig. 6 is a schematic structural diagram of a trimming module according to the present invention.
The specific embodiment is as follows:
the invention is further illustrated by the following examples in conjunction with the accompanying drawings.
Example 1:
as shown in fig. 1, the main structure of the charge balance type touch capacitance monitor according to the embodiment includes a touch sensing module 1, a control analysis module 2, and a data processing module 3; the touch sensing module 1, the control analysis module 2 and the data processing module 3 are sequentially connected with each other in an orderly manner; wherein the method comprises the steps of
The touch sensing module 1 is used for constructing a sensing circuit by utilizing a charge balance principle through a touch capacitor and outputting a sensing voltage to the outside;
control analysis module 2: the control module is used for processing and analyzing the voltage input by the touch sensing module 1, outputting a control signal, controlling the touch sensing module 1 to operate according to the control signal, and transmitting the control signal to the data processing module 3;
data processing module 3: the control signal input by the statistical control analysis module 2 is processed and calculated to obtain a data difference value, and the data difference value is input into the touch judgment module 5.
As shown in fig. 2 and 3, the touch sensing module 1 includes a first clock signal input terminal 6, a clock prescaler module (PRS) 7, a first power supply 8, a first Inverter (INV) 9, a switch TI10, an input PAD (PAD) 11, a touch capacitor CX12, a first ground wire 13, a switch TII14, a capacitor CMOD15, a second ground wire 16, a capacitor CDC17, a third ground wire 18, a switch TIV19, a fourth ground wire 20, and a switch TIII21, wherein the first clock signal input terminal 6 is connected with the input terminal of the clock prescaler module (PRS) 7 by a first fixed clock signal CLK, the first clock signal input terminal 6 inputs the first fixed clock signal (CLK) to the clock prescaler module (PRS) 7, the clock prescaler module (PRS) 7 processes the first fixed clock signal (CLK) to obtain clk_prs pulses, the clock prescaler module (PRS) 7 outputs clk_prs pulses, the output clk_prs pulses whose periods are randomly varied, but the number of PRS pulses is fixed within one sampling period, which is a great compatibility against electromagnetic interference caused by the structure; the output of the clock prescaler module (PRS) 7 is connected with a first Inverter (INV) 9 and a first contact end of a switch TII14 in parallel, the output end of the round end of the first inverter is connected with the first contact end of a switch TI10, and the connection end of the switch TI10 is connected with a first power supply 8 (the voltage is VDD); the second contact end of the switch TI10 is sequentially connected with the touch capacitor CX12 and the first ground wire 13 in series, and when the second contact end of the switch TI10 is connected with the external interface of the touch capacitor CX12 in a closed mode, the first power supply 8 is sequentially connected with the switch TI10, the touch capacitor CX12 and the first ground wire 13 in series, and the first power supply 8 charges the touch capacitor CX 12; the external interface of the touch capacitor CX12 is also connected with the output end of the input pin disc (PAD) 11, the input pin disc (PAD) 11 inputs the input (CIN) of the whole circuit, the input pin disc (PAD) 11 is used for receiving external signals and converting the external signals into the touch capacitor CX12, and the external signals are external touches; the external interface of the touch capacitor CX12 is also connected with a second contact end of the switch TII14, and the connection end of the switch TII14 is sequentially connected with the input end of the capacitor CMOD15, the connection end of the switch TIII21 and the pin p end of the comparator CMP24 of the control analysis module 2 in parallel; the capacitor CMOD15 is connected with the second ground wire 16 in series, the voltage at two ends of the capacitor CMOD15 is VMOD, and the capacitor CMOD15 is a collecting capacitor and plays a role in voltage stabilization; the first contact end of the switch TIII21 is sequentially connected with the capacitor CDC17 and the third ground wire 18 in series, and when the first contact end of the switch TIII21 is closed and connected with the first input end of the capacitor CDC17, the capacitor CMOD15 can be sequentially connected with the switch TIII21, the capacitor CDC17 and the third ground wire 18 to form a series circuit; the second input end of the capacitor CDC17 is connected with the connecting end of the switch TIV19, the first contact end of the switch TIV19 is connected with the fourth ground wire 20, when the first contact end of the switch TIV19 is connected with the fourth ground wire 20, the first contact end of the switch TIII21 is disconnected with the first input end of the capacitor CDC17, and the capacitor CDC17 discharges to the fourth ground wire 20 through the switch TIV 19; the switch TIII21 and the switch TIV19 are also respectively connected with the control analysis module 2 and controlled by the control analysis module 2.
As shown in fig. 2 and 4, the control analysis module 2 includes a second power supply 22, a first resistor 23, a comparator CMP24, a nand gate module 25, a fifth ground line 29, a flip-flop (DFF) 26, a second inverter 27, a second resistor 28, a fifth ground line 29, and a second clock signal input end 30, wherein a pin p end of the comparator CMP24 is connected with a connection end of the switch TII14, a pin N end of the comparator CMP24 is connected with a first resistor 23 and a second resistor 28 in parallel, and resistance values of the first resistor 23 and the second resistor 28 are 100kΩ; the N terminal of the pin of the comparator CMP24 obtains the same voltage value as the second resistor 28; the input end of the first resistor 23 is connected with the second power supply 22 (the voltage is VDD), and the input end of the second resistor 28 is connected with the fifth ground wire 29 in series; the output end of the comparator CMP24 is connected with the pin B end of the NAND gate module 25, the output end of the comparator CMP24 is the input end of the pin B of the NAND gate module 25, the QN end of the NAND gate module 25 is connected with the pin D end of the trigger (DFF) 26, the output end of the QN end of the NAND gate module 25 is used as the input end of the pin D end of the trigger (DFF) 26, the pin C end of the trigger (DFF) 26 is connected with the second clock signal input end 30, and the second clock signal input end 30 is also connected with the pin CLK end of the counter module (CNT) 31 of the data processing module 3; the second clock signal input 30 receives the same clock signal as the first clock signal input 6, and the flip-flop (DFF) 26 receives a second fixed clock signal (CLK) at pin C; the end of the trigger (DFF) 26Q is connected with the end of the pin A of the NAND gate module 25, and the output of the end of the trigger (DFF) 26Q is used as the input of the end of the pin A of the NAND gate module 25; the QB end of the trigger (DFF) 26 pin is connected with the second contact end of the switch TIII21, and the output of the QB end of the trigger (DFF) 26 pin controls the closed state of the switch TIII 21; the QB end of the trigger (DFF) 26 pin is also connected with the input end of the second inverter 27, and the output of the QB end of the trigger (DFF) 26 pin is processed by the second inverter 27 to obtain a signal CLK-CDC; the output end of the second inverter 27 is connected with the INC end of the pin (CNT) 31 of the counter module (CNT), and the second inverter 27 inputs CLK_CDC into the INC end of the pin (CNT) 31 of the counter module (CNT); the output terminal of the second inverter 27 is also connected to a second contact terminal of the switch TIV19, and the closed state of the switch TIV19 is controlled by clk_cdc output from the second inverter 27.
As shown in fig. 2 and 5, the data processing module 3 includes a counter module (CNT) 31, an AVERAGE module 32, and an a-B subtractor 33, where a pin CLK of the counter module (CNT) 31 receives a second fixed clock signal (CLK); the purpose of the counter module (CNT) 31 is to record the number of CLK-CDC in one sampling period, two inputs of the counter module (CNT) 31 are the signal clk_cdc and the second fixed clock signal (CLK), CLK is the clock signal with fixed frequency, the two signals are counted inside the counter module (CNT) 31, the counter module (CNT) 31 outputs sampling value marks as SAMP [11:0], wherein [11:0] represents the number of sampled bits as 12; the output end of the counter module (CNT) 31 is connected with the input end of the AVERAGE module 32, SAMP [11:0] is used as the input of the AVERAGE module 32, and the AVERAGE value STD [11:0] of a plurality of sampling periods is obtained through processing; the output end of the AVERAGE module 32 is connected with the pin B end of the A-B subtracter 33, and the AVERAGE module 32 inputs the AVERAGE value STD [11:0] into the pin B end of the A-B subtracter 33; the output end of the counter module (CNT) 31 is also connected with the pin A end of the A-B subtracter 33, and after the samP [11:0] and the STD [11:0] are processed by the A-B subtracter 33, the output is DLT [11:0].
The switches TI, TII14, TIII21, and TIV19 according to the present embodiment are ideal switches.
Example 2:
the charge balance type touch capacitance monitor described in embodiment 1 is applied to construct a charge balance type touch capacitance monitoring chip; the charge balance type touch capacitance monitoring chip comprises a touch channel and a touch judgment module 5, wherein the touch channel adopts a charge balance type touch capacitance monitor structure, and the touch channel is used for sensing touch; the touch channel is in electrical information connection with the touch judging module 5, and the touch judging module 5 is used for comparing a data difference value input by the touch channel with a set value, and when the data difference value is larger than the set value, the touch sensing module 1 is determined to be touched.
The specific process of the charge balance type touch capacitance monitoring chip for monitoring the touch capacitance CX12 is as follows:
(1) And (3) charging a touch capacitor: the clock prescaler module (PRS) 7 periodically controls the switch TI10 and the switch TII14 to be opened and closed, and the states of the switch TI10 and the switch TII14 are opposite; when the state value of the switch TI10 is 1, the switch TI10 is closed, the first power supply 8 is sequentially connected in series with the switch TI10, the touch capacitor CX12 and the first ground wire 13, and since the state values of the switch TI10 and the switch TII14 are mutually opposite, the state value of the switch TII14 is 0, at this time, the switch TII14 is opened, that is, the line between the touch capacitor CX12 and the capacitor CMOD15 is opened, the first power supply 8 charges the touch capacitor CX12, the charge in the touch capacitor CX12 gradually increases until the voltage value at both ends of the touch capacitor CX12 is the voltage VDD of the first power supply 8; when the state value of the switch TIII21 is 1, the switch TIII21 is closed, namely the line between the capacitor CMOD15 and the capacitor CDC17 is in a communicating state; the state of the switch TIII21 is in reciprocal relation to the state of the switch TIV19, when the state value of the switch TIII21 is 1, the state value of the switch TIV19 is 0, and the switch TIV19 is disconnected, namely the capacitor CDC17 and the fourth ground wire 20 are in a disconnected state;
(2) Touch capacitance discharge: when the state value of the switch TI10 is 0, the switch TI10 disconnects the serial circuit of the first power supply 8 and the touch capacitor CX12, the state value of the switch TII14 is 1, the touch capacitor CX12 is serially connected with the capacitor CMOD15 through the switch TII14, the charge in the touch capacitor CX12 is charged into the capacitor CMOD15, the voltage at both ends of the capacitor CMOD15 is VMOD, and the charging process is stopped when the voltage of the charged capacitor CMOD15 is raised from 0 to equal to the voltage of the touch capacitor CX12, that is, the voltage values are all 0.5 VDD; when the touch capacitance CX12 and the capacitance CDC17 reach balance, the touch capacitance CX12 reaches steady state, the average value of the voltages of the capacitance CMOD15 is 0.5VDD, the average value of the voltages of the touch capacitance CX12 is 0.5VDD, and then the quantity of charges transferred into the capacitance CMOD15 from the touch capacitance CX12 is 0.5 VDD;
(3) Capacitor CDC17 discharges: when the voltage value VMOD charging voltage at both ends of the capacitor CMOD15 is too high, the voltage is input to the comparator CMP24 through the pin p end of the comparator CMP24, the comparator CMP24 outputs a comparison result signal, the comparison result signal is transmitted to the nand gate module 25, the judgment result is input to the trigger (DFF) 26 through the QN end of the nand gate module 25, the trigger (DFF) 26 generates an adjustment signal according to the judgment result, the adjustment signal adjusts the control switch tii 21 through the output line of the trigger (DFF) 26QB end by the trigger (DFF) 26, the state value of the switch tii 21 becomes 0, and the switch TIII21 is disconnected, namely, the line between the capacitor CMOD15 and the capacitor CDC17 is in an off state; meanwhile, an adjusting signal is input to the second inverter 27 through the trigger (DFF) 26 via the QB end of the pin (DFF) 26, the second inverter 27 outputs a signal CLK-CDC, the state value of CLK_CDC at the moment is output to be 1, the switch TIV19 is controlled to be closed by the signal CLK-CDC output by the second inverter 27, namely, the capacitor CDC17 is in a communication state with the fourth ground wire 20, and the capacitor CDC17 discharges and discharges redundant charges;
When the voltage value VMOD voltage at two ends of the capacitor CMOD15 is relatively low, the voltage of the input comparator CMP24 is sequentially processed and output to adjust the signal through the nand gate module 25 and the DFF trigger, the state value of the switch TIII21 is controlled to be 1, the switch TIII21 is closed, and the voltage VMOD of the capacitor CMOD15 is equal to the voltage VCDC of the capacitor CDC 17; the adjustment signal is input to the second inverter 27 via the flip-flop (DFF) 26, the second inverter 27 outputs the signals CLK-CDC, the state value output at this time of clk_cdc is 0, and the switch TIV19 is turned off;
(4) Counting the number of pulses: the signal CLK-CDC output by the second inverter 27 is simultaneously transmitted to the counter module (CNT) 31, and the counter module (CNT) 31 receives the second fixed clock signal (CLK); the CLK-CDC and the second fixed clock signal (CLK) are internally counted by a counter module (CNT) 31, the counter module (CNT) 31 outputs sampling values, and the sampling values are marked as SAMP [11:0];
(5) Average value calculation: the counter module (CNT) 31 inputs the SAMP [11:0] to the AVERAGE module 32, and processes the sample period AVERAGE STD [11:0];
(6) And (3) calculating a difference value: the AVERAGE module 32 inputs the AVERAGE STD [11:0] to the A-B subtractor 33, the counter module (CNT) 31 inputs SAMP [11:0] to the A-B subtractor 33, and the difference between the AVERAGE STD [11:0] and the AVERAGE STD [11:0] calculated by the A-B subtractor 33 is recorded as DLT [11:0];
(7) And (3) touch judgment: comparing the output DLT [11:0] of the A-B module with a set critical value LN, and when the value of DLT [11:0] is larger than the critical value LN, considering that the capacitor CX is touched; the value range of LN is set to 8-30, and the appropriate sensitivity of the touch capacitor CX12 is selected according to the adjusted LN value.
The principle of the charge balance type touch capacitance monitoring chip for monitoring the touch capacitance CX12 is as follows:
(1) The states of the switch TIII21 and the switch TIV19 are reciprocal, in one clock period, when the state value of the switch TIII21 is 1, the switch TIII21 is closed to charge the capacitor CDC17, the charged charge amount is 0.5VDD, at this time, the capacitor CMOD15 and the capacitor CDC17 are connected in parallel, and the voltage VMOD at two ends of the capacitor CMOD15 and the voltage VCDC at two ends of the capacitor CDC17 are equal; when the state value of the switch TIII21 is 0, the switch TIII21 is opened, the state value of the switch TIV19 is 1, the switch TIV19 is closed, and the capacitor CDC17 is in a discharging state;
(2) The capacitor CMOD15 serves as a charging capacitor, and the first power supply 8 charges the capacitor CMOD15 through the switch TI10 and the switch TII14 by an amount equal to an amount of electric charge discharged to the capacitor CMOD15 through the switch TIII21 and the switch TIV19, that is, an amount of electric charge charged is equal to an amount of electric charge discharged; the discharging of the capacitor CMOD15 is realized by the discharging of the capacitor CDC17, because the voltage of the two ends of the capacitor CMOD15 is equal to the voltage of the two ends of the capacitor CDC17, the voltage value of the capacitor CDC17 is reduced, and the voltage value of the capacitor CMOD15 is also reduced; excess charge in capacitor CMOD15 is discharged through capacitor CDC 17; assuming that the number of pulses CLK_PRS for charging the capacitor CMOD15 is M and the number of pulses CLK_CDC for discharging the capacitor CMOD15 is N, N is the sampling value SAMP [11:0]; from the conservation of charge, the following equation can be obtained:
0.5vdd×m=0.5 vdd×cdc×n, i.e., cx×m=cdc×n;
CX is the capacitance value of the touch capacitance CX12, and CDC is the capacitance value of the capacitance CDC 17;
under the condition that M is fixed, when the touch capacitance CX12 is changed (for example, whether the touch capacitance CX12 is touched by a finger or not), N can be changed linearly along with the capacitance, and information of the touch capacitance CX12 can be obtained by monitoring N.
Example 3:
in the embodiment 2, a sampling channel is additionally designed in the charge balance type touch capacitance monitoring chip, the sampling channel and the touch channel both adopt a charge balance type touch capacitance monitor structure, the sampling channel also generates sampling values, and the sampling values obtained by the touch channel in the chip structure are trimmed and used; when the chip is interfered by some external interference, the sampling value of the sampling channel and the sampling value of the touch channel are fluctuated, the obtained data of the touch channel is corrected through the sampling channel, and the external interference is eliminated. In order to further improve the anti-interference performance of the touch chip, an additional trimming module 4 is applied to perform trimming processing on the sampling value output by the counter module by using a trimming algorithm structure.
The charge balance type touch capacitance monitoring chip further comprises a sampling channel and a trimming module 4, wherein the sampling channel adopts a charge balance type touch capacitance monitor structure, the output ends of the sampling channel and the touch channel are respectively in electric information connection with the receiving end of the trimming module 4, and the output end of the trimming module 4 is in electric information connection with the receiving end of the touch judging module 5;
The sampling channel is used for acquiring data detected by the charge balance type touch capacitance monitor under the condition of no touch;
the trimming module 4 is used for trimming the data collected by the touch channel, eliminating interference factors under the condition of no touch, and inputting the trimmed collected data into the touch judging module 5.
The structure of the trimming module 4 is shown in fig. 6, and the structure of the trimming module 4 is as follows: the trimming module 4 includes a DIV12BIT module 34, a MUL12BIT module 35, a SUB12BIT module 36, the DIV12BIT module 34 is provided with a pin A and a pin B, the pin A of the DIV12BIT module 34 obtains an input SAMP0_ [11:0], SAMP0_ [11:0] is a current sampling value in the sampling channel, the pin B of the DIV12BIT module 34 obtains an input STD0_ [11:0], STD0_ [11:0] is an average value of the current sampling in the sampling channel, and the SAMP0_ [11:0] and STD0_ [11:0] are output as DIV [12:0] after being processed by the DIV12BIT module 34; the output end of the DIV12BIT module 34 is connected with a pin B of the MUL12BIT module 35, and the MUL12BIT module 35 is provided with a pin A and a pin B; DIV [12:0] as input to pin B in MUL12BIT module 35, MUL12BIT module 35 pin A input is the average STD1_ [11:0] of the touch channel; DIV [12:0], STD1_ [11:0] are internally processed by MUL12BIT module 35 and output as STD1_VAL [11:0], and STD1_VAL [11:0] is the average value of the touch channel after trimming; the output of MUL12BIT module 35 is connected to pin B of SUB12BIT module 36, STD1_VAL [11:0] is used as input of pin B of SUB12BIT module 36, the input SAMP1_ [11:0] of pin A of SUB12BIT module 36 is the current sampling value of the touch channel, STD1_VAL [11:0], SAMP1_ [11:0] is processed by SUB12BIT module 36 and then DLT1_ [11:0] is outputted; the output DLT1_ [11:0] is the difference value of the touch channel after trimming, and the final output difference value is compared with LN to judge whether the touch capacitor CX12 is touched or not; when DLT1_ [11:0] is larger than LN, touch is considered, the value range of LN is set between 8 and 30, and the trimming module 4 adopts a calculation formula of a trimming algorithm as follows:
DIV[12:0]＝SAMP0_[11:0]/STD0_[11:0]
STD1_VAL[11:0]＝STD1_[11:0]*DIV[12:0]
DLT1_[11:0]＝SAMP01_[11:0]-STD1_VAL[11:0]。
Claims (10)
1. A charge balance type touch capacitance monitoring method is characterized in that: the charge balance type touch capacitance monitoring chip is used for monitoring the touch capacitance CX, and the specific steps are as follows:
(1) And (3) charging a touch capacitor: the clock prescaler module periodically controls the switch TI and the switch TII to be opened and closed, and the states of the switch TI and the switch TII are opposite; when the state value of the switch TI is 1, the switch TI is closed, the first power supply is sequentially connected with the switch TI, the touch capacitor CX and the first ground wire in series, and the state value of the switch TI is 0 because the state values of the switch TI and the switch TII are mutually reversed, at the moment, the switch TII is disconnected, namely, a line between the touch capacitor CX and the capacitor CMOD is disconnected, the first power supply charges the touch capacitor CX, and the charge in the touch capacitor CX is gradually increased until the voltage value at two ends of the touch capacitor CX is the voltage VDD of the first power supply; when the state value of the switch TIII is 1, the switch TIII is closed, namely the circuit between the capacitor CMOD and the capacitor CDC is in a communication state; the state of the switch TIII is in reciprocal relation with the state of the switch TIV, when the state value of the switch TIII is 1, the state value of the switch TIV is 0, and the switch TIV is disconnected, namely the capacitor CDC and the fourth ground wire are in a disconnected state;
(2) Touch capacitance discharge: when the state value of the switch TI is 0, the switch TI cuts off a serial circuit of the first power supply and the touch capacitor CX, the state value of the switch TII is 1, the touch capacitor CX is communicated with the capacitor CMOD in series through the switch TII, charges in the touch capacitor CX are charged into the capacitor CMOD, the voltage at two ends of the capacitor CMOD is VMOD, and after the voltage of the charged capacitor CMOD is increased from 0 to the voltage equal to the voltage of the touch capacitor CX, namely, when the voltage values are all 0.5VDD, the charging process is stopped; when the touch capacitance CX and the capacitance CDC reach equilibrium, the touch capacitance CX reaches a steady state, the average value of the voltages at which the capacitance CMOD is located is 0.5VDD, and the average value of the voltages at which the touch capacitance CX is located is 0.5VDD, so that the quantity of charges transferred from the touch capacitance CX into the capacitance CMOD is 0.5vdd×cx;
(3) Capacitor CDC discharge: when the voltage value VMOD at two ends of the capacitor CMOD is too high in charging voltage, the voltage is input to the comparator CMP through a pin p end of the comparator CMP, the comparator CMP outputs a comparison result signal, the comparison result signal is transmitted to the NAND gate module, a judgment result is input to the trigger through a QN end of the NAND gate module, the trigger generates an adjustment signal according to the judgment result, the adjustment signal adjusts and controls the switch TIII through an output line of a QB end of the trigger through the trigger, the state value of the switch TIII becomes 0, and the switch TIII is disconnected, namely, a line between the capacitor CMOD and the capacitor CDC is in a disconnected state; meanwhile, an adjusting signal is input to the second inverter through the QB end of the trigger pin through the trigger, the second inverter outputs a signal CLK-CDC, the state value of the signal CLK-CDC at the moment is output to be 1, the switch TIV is controlled to be closed through the signal CLK-CDC output by the second inverter, namely, the capacitor CDC is in a communication state with the fourth ground wire, and the capacitor CDC discharges and discharges redundant charges;
when the voltage value VMOD at two ends of the capacitor CMOD is lower, the voltage input into the comparator CMP is sequentially processed and output into an adjusting signal through the NAND gate module and the DFF trigger, the state value of the switch TIII is controlled to be 1, the switch TIII is closed, and the voltage VMOD of the capacitor CMOD is equal to the voltage VCDC of the capacitor CDC; the adjusting signal is input to the second inverter through the trigger, the second inverter outputs signals CLK-CDC, the state value output by CLK_CDC is 0, and the switch TIV is opened;
(4) Counting the number of pulses: the signal CLK-CDC output by the second inverter is simultaneously transmitted to a counter module, and the counter module receives a second fixed clock signal; the CLK-CDC and the second fixed clock signal are subjected to internal counting processing by a counter module, the counter module outputs sampling values, and the sampling values are marked as SAMP [11:0];
(5) Average value calculation: the counter module inputs the SAMP [11:0] into an AVERAGE module of the AVERAGE, and the AVERAGE value STD [11:0] of a plurality of sampling periods is obtained through processing;
(6) And (3) calculating a difference value: the AVERAGE value STD [11:0] is input into the A-B subtracter by the AVERAGE module, the SAMP [11:0] is input into the A-B subtracter by the counter module, and the calculated difference value between the SAMP [11:0] and the STD [11:0] through the A-B subtracter is recorded as DLT [11:0];
(7) And (3) touch judgment: comparing the output DLT [11:0] of the A-B module with a set critical value LN, and when the value of DLT [11:0] is larger than the critical value LN, considering that the capacitor CX is touched; the value range of LN is set to 8-30, and the sensitivity of the touch capacitor CX is selected according to the adjusted LN value.
2. The charge balance touch capacitance monitoring method of claim 1, wherein: the principle method for monitoring the touch capacitance CX by the charge balance type touch capacitance monitoring chip is as follows:
(1) The states of the switch TIII and the switch TIV are reciprocal, in one clock period, when the state value of the switch TIII is 1, the switch TIII is closed to charge the capacitor CDC, the charged charge quantity is 0.5VDD which is the CDC, at the moment, the capacitor CMOD and the capacitor CDC are connected in parallel, and the voltage VMOD at two ends of the capacitor CMOD and the voltage VCDC at two ends of the capacitor CDC are equal; when the state value of the switch TIII is 0, the switch TIII is opened, the state value of the switch TIV is 1, and the switch TIV is closed, so that the capacitor CDC is in a discharging state;
(2) The capacitor CMOD is used as a charging capacitor, and the amount of charge of the first power supply for charging the capacitor CMOD through the switch TI and the switch TII is equal to the amount of charge discharged through the switch TIII and the switch TIV, that is, the amount of charge charged is equal to the amount of charge discharged; the capacitor CMOD discharge is realized through the capacitor CDC discharge, and the voltage at two ends of the capacitor CMOD is equal to the voltage at two ends of the capacitor CDC, so that the voltage value of the capacitor CDC is reduced, and the voltage value of the capacitor CMOD is also reduced; excess charge in capacitor CMOD is discharged through capacitor CDC; assuming that the number of pulses CLK_PRS for charging the capacitor CMOD is M and the number of pulses CLK_CDC for discharging the capacitor CMOD is N, N is the sampling value SAMP [11:0]; from the conservation of charge, the following equation can be obtained:
0.5vdd×m=0.5 vdd×cdc×n, i.e., cx×m=cdc×n; (1)
CX is the capacitance value of the touch capacitance CX, and CDC is the capacitance value of the capacitance CDC;
under the condition that M is fixed, when the touch capacitance CX changes, N can linearly change along with the capacitance, and information of the touch capacitance CX can be obtained by monitoring N; VDD in equation (1) can be about dropped, eventually making DLT [11:0] independent of VDD, i.e., sensitivity independent of VDD, and as long as CDC is adjusted, the sensitivity of monitoring the sensing of the touch capacitance CX can be adjusted.
3. The charge balance touch capacitance monitoring method of claim 1, wherein: the charge balance type touch capacitance monitoring chip comprises a touch channel and a touch judgment module, wherein the touch channel adopts a charge balance type touch capacitance monitor structure, and the touch channel is used for sensing touch; the touch channel is in electrical information connection with the touch judging module, and the touch judging module is used for comparing the data difference value input by the touch channel with a set value, and when the data difference value is larger than the set value, the touch sensing module is judged to be touched.
4. A charge balance touch capacitance monitoring method according to claim 3, characterized in that: the charge balance type touch capacitance monitor comprises a main structure including a touch sensing module, a control analysis module and a data processing module; the touch sensing module, the control analysis module and the data processing module are sequentially connected with each other in an orderly manner; wherein the method comprises the steps of
The touch sensing module is used for constructing a sensing circuit by utilizing a charge balance principle through a touch capacitor and outputting a sensing voltage to the outside;
and a control analysis module: the touch sensing module is used for processing and analyzing the voltage input by the touch sensing module, outputting a control signal, controlling the touch sensing module to operate according to the control signal, and transmitting the control signal to the data processing module;
and a data processing module: the control signal input by the statistical control analysis module is processed and calculated to obtain a data difference value, and the data difference value is input into the touch judgment module.
5. The method for monitoring charge balance type touch capacitance according to claim 4, wherein: the touch sensing module comprises a first clock signal input end, a clock prescaler module (PRS), a first power supply, a first phase inverter, a switch TI, an input pin board, a touch capacitor CX, a first ground wire, a switch TII, a capacitor CMOD, a second ground wire, a capacitor CDC, a third ground wire, a switch TIV, a fourth ground wire and a switch TIII, wherein the first clock signal input end is connected with the input end of the clock prescaler module, the first clock signal input end inputs the first fixed clock signal into the clock prescaler module, the clock prescaler module processes the first fixed clock signal to obtain CLK_PRS pulses, and the clock prescaler module outputs the CLK_PRS pulses; the output of the clock prescaler module is connected with a first inverter and a first contact end of a switch TII in parallel, the output end of the round end of the first inverter is connected with the first contact end of a switch TI, and the connection end of the switch TI is connected with a first power supply; the second contact end of the switch TI is sequentially connected with the touch capacitor CX and the first ground wire in series, and when the second contact end of the switch TI is connected with the external interface of the touch capacitor CX in a closed mode, the first power supply is sequentially connected with the switch TI, the touch capacitor CX and the first ground wire in series and charges the touch capacitor CX; the external interface of the touch capacitor CX is also connected with the output end of an input pin disc, the input pin disc inputs the input of the whole circuit, and the input pin disc is used for receiving external signals and converting the external signals into the touch capacitor CX, wherein the external signals are external touches; the external interface of the touch capacitor CX is also connected with a second contact end of the switch TII, and the connection end of the switch TII is sequentially connected with the input end of the capacitor CMOD, the connection end of the switch TIII and the p end of the comparator CMP pin of the control analysis module in parallel; the capacitor CMOD is connected with the second ground wire in series, the voltage at two ends of the capacitor CMOD is VMOD, and the capacitor CMOD is a collecting capacitor and plays a role in voltage stabilization; when the first contact end of the switch TIII is connected with the first input end of the capacitor CDC in a closed mode, the capacitor CMOD can be connected with the switch TIII, the capacitor CDC and the third ground wire in sequence to form a series circuit; the second input end of the capacitor CDC is connected with the connecting end of the switch TIV, the first contact end of the switch TIV is connected with the fourth ground wire, when the first contact end of the switch TIV is connected with the fourth ground wire, the first contact end of the switch TIII is disconnected with the first input end of the capacitor CDC, and the capacitor CDC discharges to the fourth ground wire through the switch TIV; the switch TIII and the switch TIV are also respectively connected with the control analysis module and controlled by the control analysis module.
6. The method for monitoring charge balance type touch capacitance according to claim 5, wherein: the control analysis module comprises a second power supply, a first resistor, a comparator CMP, a NAND gate module, a fifth ground wire, a trigger, a second inverter, a second resistor, a fifth ground wire and a second clock signal input end, wherein the p end of a pin of the comparator CMP is connected with the connecting end of a switch TII, the N end of a pin of the comparator CMP is connected with the first resistor and the second resistor in parallel, and the resistance values of the first resistor and the second resistor are 100kΩ; the N end of the pin of the comparator CMP obtains the voltage value the same as that of the second resistor; the input end of the first resistor is connected with a second power supply, and the input end of the second resistor is connected with a fifth ground wire in series; the output end of the comparator CMP is connected with the end B of a NAND gate module pin B, the end O of the comparator CMP is the input of the NAND gate module pin B, the end QN of the NAND gate module is connected with the end D of a trigger pin, the output end of the NAND gate module QN is used as the input of the end D of the trigger pin, the end C of the trigger pin is connected with a second clock signal input end, and the second clock signal input end is also connected with the end CLK of a counter module pin of the data processing module; the second clock signal input end and the first clock signal input end receive the same clock signal, and the trigger pin C end receives a second fixed clock signal; the Q end of the trigger is connected with the A end of the pin of the NAND gate module, and the output of the Q end of the trigger is used as the input of the A end of the pin of the NAND gate module; the output of the trigger pin QB end controls the closing state of the switch TIII; the QB end of the trigger pin is also connected with the input end of the second inverter, and the output of the QB end of the trigger pin is processed by the second inverter to obtain a signal CLK-CDC; the output end of the second inverter is connected with the pin INC end of the counter module, and the second inverter inputs CLK_CDC into the pin INC end of the counter module; the output end of the second inverter is also connected with the second contact end of the switch TIV, and the closed state of the switch TIV is controlled through CLK_CDC output by the second inverter.
7. The method for monitoring charge balance type touch capacitance according to claim 6, wherein: the data processing module comprises a counter module, an AVERAGE module and an A-B subtracter, wherein a pin CLK (clock signal) of the counter module receives a second fixed clock signal; the two inputs of the counter module are a signal CLK_CDC and a second fixed clock signal respectively, CLK is a clock signal with fixed frequency, the two signals are counted and processed in the counter module, the counter module outputs a sampling value mark as SAMP [11:0], wherein [11:0] represents that the number of bits of sampling is 12; the output end of the counter module is connected with the input end of the AVERAGE module, SAMP [11:0] is used as the input of the AVERAGE module, and the AVERAGE value STD [11:0] of a plurality of sampling periods is obtained through processing; the output end of the AVERAGE module of AVERAGE is connected with pin B end of A-B subtracter, AVERAGE module of AVERAGE inputs AVERAGE STD [11:0] into pin B end of A-B subtracter; the output end of the counter module is also connected with the pin A end of the A-B subtracter, and after being processed by the A-B subtracter, the SAMP [11:0] and the STD [11:0] are output as DLT [11:0].
8. The method for charge balance touch capacitance monitoring of claim 7, wherein: the switch TI, the switch TII, the switch TIII and the switch TIV are ideal switches.
9. The method of charge balance touch capacitance monitoring of claim 8, wherein: the charge balance type touch capacitance monitoring chip also comprises a sampling channel and a trimming module, wherein the sampling channel adopts a charge balance type touch capacitance monitor structure, the output ends of the sampling channel and the touch channel are respectively in information connection with the receiving end of the trimming module, and the output end of the trimming module is in information connection with the receiving end of the touch judging module;
the sampling channel is used for acquiring data detected by the charge balance type touch capacitance monitor under the condition of no touch;
the trimming module is used for trimming the data acquired by the touch channel, eliminating interference factors under the condition of no touch, and inputting the trimmed acquired data into the touch judgment module.
10. The charge balance touch capacitance monitoring method of claim 9, wherein: the trimming module has the structure that: the trimming module comprises a DIV12BIT module, a MUL12BIT module and a SUB12BIT module, wherein the DIV12BIT module is provided with a pin A and a pin B, the pin A of the DIV12BIT module obtains an input SAMP0_ [11:0], SAMP0_ [11:0] is a current sampling value in a sampling channel, the pin B of the DIV12BIT module obtains an input STD0_ [11:0], STD0_ [11:0] is an average value of current sampling in the sampling channel, and the SAMP0_ [11:0] and the STD0_ [11:0] are output as DIV [12:0] after being internally processed by the DIV12BIT module; the output end of the DIV12BIT module is connected with a pin B of the MUL12BIT module, and the MUL12BIT module is provided with a pin A and a pin B; DIV [12:0] is used as the input of pin B in the MUL12BIT module, and the input of pin A of the MUL12BIT module is the average value STD1_ [11:0] of the touch channel; DIV [12:0], STD1_ [11:0] are internally processed by the MUL12BIT module and then output as STD1_VAL [11:0], and STD1_VAL [11:0] is the average value of the touch channels after trimming; the output end of the MUL12BIT module is connected with a pin B of the SUB12BIT module, STD1_VAL [11:0] is used as the input of the pin B of the SUB12BIT module, the input SAMP1_11:0 of the pin A of the SUB12BIT module is the current sampling value of the touch channel, and after the STD1_VAL [11:0] and the SAMP1_11:0 ] are processed in the SUB12BIT module, DLT1_11:0 is output; the output DLT1_ [11:0] is the difference value of the touch channel after trimming, and the final output difference value is compared with LN to judge whether the touch capacitor CX is touched or not; when DLT1_ [11:0] is larger than LN, touch is considered, the value range of LN is set between 8 and 30, and the trimming module adopts a calculation formula of a trimming algorithm as follows:
DIV[12:0]＝SAMP0_[11:0]/STD0_[11:0]
STD1_VAL[11:0]＝STD1_[11:0]*DIV[12:0]
DLT1_[11:0]＝SAMP01_[11:0]-STD1_VAL[11:0]。
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