CN116471837A

CN116471837A - Semiconductor structure, memory structure and preparation method thereof

Info

Publication number: CN116471837A
Application number: CN202310271342.6A
Authority: CN
Inventors: 石峰; 平延磊; 贾礼宾; 周俊; 田超
Original assignee: Beijing Superstring Academy of Memory Technology
Current assignee: Beijing Superstring Academy of Memory Technology
Priority date: 2023-03-16
Filing date: 2023-03-16
Publication date: 2023-07-21
Anticipated expiration: 2043-03-16
Also published as: CN116471837B

Abstract

The application relates to a semiconductor structure, a memory structure and a preparation method thereof. The preparation method of the semiconductor structure comprises the following steps: providing a substrate; forming a plurality of patterning structures which are arranged at intervals, wherein the patterning structures are positioned in or on the substrate; the patterning structure is provided with a region to be doped, and the region to be doped is at least spaced from the bottom of the patterning structure; forming a first dielectric layer in the gap between the adjacent patterned structures, wherein the upper surface of the first dielectric layer is not higher than the bottom of the region to be doped; forming a doped layer at least on the side wall of the region to be doped; and carrying out heat treatment on the obtained structure so as to diffuse doped particles in the doped layer into the region to be doped to form a doped region. The preparation method of the semiconductor structure has high doping utilization rate, the doping position can be accurately controlled, and the contact resistance can be reduced.

Description

Semiconductor structure, memory structure and preparation method thereof

Technical Field

The present disclosure relates to the field of semiconductor technologies, and in particular, to a semiconductor structure, a memory structure, and a method for manufacturing the same.

Background

With the development of semiconductor process technology, the improvement of the contact resistance of the bit line of the device is receiving a great deal of attention. In order to reduce the contact resistance of the bit line of the device, particle doping is usually performed in the substrate at the bottom of the trench, and then doped particles are diffused to the bottom end of the patterned structure through annealing, but the distance between the substrate at the bottom of the trench and the bottom end of the patterned structure is far, so that high-concentration and accurate doping cannot be realized, the problems of low doping utilization rate, incapability of accurately controlling the doping position and the like are caused, and the performance of the device is affected.

Disclosure of Invention

Based on this, it is necessary to provide a semiconductor structure, a memory structure and a method for manufacturing the same in order to solve the above-mentioned problems.

In a first aspect, the present application provides a method for preparing a semiconductor structure, including:

providing a substrate;

forming a plurality of patterning structures which are arranged at intervals, wherein the patterning structures are positioned in the substrate or on the substrate; the patterning structure is provided with a region to be doped, and the region to be doped is at least spaced from the bottom of the patterning structure;

forming a first dielectric layer in a gap between adjacent patterned structures, wherein the upper surface of the first dielectric layer is not higher than the bottom of the region to be doped;

forming a doped layer at least on the side wall of the region to be doped;

and carrying out heat treatment on the obtained structure so as to enable doped particles in the doped layer to diffuse into the region to be doped to form a doped region.

In one embodiment, a plurality of patterned structures are formed in a spaced arrangement, the patterned structures being located within the substrate, including:

forming a plurality of first grooves which are arranged at intervals along a first direction in the substrate, wherein the first grooves isolate the substrate into a plurality of active walls which are arranged at intervals along the first direction, the active walls extend along a second direction, the active walls are provided with areas to be doped, and the areas to be doped are spaced from the top of the active walls and the bottom of the active walls; the second direction intersects the first direction.

In one embodiment, the forming a doped layer on at least the sidewall of the region to be doped includes:

forming a doped material layer in the first groove and on the upper surface of the substrate; the doped material layer covers the upper surface of the substrate and fills the first groove;

and removing the doped material layer positioned on the upper surface of the substrate, and back-etching the doped material layer positioned in the first groove to obtain the doped layer.

In one embodiment, after the forming of the doped layer on at least the sidewall of the region to be doped, before the heat treatment of the obtained structure, the method further includes:

and forming a second dielectric layer in the first groove and on the upper surface of the substrate, wherein the first groove is filled with the second dielectric layer.

In one embodiment, forming a doped layer on at least the sidewall of the region to be doped includes:

forming a doped material layer on the upper surface of the first dielectric layer, the side wall of the first groove and the upper surface of the substrate;

forming a medium filling material layer on the upper surface of the doped material layer;

and removing the filling dielectric material layer positioned on the upper surface of the substrate and the doping material layer positioned on the upper surface of the substrate, and back-etching the filling dielectric material layer positioned in the first groove and the doping material layer positioned in the first groove to form the doping layer and the first filling dielectric layer, wherein the upper surface of the first filling dielectric layer is lower than the top of the first groove.

forming a second filling medium layer in the first groove and on the upper surface of the substrate, wherein the first groove is filled with the second filling medium layer; the second filling medium layer and the first filling medium layer are used together as a second medium layer.

In one embodiment, after the heat treatment is performed on the obtained structure to enable the doped particles in the doped layer to diffuse into the region to be doped to form a doped region, the method further includes:

and removing the second dielectric layer, the residual doped layer and the first dielectric layer.

In one embodiment, after the removing the second dielectric layer, the remaining doped layer, and the first dielectric layer, the method further includes:

filling a first isolation medium layer in the first groove;

etching the first isolation medium layer and the active wall to form a plurality of second grooves which are arranged at intervals along the second direction, wherein the second grooves extend along the first direction so as to divide the active wall into a plurality of active columns which are arranged at intervals; the doped region is positioned at the lower part of each active column;

Etching the substrate to form a plurality of bit line grooves which are arranged at intervals along the first direction in the substrate, wherein the bit line grooves extend along the second direction; the bit line trench is positioned below the doped region;

and forming a bit line in the bit line groove.

In one embodiment, the active pillar further includes a first connection terminal, a channel region, and a second connection terminal connected in sequence; the first connecting end is positioned on the doped region and is contacted with the doped region; the channel region is positioned at one side of the first connecting end far away from the doped region and is contacted with the first connecting end; the second connecting end is positioned at one side of the channel region away from the first connecting end and is contacted with the channel region; after the bit line is formed in the bit line trench, the method further comprises:

forming a second isolation medium layer in the second groove;

etching back part of the second isolation medium layer to expose the second connection end and the channel region;

and forming word lines on the surface of the channel region, wherein the word lines extend along the first direction so as to cover the channel regions of the active pillars positioned in the same row.

In one embodiment, the patterned structure comprises a gate structure;

forming a plurality of patterned structures arranged at intervals, wherein the patterned structures are positioned on the substrate and comprise: forming a plurality of gate structures which are arranged at intervals on the upper surface of the substrate;

forming a doped layer on at least the side wall of the region to be doped, comprising: and forming the doping layer on the upper surface of the first dielectric layer, the upper surface of the gate structure and the exposed side wall of the gate structure.

In one embodiment, the patterned structure comprises a fin structure;

forming a plurality of patterned structures arranged at intervals, wherein the patterned structures are positioned in the substrate and comprise: etching the substrate to form a plurality of fin structures which are arranged at intervals in the substrate;

forming a doped layer on at least the side wall of the region to be doped, comprising: and forming the doping layer on the upper surface of the first dielectric layer, the upper surface of the fin-shaped structure and the exposed side wall of the fin-shaped structure.

In a second aspect, the present application also provides a semiconductor structure, the semiconductor structure comprising:

a substrate;

the patterning structure is internally provided with a doping region, and the doping region is at least spaced from the bottom of the patterning structure.

In one embodiment, the patterned structure includes an active pillar including a first connection terminal, a channel region, and a second connection terminal; the first connecting end is positioned on the doped region and is contacted with the doped region; the channel region is positioned at one side of the first connecting end far away from the doped region and is contacted with the first connecting end; the second connecting end is positioned at one side of the channel region away from the first connecting end and is contacted with the channel region; the semiconductor structure further includes:

a plurality of bit lines arranged at intervals along a first direction, wherein the bit lines are positioned below the active columns, and each bit line extends along a second direction so as to serially connect the doped regions of the active columns positioned in the same column in sequence; the second direction intersects the first direction.

In one embodiment, the substrate is provided with a first groove and a second groove, and the first groove and the second groove are isolated to form a plurality of active columns which are arranged at intervals; the first groove extends along the second direction, and the second groove extends along the first direction; the semiconductor structure further includes:

the first isolation medium layer is positioned in the first groove;

The second isolation medium layer is positioned in the second groove, and the first isolation medium layer and the second isolation medium layer jointly cover the first connection end of each active column and the doped region of each active column;

and a word line cladding the channel region of the active pillars in the same row.

In one embodiment, the patterned structure comprises a gate structure, the gate structure being located on an upper surface of the substrate; the semiconductor structure further includes:

a source region located within the substrate and located on one side of the gate structure;

and the drain region is positioned in the substrate and is positioned at one side of the grid structure away from the source region.

In one embodiment, the patterned structure includes a fin structure, the fin structure being located within the substrate.

In a third aspect, the present application further provides a method for manufacturing a memory structure, including:

preparing the semiconductor structure by adopting the preparation method of the semiconductor structure;

forming a plurality of storage node structures, wherein the storage node structures are positioned above the second connecting ends of the active columns and are connected with the second connecting ends in a one-to-one correspondence manner;

And forming a plurality of capacitors, wherein the capacitors are positioned on the upper surface of the storage node structure and are arranged in one-to-one correspondence with the storage node structure.

In a fourth aspect, the present application further provides a memory structure, the memory structure comprising:

a semiconductor structure as described above;

the storage node structures are positioned above the second connecting ends of the active columns and are connected with the second connecting ends in a one-to-one correspondence manner;

the capacitors are positioned on the upper surface of the storage node structure and are arranged in one-to-one correspondence with the storage node structure.

According to the preparation method of the semiconductor structure and the semiconductor structure, the patterning structures are arranged at intervals in the substrate, the patterning structures are provided with the regions to be doped, and the doped layers are at least formed on the side walls of the regions to be doped, so that after the doped layers are formed, doped particles in the doped layers are diffused into the regions to be doped to form the doped regions through heat treatment, the doped particles of the doped layers are directly diffused into the active walls, the substrate is not needed, the diffusion distance of the doped particles is short, the doping utilization rate is high, and the high-concentration doped regions can be obtained in the patterning structures, so that the active columns, the gates or the fin-shaped structures with high-concentration doping can be obtained later; the first dielectric layer is formed in the gaps between the patterned structures, so that the upper and lower positions of the doped layers can be correspondingly adjusted by adjusting the thickness of the first dielectric layer, and the doped positions can be accurately controlled; the doped region is spaced from the bottom of the patterned structure, and is not removed when the partial structure at the bottom of the patterned structure needs to be removed in the subsequent process, so that the doped region can be at least partially reserved in the patterned structure, and the purpose of reducing contact resistance is achieved.

According to the preparation method of the memory structure and the memory structure, the semiconductor structure is prepared by adopting the preparation method of the semiconductor structure, and comprises a substrate and a plurality of graphical structures which are arranged at intervals, and a doped region is positioned in the graphical structures so as to obtain an active column, a grid or a fin-shaped structure and the like with high-concentration doping at a later time, so that the doping utilization rate is high; the doped region is at least spaced from the bottom of the patterned structure, and is not removed when the partial structure at the bottom of the patterned structure needs to be removed in the subsequent process, so that the doped region can be at least partially reserved in the patterned structure, and the purpose of reducing contact resistance is achieved; the first dielectric layer is formed in the gaps between the patterned structures, so that the upper and lower positions of the doped layers can be correspondingly adjusted by adjusting the thickness of the first dielectric layer, and the doped positions can be accurately controlled.

Drawings

In order to more clearly illustrate the technical solutions of embodiments or conventional techniques of the present application, the drawings required for the descriptions of the embodiments or conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.

FIG. 1 is a flow chart of a method for fabricating a semiconductor structure according to one embodiment;

FIG. 2 is a schematic top view of a semiconductor structure according to one embodiment;

fig. 3 is a schematic perspective view of a structure obtained in step S102 in a method for manufacturing a semiconductor structure according to an embodiment;

FIG. 4 (a) is a schematic cross-sectional view taken along aa' in FIG. 3; fig. 4 (b) is a schematic cross-sectional structure along the bb' direction shown in fig. 3; fig. 4 (c) is a schematic sectional structure along the direction cc 'shown in fig. 3, and fig. 4 (d) is a schematic sectional structure along the direction dd' shown in fig. 3;

FIG. 5 is a schematic cross-sectional view of a structure obtained by removing a first dielectric material layer on a surface of a substrate in a method for fabricating a semiconductor structure according to one embodiment;

FIG. 6 (a) is a schematic cross-sectional view taken along the aa' direction shown in FIG. 5; fig. 6 (b) is a schematic cross-sectional structure along the bb' direction shown in fig. 5; fig. 6 (c) is a schematic sectional structure along the direction cc 'shown in fig. 5, and fig. 6 (d) is a schematic sectional structure along the direction dd' shown in fig. 5;

fig. 7 is a schematic perspective view of a structure obtained in step S103 in the method for manufacturing a semiconductor structure according to an embodiment;

FIG. 8 (a) is a schematic cross-sectional view taken along the aa' direction shown in FIG. 7; fig. 8 (b) is a schematic cross-sectional structure along the bb' direction shown in fig. 7; fig. 8 (c) is a schematic sectional structure along the direction cc 'shown in fig. 7, and fig. 8 (d) is a schematic sectional structure along the direction dd' shown in fig. 7;

fig. 9 is a schematic flow chart of step S104 in the method for manufacturing a semiconductor structure according to an embodiment;

fig. 10 is a schematic perspective view of a structure obtained in step S1041 in the method for manufacturing a semiconductor structure according to an embodiment;

FIG. 11 (a) is a schematic cross-sectional view taken along the aa' direction shown in FIG. 10; fig. 11 (b) is a schematic cross-sectional structure along the bb' direction shown in fig. 10; fig. 11 (c) is a schematic sectional structure along the direction cc 'shown in fig. 10, and fig. 11 (d) is a schematic sectional structure along the direction dd' shown in fig. 10;

fig. 12 is a schematic perspective view of a structure obtained in step S1042 in the method for manufacturing a semiconductor structure according to an embodiment;

FIG. 13 (a) is a schematic cross-sectional view taken along the aa' direction shown in FIG. 12; fig. 13 (b) is a schematic cross-sectional structure along the bb' direction shown in fig. 12; fig. 13 (c) is a schematic sectional structure along the direction cc 'shown in fig. 12, and fig. 13 (d) is a schematic sectional structure along the direction dd' shown in fig. 12;

FIG. 14 is a schematic cross-sectional view of a structure obtained by forming a second dielectric layer in a first trench and on an upper surface of a substrate in the method for fabricating a semiconductor structure according to one embodiment along aa ', bb', cc 'and dd' directions shown in FIG. 2;

FIG. 15 is a schematic cross-sectional view of the structure obtained in step S105 along aa ', bb', cc 'and dd' directions shown in FIG. 2 in a method for fabricating a semiconductor structure according to an embodiment;

FIG. 16 is a schematic cross-sectional view of a structure obtained by removing a second dielectric layer on a surface of a substrate in the aa ', bb', cc 'and dd' directions shown in FIG. 2 in a method for fabricating a semiconductor structure according to an embodiment;

FIG. 17 is a schematic diagram showing a perspective structure of a semiconductor structure obtained by removing a second dielectric layer, a residual doped layer and a first dielectric layer in the method for fabricating a semiconductor structure according to an embodiment;

FIG. 18 (a) is a schematic view showing a sectional structure along the aa' direction shown in FIG. 17; fig. 18 (b) is a schematic cross-sectional structure along the bb' direction shown in fig. 17; fig. 18 (c) is a schematic sectional structure along the direction cc 'shown in fig. 17, and fig. 18 (d) is a schematic sectional structure along the direction dd' shown in fig. 17;

FIG. 19 is a flow chart of a method of fabricating a semiconductor structure provided in another embodiment;

fig. 20 is a schematic diagram showing a three-dimensional structure of the structure obtained in step S106 in the method for manufacturing a semiconductor structure according to an embodiment;

fig. 21 is a schematic diagram showing a three-dimensional structure of a structure obtained in step S107 in the method for manufacturing a semiconductor structure according to an embodiment;

FIG. 22 (a) is a schematic cross-sectional view taken along the aa' direction shown in FIG. 21; fig. 22 (b) is a schematic cross-sectional structure along the bb' direction shown in fig. 21; fig. 22 (c) is a schematic sectional structure along the direction cc 'shown in fig. 21, and fig. 22 (d) is a schematic sectional structure along the direction dd' shown in fig. 21;

FIG. 23 is a schematic cross-sectional view of the structure obtained in step S108 along aa ', bb', cc 'and dd' directions shown in FIG. 2 in a method for fabricating a semiconductor structure according to an embodiment;

FIG. 24 is a schematic cross-sectional view of the structure obtained in step S109 along the aa ', bb', cc 'and dd' directions shown in FIG. 2 in a method for fabricating a semiconductor structure according to an embodiment;

FIG. 25 is a flow chart of a method of fabricating a semiconductor structure provided in another embodiment;

FIG. 26 is a schematic cross-sectional view of the structure obtained in step S110 along aa ', bb', cc 'and dd' directions shown in FIG. 2 in a method for fabricating a semiconductor structure according to an embodiment;

FIG. 27 is a schematic cross-sectional view of the structure obtained in step S111 along aa ', bb', cc 'and dd' directions shown in FIG. 2 in a method for fabricating a semiconductor structure according to an embodiment;

FIG. 28 is a schematic cross-sectional view of the structure obtained in step S112 along aa ', bb', cc 'and dd' directions shown in FIG. 2 in a method for fabricating a semiconductor structure according to an embodiment;

fig. 29 is a flowchart illustrating a step of step S104 in the method for manufacturing a semiconductor structure according to another embodiment;

FIG. 30 is a schematic cross-sectional view of the structure obtained in step S1041 in the method for fabricating a semiconductor structure according to another embodiment along aa ', bb', cc 'and dd' directions shown in FIG. 2;

FIG. 31 is a schematic cross-sectional view of the structure obtained in step S1042 in the method for fabricating a semiconductor structure according to another embodiment along aa ', bb', cc 'and dd' directions shown in FIG. 2;

FIG. 32 is a schematic cross-sectional view of the structure obtained in step S1043 in the method for fabricating a semiconductor structure according to an embodiment along aa ', bb', cc 'and dd' directions shown in FIG. 2;

FIG. 33 is a schematic cross-sectional view of the structure obtained in step S105 along the aa ', bb', cc 'and dd' directions shown in FIG. 2 in another embodiment of a method for fabricating a semiconductor structure;

fig. 34 is a schematic cross-sectional structure of a structure obtained in step S102 in a method for manufacturing a semiconductor structure according to another embodiment;

fig. 35 is a schematic cross-sectional structure of the structure obtained in step S103 in the method for manufacturing a semiconductor structure according to another embodiment;

fig. 36 is a schematic cross-sectional view of a structure obtained in step S104 in a method for manufacturing a semiconductor structure according to another embodiment;

fig. 37 is a schematic cross-sectional view of a structure obtained in step S105 in a method for manufacturing a semiconductor structure according to another embodiment;

fig. 38 is a schematic cross-sectional structure of a structure obtained in step S102 in a method for manufacturing a semiconductor structure according to another embodiment;

fig. 39 is a schematic cross-sectional structure of a structure obtained in step S103 in a method for manufacturing a semiconductor structure according to another embodiment;

fig. 40 is a schematic cross-sectional structure of a structure obtained in step S104 in a method for manufacturing a semiconductor structure according to another embodiment;

fig. 41 is a schematic cross-sectional structure of a structure obtained in step S105 in a method for manufacturing a semiconductor structure according to another embodiment;

FIG. 42 is a flow chart illustrating steps of a method for fabricating a memory structure according to an embodiment.

Reference numerals illustrate:

100. a substrate; 101. a first dielectric material layer; 102. a doped material layer; 103. shallow trench isolation structures; 105. filling a dielectric material layer; 111. a first trench; 11. a first dielectric layer; 12. a doped layer; 13. a second dielectric layer; 14. a first isolation dielectric layer; 15. a first filling medium layer; 16. a second filling medium layer; 20. an active column; 21. an active wall; 201. a region to be doped; 202. a first connection end; 203. a channel region; 204. a second connection end; 211. a doped region; 30. a second trench; 31. a second isolation dielectric layer; 32. a word line; 4. a bit line; 40. bit line trenches; 51. a gate structure; 52. a source region; 53. a drain region; 6. fin-shaped structures.

Detailed Description

In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section.

Spatially relative terms, such as "under", "below", "beneath", "under", "above", "over" and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein interpreted accordingly.

As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.

With the development of semiconductor process technology, the improvement of the contact resistance of the bit line of the device is receiving a great deal of attention. In order to reduce the contact resistance of the bit line of the device, particle doping is usually performed in the substrate at the bottom of the trench, and then doped particles are diffused to the bottom end of the active column by annealing, but the distance between the substrate at the bottom of the trench and the bottom end of the active column is far, so that high-concentration and accurate doping cannot be realized, the problems of low doping utilization rate, incapability of accurately controlling the doping position and the like are caused, and the performance of the device is affected.

As shown in fig. 1, the present application provides a method for preparing a semiconductor structure, which may include the following steps:

s101: providing a substrate;

s102: forming a plurality of patterning structures which are arranged at intervals, wherein the patterning structures are positioned in or on the substrate; the patterning structure is provided with a region to be doped, and the region to be doped is at least spaced from the bottom of the patterning structure;

s103: forming a first dielectric layer in the gap between the adjacent patterned structures, wherein the upper surface of the first dielectric layer is not higher than the bottom of the region to be doped;

s104: forming a doped layer at least on the side wall of the region to be doped;

S105: and carrying out heat treatment on the obtained structure so as to diffuse doped particles in the doped layer into the region to be doped to form a doped region.

Wherein the patterned structure is located in or on the substrate, which means that the patterned structure may be located in or on the substrate; the patterned structure is located on the substrate, which means that the patterned structure may be directly located on the upper surface of the substrate, or other structural layers may be further disposed between the patterned structure and the upper surface of the substrate.

The semiconductor structure obtained after the steps S101 to S105 may be referred to fig. 15, 33, 37 or 41. Of course, in order to facilitate understanding of the present invention, fig. 15, 33, 37 or 41 show some examples of semiconductor structures prepared by the method for preparing a semiconductor structure according to the present invention, and other suitable examples of semiconductor structures prepared by the method for preparing a semiconductor structure according to the present invention may be used, which are not limited herein.

In the method for manufacturing a semiconductor structure in the above embodiment, a plurality of patterned structures are formed in a substrate at intervals, the patterned structures have regions to be doped, and a doped layer is formed at least on the side walls of the regions to be doped, so that after the doped layer is formed, doped particles in the doped layer are diffused into the regions to be doped to form the doped regions by heat treatment, the doped particles of the doped layer are directly diffused into the active walls, the doped particles do not need to pass through the substrate, the diffusion distance of the doped particles is short, the doping utilization rate is high, and the doped regions with high concentration can be obtained in the patterned structures, so that active columns, gates or fin structures with high concentration doping can be obtained later; the first dielectric layer is formed in the gaps between the patterned structures, so that the upper and lower positions of the doped layers can be correspondingly adjusted by adjusting the thickness of the first dielectric layer, and the doped positions can be accurately controlled; the doped region is spaced from the bottom of the patterned structure, and is not removed when the partial structure at the bottom of the patterned structure needs to be removed in the subsequent process, so that the doped region can be at least partially reserved in the patterned structure, and the purpose of reducing contact resistance is achieved.

Referring to fig. 2, fig. 2 shows aa 'direction, bb' direction, cc 'direction, and dd' direction of the semiconductor structure in the present application.

Referring to fig. 3 and 4, in step S101, a substrate 100 is provided.

In the coordinate system shown in fig. 3, the x-axis direction represents the first direction, and the y-axis direction represents the second direction.

In the method for manufacturing a semiconductor structure provided in the present application, the material of the substrate 100 is not particularly limited. By way of example, the material of the substrate 100 may be any suitable material, for example, at least one of the following mentioned materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN), or other III/V compound semiconductors, and also include multilayer structures formed of these semiconductors, or the like, or are silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), germanium-on-insulator (GeOI), or the like, or may be Double polished silicon wafer (Double Side PolishedWafers, DSP), and the like, and the present embodiment is not limited thereto.

In one embodiment, the patterned structure may include active walls 21. With continued reference to fig. 3 and fig. 4, in step S102, a plurality of patterned structures arranged at intervals are formed, wherein the patterned structures are located in the substrate 100, and may include: forming a plurality of first trenches 111 in the substrate 100, wherein the first trenches 111 isolate the substrate 100 from a plurality of active walls 21, the active walls 21 extend along a second direction, the active walls 21 have regions 201 to be doped, and the regions 201 to be doped have a distance from the top of the active walls 21 and the bottom of the active walls 21; the second direction intersects the first direction.

Note that the first trench 111 may extend in the second direction; the first trench 111 is a gap between adjacent patterned structures.

In some examples, the second direction may be perpendicular to the first direction.

The method for manufacturing the semiconductor structure provided in the present application is not particularly limited as to the manner of forming the first trench 111 in step S102. As an example, the first trench 111 may be formed in the substrate 100 using a Self-aligned double imaging (Self-aligned Double Patterning, abbreviated as SADP) process or a Self-aligned quad pattern (Self-Aligned Quadruple Pattern, abbreviated as SADP) process.

Illustratively, forming a plurality of first trenches 111 spaced apart along a first direction in the substrate 100 may include the steps of: forming a first mask material layer on the surface of the substrate 100; forming a first photoresist layer on a surface of the first mask material layer away from the substrate 100; exposing and developing the first photoresist layer to obtain a first patterned photoresist layer, wherein the first patterned photoresist layer is provided with a first opening; etching the first mask material layer based on the first patterned photoresist layer to obtain a first patterned mask layer, wherein the first patterned mask layer is provided with a second opening, and the first opening defines the shape and the position of the second opening; removing the first patterned photoresist layer; the substrate 100 is etched based on the first patterned mask layer to form a plurality of first trenches 111 in the substrate 100, which are spaced apart along the first direction, wherein the second openings define the shape and location of the first trenches 111.

The first mask material layer may be formed on the surface of the substrate 100 by a physical vapor deposition (Physical Vapor Deposition, abbreviated as PVD) process, a chemical vapor deposition (Chemical Vapor Deposition, abbreviated as CVD) process, or an atomic layer deposition (Atomic Layer Deposition, abbreviated as ALD) process, and the first mask material layer may include a silicon nitride layer or a silicon oxynitride layer, or may include a stacked structure of a silicon nitride layer and a silicon oxynitride layer. The spin coating method may be used to form a first photoresist layer on the surface of the first mask material layer away from the substrate 100, where the first photoresist layer may include a positive photoresist layer or a negative photoresist layer. Methods of removing the first patterned photoresist layer may include, but are not limited to, ashing processes.

In the above embodiment, the first patterned mask layer is obtained based on the first patterned photoresist layer, and the first opening of the first patterned photoresist layer has an accurate shape and size, so that the second opening of the obtained first patterned mask layer also has an accurate shape and size, so that the first trench 111 obtained by etching the substrate 100 based on the first patterned mask layer also has an accurate shape and size.

Referring to fig. 5 to 8, in step S103, a first dielectric layer 11 is formed in the gaps between the adjacent patterned structures, and the upper surface of the first dielectric layer 11 is not higher than the bottom of the to-be-doped region 201, which may include: a first dielectric layer 11 is formed in the first trench 111, and an upper surface of the first dielectric layer 11 is not higher than a bottom of the region 201 to be doped.

The forming of the first dielectric layer 11 in the first trench 111 may include the following steps: forming a first dielectric material layer 101 in the first trench 111 and on the surface of the substrate 100; removing the first dielectric material layer 101 located on the surface of the substrate 100, as shown in fig. 5 and 6; the first dielectric material layer 101 located in the first trench 111 is etched back, and a portion of the first dielectric material layer 101 located in the first trench 111 remains as the first dielectric layer 11, as shown in fig. 7 and 8.

As an example, an oxide layer may be formed as the first dielectric material layer 101 within the first trench 111 and on the surface of the substrate 100 using, but not limited to, a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process. A chemical mechanical polishing process may be used to remove the first dielectric material layer 101 located on the surface of the substrate 100; methods employed to etch back the first dielectric material layer 101 located within the first trench 111 may include, but are not limited to, a dry etching process or a wet etching process.

The material of the first dielectric layer 11 is not particularly limited in this application. As an example, the first dielectric layer 11 may include, but is not limited to, a first oxide layer, which may include, but is not limited to, a silicon oxide layer.

Referring to fig. 9 to 13, in step S104, a doped layer 12 is formed at least on the sidewall of the region 201 to be doped.

In one embodiment, as shown in fig. 9, step S104 may include the following steps:

s1041: forming a doped material layer 102 in the first trench 111 and on the upper surface of the substrate 100; the doped material layer 102 covers the upper surface of the substrate 100 and fills the first trench 111; the resulting structure is shown in fig. 10 and 11.

S1042: removing the doped material layer 102 on the upper surface of the substrate 100, and back-etching the doped material layer 102 in the first trench 111 to obtain a doped layer 12; the resulting structure is shown in fig. 12 and 13.

The doped layer 12 may include a borosilicate glass layer or a phosphosilicate glass layer, among others.

By way of example, a Plasma enhanced atomic layer deposition (Plasma-Enhanced Atomic Layer Deposition, PEALD) process or a chemical vapor deposition process may be employed, with a boron source gas being incorporated in the deposition of the silicon oxide gas to obtain a borosilicate glass layer as the doped material layer 102; or a phosphorus source gas is doped at the time of depositing the silicon oxide gas to obtain a phosphosilicate glass layer as the doping material layer 102.

Referring to fig. 14, after forming the doped layer 12 at least on the sidewall of the region 201 to be doped, before performing the heat treatment on the obtained structure, the method may further include: and forming a second dielectric layer 13 in the first trench 111 and on the upper surface of the substrate 100, wherein the second dielectric layer 13 fills the first trench 111.

The material of the second dielectric layer 13 is not particularly limited in this application. As an example, the second dielectric layer 13 may include, but is not limited to, a second oxide layer; the second oxide layer may include, but is not limited to, a silicon oxide layer.

As an example, a second oxide layer may be formed as the second dielectric layer 13 within the first trench 111 and on the upper surface of the substrate 100 using, but not limited to, a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process.

Referring to fig. 15, in step S105, the obtained structure is subjected to a heat treatment to diffuse the doped particles in the doped layer 12 into the region 201 to be doped to form a doped region 211.

Wherein the doped region 211 comprises a boron doped region or a phosphorus doped regionA zone. The doped region 211 is a boron doped region, and the doping concentration of boron element in the doped region 211 is 1E17cm ^-3 ～1E22cm ^-3 The method comprises the steps of carrying out a first treatment on the surface of the The doped region 211 is a phosphorus doped region, and the doping concentration of phosphorus element in the doped region 211 is 1E17cm ^-3 ～6E21cm ^-3 。

Exemplary, the doped region 211 is a boron doped region, the doping concentration of boron element in the doped region 211 is 1E17cm ^-3 、1E18cm ^-3 、1E19cm ^-3 、1E20cm ^-3 、1E21cm ^-3 Or 1E22cm ^-3 Other 1E17cm may be used ^-3 ～1E22cm ^-3 The doping concentration therebetween is not limited by the example. The doped region 211 is a phosphorus doped region, and the doping concentration of phosphorus element in the doped region 211 is 1E17cm ^-3 、1E18cm ^-3 、1E19cm ^-3 、1E20cm ^-3 、1E21cm ^-3 、2E21cm ^-3 、3E21cm ^-3 、4E21cm ^-3 、5E21cm ^-3 Or 6E21cm ^-3 Other 1E17cm may be used ^-3 ～6E21cm ^-3 The doping concentration therebetween is not limited by the example.

Wherein the doping concentration may be controlled by controlling the concentration of the particles incorporated when forming the doped layer 12 and/or the thickness of the doped layer 12 formed.

Specifically, the doping concentration may be controlled by controlling the concentration of the particles doped when forming the doped layer 12, or by controlling the thickness of the doped layer 12 formed, or by controlling both the concentration of the particles doped when forming the doped layer 12 and the thickness of the doped layer 12.

Referring to fig. 16 to fig. 18, in one embodiment, after performing a heat treatment on the obtained structure to diffuse the doped particles in the doped layer 12 into the region 201 to be doped to form a doped region 211, the method further includes: and removing the second dielectric layer 13, the residual doped layer 12 and the first dielectric layer 11.

As an example, the second dielectric layer 13 located on the surface of the substrate 100 may be removed by a chemical mechanical polishing process, and then the second dielectric layer 13, the remaining doped layer 12, and the first dielectric layer 11 located in the first trench 111 may be removed by a dry etching process or a wet etching process; the structure obtained by removing the second dielectric layer 13 on the surface of the substrate 100 can be referred to as fig. 16.

Referring to fig. 19, after removing the second dielectric layer 13, the residual doped layer 12 and the first dielectric layer 11, the method for manufacturing the semiconductor structure may further include the following steps:

s106: filling the first trench 111 with a first isolation dielectric layer 14; the resulting structure is shown in FIG. 20.

S107: etching the first isolation dielectric layer 14 and the active wall 21 to form a plurality of second trenches 30 arranged at intervals along the second direction, wherein the second trenches 30 extend along the first direction to divide the active wall 21 into a plurality of active columns 20 arranged at intervals; the doped regions 211 are located at the lower portions of the respective active pillars 20; the resulting structure is shown in fig. 21 and 22.

S108: etching the substrate 100 to form a plurality of bit line trenches 40 in the substrate 100, the bit line trenches 40 extending in a second direction; bit line trench 40 is located below doped region 211; the resulting structure is shown in FIG. 23.

S109: forming a bit line 4 in the bit line trench 40; the resulting structure is shown in FIG. 24.

After step S108, the patterned structure is converted from the active wall 21 to the active column 20. The doped region 211 is located inside each active column 20 and at a position below each active column 20. The bit lines 4 are located below the active pillars 20, and the doped regions 211 of the active pillars 20 located in the same column may be sequentially connected in series to achieve electrical connection.

The doped region 211 is spaced from the bottom of the active wall 21, so that when the substrate 100 is etched to form a plurality of bit line trenches 40 in the substrate 100, the doped region 211 is not completely removed, and the doped region 211 may be at least partially remained in the active column 20, so as to achieve the purpose of reducing the contact resistance.

Illustratively, in step S106, the first isolation dielectric layer 14 may be filled in the first trench 111 using a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process.

The material of the first isolation dielectric layer 14 is not particularly limited in this application. As an example, the first isolation dielectric layer 14 may include, but is not limited to, a third oxide layer, which may include, but is not limited to, a silicon oxide layer.

The method for manufacturing the semiconductor structure provided in the present application is not particularly limited as to the manner of forming the second trench 30 in step S107. As an example, the second trench 30 may be formed using a self-aligned double imaging process or a self-aligned quad pattern process.

Illustratively, before etching the first isolation dielectric layer 14 and the active wall 21 to form a plurality of second trenches 30 arranged at intervals along the second direction, the method may further include the following steps: forming a second mask material layer on the upper surfaces of the first isolation dielectric layer 14 and the active wall 21; forming a second photoresist layer on the surface of the second mask material layer away from the substrate 100; exposing and developing the second photoresist layer to obtain a second patterned photoresist layer, wherein the second patterned photoresist layer is provided with a third opening; etching the second mask material layer based on the second patterned photoresist layer to obtain a second patterned mask layer, wherein the second patterned mask layer is provided with a fourth opening, and the third opening defines the shape and the position of the fourth opening; and removing the second patterned photoresist layer.

Wherein, etching the first isolation dielectric layer 14 and the active wall 21 to form a plurality of second trenches 30 arranged at intervals along the second direction may include: the first isolation dielectric layer 14 and the active wall 21 are etched based on the second patterned mask layer to form a plurality of second trenches 30 arranged at intervals along the second direction, wherein the fourth opening defines the shape and position of the second trenches 30.

For example, a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process may be used to form a second mask material layer on the surface of the substrate 100, where the second mask material layer includes a silicon nitride layer or a silicon oxynitride layer, and may also include a stacked structure of a silicon nitride layer and a silicon oxynitride layer. A second photoresist layer may be formed on the surface of the second mask material layer away from the substrate 100 by spin coating in the coating method, where the second photoresist layer may include a positive photoresist layer or a negative photoresist layer. Methods of removing the second patterned photoresist layer may include, but are not limited to, ashing processes.

In the above embodiment, the second patterned mask layer is obtained based on the second patterned photoresist layer, and the third opening of the second patterned photoresist layer has an accurate shape and size, so that the fourth opening of the second patterned mask layer also has an accurate shape and size, so that the second trench 30 obtained by etching the first isolation dielectric layer 14 and the active wall 21 based on the second patterned mask layer also has an accurate shape and size.

Illustratively, in step S108, the substrate 100 may be etched using a dry etching process or a wet etching process to form a plurality of bit line trenches 40 within the substrate 100 that are spaced apart along the first direction.

The shape of the bit line trench 40 formed in some embodiments is not particularly limited in this application. As an example, the shape of the bit line trench 40 may be bowl-shaped, rectangular, oval or circular in cross section along the aa' direction in fig. 2, etc.

In step S109, the formed bit line 4 may include a bit line dielectric layer and a conductive layer, the conductive layer being located within the bit line trench 40, the bit line dielectric layer being located between the substrate 100 and the conductive layer, and between the active pillar 20 and the conductive layer.

By way of example, when the substrate 100 is a silicon substrate 100, the bit line dielectric layer may be formed within the bit line trench 40 using the following steps: forming a conductive layer within the bit line trench 40; the resulting structure is subjected to a rapid thermal process (rapid thermal processing, RTP) such that a portion of the conductive layer reacts with the substrate 100 to form a bit line dielectric layer within the bit line trench 40. During the rapid thermal processing, the doped region 211 can effectively protect the active column 20 and avoid deformation of the active column 20, thereby improving the structural stability of the active column 20. The rapid thermal process may be a wet anneal process or a dry anneal process.

The material of the conductive layer is not particularly limited in this application. As an example, the conductive layer may include, but is not limited to, a metal layer.

In one embodiment, as shown in fig. 24 (a), the active pillar 20 further includes a first connection terminal 202, a channel region 203, and a second connection terminal 204 connected in sequence; the first connection terminal 202 is located on the doped region 211 and contacts the doped region 211; the channel region 203 is located at a side of the first connection terminal 202 away from the doped region 211, and is in contact with the first connection terminal 202; the second connection end 204 is positioned on one side of the channel region 203 away from the first connection end 202 and is in contact with the channel region 203; as shown in fig. 25, after forming the bit line 4 in the bit line trench 40, the method for manufacturing the semiconductor structure may further include the following steps:

s110: forming a second isolation dielectric layer 31 in the second trench 30; the resulting structure is shown in FIG. 26.

S111: etching back to remove a portion of the second isolation dielectric 31 to expose the second connection terminal 204 and the channel region 203; the resulting structure is shown in FIG. 27.

S112: forming word lines 32 on the surface of the channel regions 203, wherein the word lines 32 extend along the first direction to cover the channel regions 203 of the active pillars 20 located in the same row; the resulting structure is shown in FIG. 28.

It should be noted that the second trench 30 may define the location of the word line 32.

Illustratively, in step S110, a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process may be used to form the second isolation dielectric 31 in the second trench 30.

The material of the second isolation medium layer 31 is not particularly limited in this application. As an example, the second isolation dielectric layer 31 may include, but is not limited to, a fourth oxide layer, which may include, but is not limited to, a silicon oxide layer.

The method used for etching back and removing part of the second isolation dielectric layer 31 may include, but is not limited to, a dry etching process or a wet etching process.

For example, the word line 32 may be formed on the surface of the channel region 203 using a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process.

In other embodiments, in step S104, referring to fig. 29 to 33 in combination with fig. 1 to 8, a doped layer 12 is formed at least on the sidewall of the region 201 to be doped.

In one embodiment, as shown in fig. 29, step S104 may include the following steps:

s1041: forming a doped material layer 102 on the upper surface of the first dielectric layer 11, the sidewall of the first trench 111, and the upper surface of the substrate 100; the resulting structure is shown in FIG. 30.

S1042: forming a filling dielectric material layer 105 on the upper surface of the doped material layer 102; the resulting structure is shown in FIG. 31.

S1043: removing the filling medium material layer 105 positioned on the upper surface of the substrate 100 and the doping material layer 102 positioned on the upper surface of the substrate 100, and back-etching the filling medium material layer 105 positioned in the first groove 111 and the doping material layer 102 positioned in the first groove 111 to form a doping layer 12 and a first filling medium layer 15, wherein the upper surface of the first filling medium layer 15 is lower than the top of the first groove 111; the resulting structure is shown in FIG. 32.

By way of example, a plasma enhanced atomic layer deposition process or a chemical vapor deposition process may be employed, with a boron source being incorporated in the deposition of the silicon oxide gas to obtain a borosilicate glass layer as the doped material layer 102; or a phosphorus source gas is doped at the time of depositing the silicon oxide gas to obtain a phosphosilicate glass layer as the doping material layer 102.

Referring to fig. 33, after forming the doped layer 12 at least on the sidewall of the region 201 to be doped, before performing the heat treatment on the obtained structure, the method further includes: forming a second filling medium layer 16 in the first trench 111 and on the upper surface of the substrate 100, wherein the first trench 111 is filled with the second filling medium layer 16; the second filling-medium layer 16 is used together with the first filling-medium layer 15 as a second medium layer.

The materials of the filling medium material layer 105, the first filling medium layer 15, and the second filling medium layer 16 are not particularly limited in this application. As an example, the filling medium material layer 105, the first filling medium layer 15, and the second filling medium layer 16 may all include, but are not limited to, a second oxide layer; the second oxide layer may include, but is not limited to, a silicon oxide layer.

As an example, the filling dielectric material layer 105 may be formed on the upper surface of the doping material layer 102 using, but not limited to, a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process; a second oxide layer may be formed as the second filling medium layer 16 in the first trench 111 and on the upper surface of the substrate 100 using, but not limited to, a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process.

Still referring to fig. 33, in step S105, the resulting structure is subjected to a heat treatment to diffuse the doped particles in the doped layer 12 into the region 201 to be doped to form a doped region 211.

Wherein the doped region 211 comprises a boron doped region or a phosphorous doped region. The doped region 211 is a boron doped region, and the doping concentration of boron element in the doped region 211 is 1E17cm ^-3 ～1E22cm ^-3 The method comprises the steps of carrying out a first treatment on the surface of the The doped region 211 is a phosphorus doped region, and the doping concentration of phosphorus element in the doped region 211 is 1E17cm ^-3 ～6E21cm ^-3 。

Referring to fig. 18, after performing a heat treatment on the obtained structure to diffuse the doped particles in the doped layer 12 into the region 201 to be doped to form a doped region 211, the method further includes: and removing the second dielectric layer 13, the residual doped layer 12 and the first dielectric layer 11.

In this embodiment, the second filling medium layer 16 and the first filling medium layer 15 are used together as the second medium layer, that is, removing the second medium layer 13, the residual doped layer 12 and the first medium layer 11 may include: the second filling-in dielectric layer 16, the remaining doped layer 12, the first filling-in dielectric layer 15 and the first dielectric layer 11 are removed.

As an example, the second filling dielectric layer 16 located on the surface of the substrate 100 may be removed using a chemical mechanical polishing process, and then the second filling dielectric layer 16, the remaining doped layer 12, the first filling dielectric layer 15, and the first dielectric layer 11 located within the first trench 111 may be removed using a dry etching process or a wet etching process.

Referring to fig. 20 to 24, after removing the second dielectric layer 13, the residual doped layer 12 and the first dielectric layer 11, the method for manufacturing the semiconductor structure may further include the following steps: filling the first trench 111 with a first isolation dielectric layer 14; etching the first isolation dielectric layer 14 and the active wall 21 to form a plurality of second trenches 30 arranged at intervals along the second direction, wherein the second trenches 30 extend along the first direction to divide the active wall 21 into a plurality of active columns 20 arranged at intervals; the doped regions 211 are located at the lower portions of the respective active pillars 20; etching the substrate 100 to form a plurality of bit line trenches 40 in the substrate 100, the bit line trenches 40 extending in a second direction; bit line trench 40 is located below doped region 211; forming a bit line 4 in the bit line trench 40; the resulting structure is shown in FIG. 24.

For example, the first isolation dielectric layer 14 may be filled in the first trench 111 using a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process.

As an example, the second trench 30 may be formed using a self-aligned double imaging process or a self-aligned quad pattern process.

For example, the substrate 100 may be etched using a dry etching process or a wet etching process to form a plurality of bit line trenches 40 spaced apart in the first direction within the substrate 100.

The bit line 4 may include a bit line dielectric layer and a conductive layer, the conductive layer being located in the bit line trench 40, the bit line dielectric layer being located between the substrate 100 and the conductive layer, and between the active pillar 20 and the conductive layer.

By way of example, when the substrate 100 is a silicon substrate 100, the bit line dielectric layer may be formed within the bit line trench 40 using the following steps: forming a conductive layer within the bit line trench 40; the resulting structure is subjected to a rapid thermal process such that a portion of the conductive layer reacts with substrate 100 to form a bit line dielectric layer within bit line trench 40. In the rapid thermal processing, the doped layer 12 can effectively protect the active column 20 and avoid deformation of the active column 20, thereby improving the structural stability of the active column 20. The rapid thermal process may be a wet anneal process or a dry anneal process.

Referring to fig. 25 to 28, the active pillar 20 further includes a first connection terminal 202, a channel region 203, and a second connection terminal 204 sequentially connected, the first connection terminal 202 contacts the doped region 211, the channel region 203 is located at a side of the first connection terminal 202 away from the doped region 211, and the second connection terminal 204 is located at a side of the channel region 203 away from the first connection terminal 202; after forming the bit line 4 in the bit line trench 40, the method of fabricating the semiconductor structure may further include the steps of: forming a second isolation dielectric layer 31 in the second trench 30; etching back to remove a portion of the second isolation dielectric 31 to expose the second connection terminal 204 and the channel region 203; forming word lines 32 on the surface of the channel regions 203, wherein the word lines 32 extend along the first direction to cover the channel regions 203 of the active pillars 20 located in the same row; the resulting structure is shown in FIG. 28.

In one embodiment, the patterned structure may include a gate structure 51. Referring to fig. 34 in conjunction with fig. 1, in step S102, a plurality of patterned structures arranged at intervals are formed, and the patterned structures are located on a substrate, and may include: a plurality of gate structures 51 are formed on the upper surface of the substrate 100 in a spaced apart arrangement.

The gate structure 51 has a region 201 to be doped, and the region 201 to be doped has a space from at least the bottom of the gate structure 51.

Illustratively, the gate structure 51 comprises a gate structure of a trench-type device.

With continued reference to fig. 34, before forming the plurality of patterned structures arranged at intervals, the method for manufacturing a semiconductor structure further includes: shallow trench isolation structures 103 are formed within the substrate 100.

Referring to fig. 35, before forming the first dielectric layer in the gaps between the adjacent patterned structures, the method may further include: a step of forming a source region 52 and a drain region 53 in the substrate 100; wherein the source region 52 is located within the substrate 100 and on one side of the gate structure 51; drain region 53 is located within substrate 100 and on a side of gate structure 51 remote from source region 52.

With reference to fig. 35, in step S103, a first dielectric layer 11 is formed in the gaps between the adjacent patterned structures, and the upper surface of the first dielectric layer 11 is not higher than the bottom of the to-be-doped region 201, which may include: a first dielectric layer 11 is formed in the gap between the adjacent gate structures 51, and the upper surface of the first dielectric layer 11 is not higher than the bottom of the region 201 to be doped.

The material of the first dielectric layer 11 is not particularly limited in this embodiment. As an example, the first dielectric layer 11 may include, but is not limited to, a first oxide layer, which may include, but is not limited to, a silicon oxide layer.

As an example, the first dielectric layer 11 may be formed in the gap between the adjacent gate structures 51 using, but not limited to, a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process.

Referring to fig. 36, in step S104, forming a doped layer 12 at least on the sidewall of the region 201 to be doped may include: a doped layer 12 is formed on the upper surface of the first dielectric layer 11, the upper surface of the gate structure 51, and the exposed sidewalls of the gate structure 51.

By way of example, a plasma enhanced atomic layer deposition process or a chemical vapor deposition process may be employed, with a boron source gas being doped while depositing a silicon oxide gas to obtain a borosilicate glass layer as doped layer 12; or a phosphorus source gas is doped at the time of depositing the silicon oxide gas to obtain a phosphosilicate glass layer as the doped layer 12.

Referring to fig. 37, in step S105, the obtained structure is subjected to a heat treatment to diffuse the doped particles in the doped layer 12 into the region 201 to be doped to form a doped region 211.

The doped layer 12 directly contacts the gate structure 51, and in the heat treatment process, the doped particles are directly diffused into the gate structure 51, so that the diffusion distance is short, the doping efficiency is high, the obtained doping concentration is high, and the doped region 211 is located in the gate structure 51, so that the gate contact resistance can be reduced, and the device performance can be improved.

Exemplary, the doped region 211 is a boron doped region, the doping concentration of boron element in the doped region 211 is 1E17cm ^-3 、1E18cm ^-3 、1E19cm ^-3 、1E20cm ^-3 、1E21cm ^-3 Or 1E22cm ^-3 Also, itMay be otherwise located at 1E17cm ^-3 ～1E22cm ^-3 The doping concentration therebetween is not limited by the example. The doped region 211 is a phosphorus doped region, and the doping concentration of phosphorus element in the doped region 211 is 1E17cm ^-3 、1E18cm ^-3 、1E19cm ^-3 、1E20cm ^-3 、1E21cm ^-3 、2E21cm ^-3 、3E21cm ^-3 、4E21cm ^-3 、5E21cm ^-3 Or 6E21cm ^-3 Other 1E17cm may be used ^-3 ～6E21cm ^-3 The doping concentration therebetween is not limited by the example.

In one embodiment, the patterned structure may include fin structures 6. Referring to fig. 38 in conjunction with fig. 1, in step S102, a plurality of patterned structures arranged at intervals are formed, and the patterned structures are located on a substrate, and may include: the substrate 100 is etched to form a plurality of fin structures 6 in the substrate 100 in spaced apart arrangement.

The fin-shaped structure 6 has a region 201 to be doped, and the region 201 to be doped has a space at least from the bottom of the fin-shaped structure 6.

Referring to fig. 39, in step S103, a first dielectric layer 11 is formed in the gaps between the adjacent patterned structures, and the upper surface of the first dielectric layer 11 is not higher than the bottom of the to-be-doped region 201, which may include: a first dielectric layer 11 is formed in the gaps between adjacent fin structures 6, and the upper surface of the first dielectric layer 11 is not higher than the bottom of the region 201 to be doped.

As an example, the first dielectric layer 11 may be formed in the gap between the adjacent fin structures 6 using, but not limited to, a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process.

Referring to fig. 40, in step S104, forming a doped layer 12 at least on the sidewall of the region 201 to be doped may include: a doped layer 12 is formed on the upper surface of the first dielectric layer 11, the upper surface of the fin structure 6, and the exposed sidewalls of the fin structure 6.

Referring to fig. 41, in step S105, the obtained structure is subjected to a heat treatment to diffuse the doped particles in the doped layer 12 into the region 201 to be doped to form a doped region 211.

The doped layer 12 directly contacts the fin structure 6, and in the heat treatment process, the doped particles are directly diffused into the fin structure 6, so that the diffusion distance is short, the doping efficiency is high, the obtained doping concentration is high, the doped region 211 is located in the fin structure 6, the contact resistance of the fin structure 6 can be reduced, and the device performance is improved.

Exemplary, the doped region 211 is a boron doped region, the doping concentration of boron element in the doped region 211 is 1E17cm ^-3 、1E18cm ^-3 、1E19cm ^-3 、1E20cm ^-3 、1E21cm ^-3 Or 1E22cm ^-3 Other 1E17cm may be used ^-3 ～1E22cm ^-3 The doping concentration therebetween is not limited by the example. Doped region 211 is a phosphorus doped region, and phosphorus in doped region 211The doping concentration of the element is 1E17cm ^-3 、1E18cm ^-3 、1E19cm ^-3 、1E20cm ^-3 、1E21cm ^-3 、2E21cm ^-3 、3E21cm ^-3 、4E21cm ^-3 、5E21cm ^-3 Or 6E21cm ^-3 Other 1E17cm may be used ^-3 ～6E21cm ^-3 The doping concentration therebetween is not limited by the example.

It should be understood that, although the steps in the flowcharts of the embodiments are shown in order as indicated by the arrows, these steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least a portion of the steps in the flowcharts of the embodiments may include a plurality of steps or a plurality of stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of the execution of the steps or stages is not necessarily sequential, but may be performed in rotation or alternatively with at least a portion of the steps or stages in other steps or others.

The present application further provides a semiconductor structure, referring to fig. 28, 33, 37 or 41, the semiconductor structure includes: the substrate 100 and a plurality of patterned structures arranged at intervals, wherein the patterned structures are provided with doped regions 211, and the doped regions 211 are at least spaced from the bottom of the patterned structures.

In the semiconductor structure provided in the present application, the material of the substrate 100 is not particularly limited. By way of example, the material of the substrate 100 may be any suitable material, for example, at least one of the following mentioned materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN), or other III/V compound semiconductors, and also include multilayer structures formed of these semiconductors, or the like, or are silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), germanium-on-insulator (GeOI), or the like, or may be Double polished silicon wafer (Double Side PolishedWafers, DSP), and the like, and the present embodiment is not limited thereto.

Wherein the patterned structure may be located within the substrate 100 or on the substrate 100. It will be appreciated that the patterned structure may be located within the substrate 100, or the patterned structure may be located on the substrate 100; the patterned structure is located on the substrate 100, which means that the patterned structure may be directly located on the upper surface of the substrate 100, or other structural layers may be further disposed between the patterned structure and the upper surface of the substrate 100.

The semiconductor structure in the above embodiment includes the substrate 100 and a plurality of patterned structures arranged at intervals, where the doped region 211 is located in the patterned structures, so as to obtain an active column, a gate or a fin structure with high-concentration doping later, and the doping utilization rate is high; the doped region 211 has a distance from at least the bottom of the patterned structure, and when the partial structure at the bottom of the patterned structure needs to be removed in the subsequent process, the doped region 211 is not removed, so that the doped region 211 can be at least partially remained in the patterned structure, thereby achieving the purpose of reducing the contact resistance.

In one embodiment, with continued reference to fig. 28, the patterned structure may include active pillars 20. The active pillar 20 includes a first connection terminal 202, a channel region 203, and a second connection terminal 204; the first connection terminal 202 is located on the doped region 211 and contacts the doped region 211; the channel region 203 is located at a side of the first connection terminal 202 away from the doped region 211, and is in contact with the first connection terminal 202; the second connection terminal 204 is located at a side of the channel region 203 away from the first connection terminal 202, and contacts the channel region 203.

With continued reference to fig. 28, the semiconductor structure further includes: a plurality of bit lines 4 arranged at intervals along the first direction, the bit lines 4 being located under the active pillars 20, each bit line 4 extending along the second direction to serially connect the doped regions 211 of the active pillars 20 located in the same column in sequence; the second direction intersects the first direction.

Illustratively, the bit line 4 may include a bit line dielectric layer and a conductive layer, the bit line dielectric layer being located between the substrate 100 and the conductive layer, and between the active pillar 20 and the conductive layer. The material of the conductive layer is not particularly limited in this application. As an example, the conductive layer may include, but is not limited to, a metal layer.

Illustratively, the shape of the bit line 4 may include a bowl shape, a rectangle, an oval shape, a circle, or the like.

Referring to fig. 3 to 28, the substrate 100 has a first trench 111 and a second trench 30 therein, and the first trench 111 and the second trench 30 are isolated from each other to form a plurality of active pillars 20 arranged at intervals; the first trench 111 extends in a second direction, and the second trench 30 extends in the first direction; the semiconductor structure further includes: a first isolation dielectric layer 14 and a second isolation dielectric layer 31; the first isolation dielectric layer 14 is located in the first trench 111; the second isolation dielectric layer 31 is located in the second trench 30, and the second isolation dielectric layer 31 and the first isolation dielectric layer 14 jointly cover the first connection end 202 of each active column 20 and the doped region 211 of the active column 20; the word line 32 wraps around the channel regions 203 of the active pillars 20 located in the same row.

As an example, the first isolation dielectric layer 14 may include, but is not limited to, a third oxide layer, which may include, but is not limited to, a silicon oxide layer. The second isolation dielectric layer 31 may include, but is not limited to, a fourth oxide layer, which may include, but is not limited to, a silicon oxide layer.

In one embodiment, doped region 211 may include a boron doped region or a phosphorous doped region. The doped region 211 is a boron doped region, and the doping concentration of boron element in the doped region 211 is 1E17cm ^-3 ～1E22cm ^-3 The method comprises the steps of carrying out a first treatment on the surface of the The doped region 211 is a phosphorus doped region, and the doping concentration of phosphorus element in the doped region 211 is 1E17cm ^-3 ～6E21cm ^-3 。

In one embodiment, as shown in fig. 37, the patterned structure may include a gate structure 51, the gate structure 51 being located on the upper surface of the substrate 100; the semiconductor structure may further include: a source region 52 and a drain region 53; source region 52 is located within substrate 100 and on one side of gate structure 51; drain region 53 is located within substrate 100 and on a side of gate structure 51 remote from source region 52.

The doped region 211 is located in the gate structure 51, which can help to reduce the gate contact resistance and improve the device performance.

With continued reference to fig. 37, the semiconductor structure may further include: shallow trench isolation structure 103; shallow trench isolation structure 103 is located within substrate 100.

In one embodiment, as shown in fig. 41, the patterned structure may include a fin structure 6, the fin structure 6 being located within the substrate 100.

The doped region 211 is located in the fin structure 6, which can help to reduce the contact resistance of the fin structure 6 and improve the structure performance.

Based on the same inventive concept, the application also provides a preparation method of the memory structure. As shown in fig. 42, the method for manufacturing the memory structure may include the steps of:

s4201: the preparation method of the semiconductor structure is adopted to prepare the semiconductor structure;

s4202: forming a plurality of storage node structures; the storage node structure is positioned above the second connecting end of the active column and is connected with the second connecting end in one-to-one correspondence;

s4203: forming a plurality of capacitors; the capacitors are positioned on the upper surface of the storage node structure and are arranged in one-to-one correspondence with the storage node structure.

The preparation method of the memory structure in the embodiment adopts the preparation method of the semiconductor structure, and the patterning structure is provided with the region to be doped by forming a plurality of patterning structures which are distributed at intervals in the substrate, and the doped layer is at least formed on the side wall of the region to be doped, so that after the doped layer is formed, the doped particles in the doped layer are diffused into the region to be doped to form the doped region by heat treatment, the doped particles of the doped layer are directly diffused into the active wall, the substrate is not required to be passed, the diffusion distance of the doped particles is short, the doping utilization rate is high, and the doped region with high concentration can be obtained in the patterning structure so as to obtain the active column, the grid or the fin structure with high concentration doping later; the first dielectric layer is formed in the gaps between the patterned structures, so that the upper and lower positions of the doped layers can be correspondingly adjusted by adjusting the thickness of the first dielectric layer, and the doped positions can be accurately controlled; the doped region is spaced from the bottom of the patterned structure, and is not removed when the partial structure at the bottom of the patterned structure needs to be removed in the subsequent process, so that the doped region can be at least partially reserved in the patterned structure, and the purpose of reducing contact resistance is achieved.

Based on the same inventive concept, the present application also provides a memory structure (not shown). The memory structure includes: the semiconductor structure, the plurality of storage node structures and the plurality of capacitors of the application; the storage node structures are positioned above the second connecting ends of the active columns and are connected with the second connecting ends in a one-to-one correspondence manner; the plurality of capacitors are positioned on the upper surface of the storage node structure and are arranged in one-to-one correspondence with the storage node structure.

The memory structure in the embodiment comprises a semiconductor structure, wherein the semiconductor structure comprises a substrate and a plurality of patterned structures which are arranged at intervals, and a doped region is positioned in the patterned structures so as to obtain an active column, a grid or a fin-shaped structure with high-concentration doping, and the like, and the doping utilization rate is high; the doped region is at least spaced from the bottom of the patterned structure, and is not removed when the partial structure at the bottom of the patterned structure needs to be removed in the subsequent process, so that the doped region can be at least partially reserved in the patterned structure, and the purpose of reducing contact resistance is achieved.

The technical features of the above embodiments may be arbitrarily combined, and for brevity, all of the possible combinations of the technical features of the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The above examples only represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the claims. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.

Claims

1. A method of fabricating a semiconductor structure, comprising:

providing a substrate;

forming a doped layer at least on the side wall of the region to be doped;

2. The method of manufacturing a semiconductor structure according to claim 1, wherein forming a plurality of spaced apart patterned structures, the patterned structures being located within the substrate, comprises:

3. The method of claim 2, wherein forming a doped layer on at least a sidewall of the region to be doped comprises:

4. The method of claim 3, wherein after forming a doped layer on at least a sidewall of the region to be doped, the method further comprises, prior to heat treating the resulting structure:

5. The method of claim 2, wherein forming a doped layer on at least a sidewall of the region to be doped comprises:

6. The method of claim 5, wherein after forming a doped layer on at least a sidewall of the region to be doped, the method further comprises, prior to heat treating the resulting structure:

7. The method of manufacturing a semiconductor structure according to claim 4 or 6, wherein after performing a heat treatment on the obtained structure to diffuse doped particles in the doped layer into the region to be doped to form a doped region, further comprising:

8. The method for manufacturing a semiconductor structure according to claim 7, wherein after removing the second dielectric layer, the remaining doped layer and the first dielectric layer, further comprises:

filling a first isolation medium layer in the first groove;

and forming a bit line in the bit line groove.

9. The method of claim 8, wherein the active column further comprises a first connection terminal, a channel region, and a second connection terminal connected in sequence; the first connecting end is positioned on the doped region and is contacted with the doped region; the channel region is positioned at one side of the first connecting end far away from the doped region and is contacted with the first connecting end; the second connecting end is positioned at one side of the channel region away from the first connecting end and is contacted with the channel region; after the bit line is formed in the bit line trench, the method further comprises:

forming a second isolation medium layer in the second groove;

10. The method of claim 1, wherein the patterned structure comprises a gate structure;

11. The method of manufacturing a semiconductor structure of claim 1, wherein the patterned structure comprises a fin structure;

12. A semiconductor structure, comprising:

A substrate;

13. The semiconductor structure of claim 12, wherein the patterned structure comprises an active pillar comprising a first connection terminal, a channel region, and a second connection terminal; the first connecting end is positioned on the doped region and is contacted with the doped region; the channel region is positioned at one side of the first connecting end far away from the doped region and is contacted with the first connecting end; the second connecting end is positioned at one side of the channel region away from the first connecting end and is contacted with the channel region; the semiconductor structure further includes:

14. The semiconductor structure of claim 13, wherein the substrate has a first trench and a second trench therein, the first trench and the second trench isolating a plurality of the active pillars arranged in a spaced apart relationship; the first groove extends along the second direction, and the second groove extends along the first direction; the semiconductor structure further includes:

The first isolation medium layer is positioned in the first groove;

15. The semiconductor structure of claim 12, wherein the patterned structure comprises a gate structure, the gate structure being located on an upper surface of the substrate; the semiconductor structure further includes:

16. The semiconductor structure of claim 12, wherein the patterned structure comprises a fin structure, the fin structure being located within the substrate.

17. A method of fabricating a memory structure, comprising:

preparing the semiconductor structure by adopting the preparation method of the semiconductor structure as claimed in claim 9;

18. A memory structure, comprising:

the semiconductor structure of claim 14;