CN116469846A - Power semiconductor module and packaging method thereof - Google Patents

Power semiconductor module and packaging method thereof Download PDF

Info

Publication number
CN116469846A
CN116469846A CN202310658528.7A CN202310658528A CN116469846A CN 116469846 A CN116469846 A CN 116469846A CN 202310658528 A CN202310658528 A CN 202310658528A CN 116469846 A CN116469846 A CN 116469846A
Authority
CN
China
Prior art keywords
area
region
groove
power semiconductor
semiconductor module
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310658528.7A
Other languages
Chinese (zh)
Inventor
曹永锋
杨恒
陈皓
顾捷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Zhaoqing Xiaopeng Automobile Co Ltd
Original Assignee
Guangzhou Xiaopeng Motors Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Guangzhou Xiaopeng Motors Technology Co Ltd filed Critical Guangzhou Xiaopeng Motors Technology Co Ltd
Priority to CN202310658528.7A priority Critical patent/CN116469846A/en
Publication of CN116469846A publication Critical patent/CN116469846A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The application relates to a power semiconductor module and a packaging method of the power semiconductor module, wherein the power semiconductor module comprises: plastic packaging material; a cermet substrate; wherein the cermet substrate comprises a first metal surface comprising a first region and a second region distinct from the first region; the first region is provided with a first groove and at least one component, the first groove is used for forming a conductive circuit meeting electrical isolation on the first metal surface, and the conductive circuit is communicated with the at least one component; at least part of the second area has target characteristics, and the target characteristics are obtained by processing in a preset processing mode; the probability of layering phenomenon is reduced, and the stability of the power semiconductor module is improved.

Description

Power semiconductor module and packaging method thereof
Technical Field
The present disclosure relates to power semiconductor technology, and more particularly, to a power semiconductor module and a method for packaging the power semiconductor module.
Background
The power semiconductor module generally comprises a chip, a terminal, a metal ceramic substrate, a plastic package material, a metal wire and other components, wherein the plastic package material is used for plastic package of other components.
The inventor found in the study that, because the difference of thermal expansion coefficients of the metal ceramic substrate and the plastic package material is larger, stress is generated at the interface between the metal ceramic substrate and the plastic package material due to heat curing and cooling of the plastic package material or severe change of the plastic package temperature in the plastic package process, so that layering phenomenon is easy to occur between the metal ceramic substrate and the plastic package material, and the stability of the power semiconductor module is poor.
Disclosure of Invention
In order to overcome the problems in the related art, the application provides a power semiconductor module and a packaging method of the power semiconductor module, so as to reduce the probability of layering phenomenon between a metal ceramic substrate and a plastic package material and improve the stability of the power semiconductor module.
A first aspect of the present application provides a power semiconductor module, comprising:
plastic packaging material;
a cermet substrate;
wherein the cermet substrate comprises a first metal surface comprising a first region and a second region distinct from the first region; the first region is provided with a first groove and at least one component, the first groove is used for forming a conductive circuit meeting electrical isolation on the first metal surface, and the conductive circuit is communicated with the at least one component;
at least part of the second area has target characteristics, and the target characteristics are obtained by processing in a preset processing mode.
As a possible embodiment of the present application, in this embodiment, at least a part of the second area has a target feature, including: at least part of the second area is provided with at least one groove, wherein the groove is used for accommodating the plastic package material;
or at least part of the second area is provided with at least one second groove, wherein the second groove is used for accommodating the plastic package material.
As a possible embodiment of the present application, in this embodiment, when at least two grooves are formed in the at least partial region, the at least two grooves are disposed in parallel and/or in a crossing manner.
As one possible embodiment of the present application, in this embodiment, the cermet substrate includes a first metal layer having the first metal surface;
the first metal layer has a first thickness;
wherein the groove has a first depth that is less than or equal to the first thickness.
As a possible implementation manner of the present application, in this implementation manner, the first trench adopts the preset processing manner and has a first depth; the second trench has a second depth;
the second depth is less than or equal to the first depth.
As a possible embodiment of the present application, in this embodiment, at least a part of the second area has a target feature, including: at least a portion of the second region has a first roughness;
wherein the at least partial region of the second region has a second roughness prior to being treated in the predetermined treatment mode;
the first roughness is greater than the second roughness.
A second aspect of the present application provides a method for packaging a power semiconductor module, including:
acquiring a metal ceramic substrate, wherein a first metal surface of the metal ceramic substrate comprises a first area and a second area which is different from the first area; wherein the first region is provided with a first groove and at least one component, the first groove is used for forming a conductive circuit meeting electrical isolation on the first metal surface, and the conductive circuit is communicated with the at least one component;
processing at least part of the second region by adopting a preset processing mode, so that the at least part of the second region generates target characteristics;
and adopting plastic packaging material to carry out plastic packaging on the first metal surface with the target characteristics to obtain the packaged power semiconductor module.
As a possible implementation manner of the present application, in this implementation manner, the processing at least a part of the second area by using a preset processing manner, so that the generating, by using the at least part of the second area, the target feature includes:
and manufacturing at least one groove or at least one groove in at least part of the second area by adopting a preset processing mode.
As a possible implementation manner of the present application, in this implementation manner, the processing at least a part of the second area by using a preset processing manner, so that the generating, by using the at least part of the second area, the target feature includes:
carrying out surface roughening treatment on at least part of the second area by adopting a preset treatment mode, so that the surface of the at least part of the second area has first roughness; the at least partial area has a second roughness before being processed by the preset processing mode, and the first roughness is larger than the second roughness.
As a possible implementation manner of the present application, in this implementation manner, the preset processing manner processes at least a part of the second area, so that the at least part of the second area generates the target feature, including:
and processing at least part of the second region by at least one of a mechanical manufacturing mode, an etching manufacturing mode, a laser manufacturing mode, a microetching manufacturing mode, a sand blasting manufacturing mode and a sputtering manufacturing mode so that the at least part of the second region generates target features.
The technical scheme that this application provided can include following beneficial effect:
the application provides a power semiconductor module, which comprises a plastic package material and a metal ceramic substrate, wherein the first metal surface of the metal ceramic substrate comprises a first area and a second area which is different from the first area, and the first area is provided with a first groove and at least one part; at least part of the second area has target characteristics, and the target characteristics are obtained by processing in a preset processing mode; in the application, the processing of the preset processing mode is carried out on at least part of the second area of the first metal surface, so that the formed target feature can be tightly attached to the first metal surface and the plastic package material, layering phenomenon is not easy to occur between the first metal surface and the plastic package material in the plastic package process, namely, the probability of layering phenomenon is reduced, and the stability of the power semiconductor module is improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
The foregoing and other objects, features and advantages of the application will be apparent from the following more particular descriptions of exemplary embodiments of the application as illustrated in the accompanying drawings wherein like reference numbers generally represent like parts throughout the exemplary embodiments of the application.
FIG. 1a is a schematic side view of a combination of a cermet substrate and a molding compound according to an embodiment of the present application;
FIG. 1b is a schematic top view of a ceramic-metal substrate and molding compound combination according to an embodiment of the present application;
fig. 2 is a schematic structural view of a power semiconductor module according to an embodiment of the present application;
FIG. 3 is a schematic view of a partial structure of a first metal surface of a cermet substrate provided with a first trench according to an embodiment of the present disclosure;
FIG. 4 is a schematic top view of a first metal surface of a cermet substrate before plastic encapsulation according to an embodiment of the present disclosure;
FIG. 5 is a schematic side view of a cermet substrate shown in an embodiment of the present application;
FIG. 6 is another schematic side view of a cermet substrate and molding compound combination shown in an embodiment of the present application;
FIG. 7 is a schematic top view of a first metal surface of a cermet substrate before plastic encapsulation according to an embodiment of the present application;
FIG. 8 is another schematic top view of a first metal surface of a cermet substrate prior to plastic encapsulation according to an embodiment of the present disclosure;
FIG. 9 is a schematic diagram of a further partial top view of a first metal surface of a cermet substrate prior to plastic encapsulation according to embodiments of the present application;
fig. 10 is a flow chart illustrating a packaging method of a power semiconductor module according to an embodiment of the present application.
Detailed Description
Preferred embodiments of the present application will be described in more detail below with reference to the accompanying drawings. While the preferred embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
The terminology used in the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items.
It should be understood that although the terms "first," "second," "third," etc. may be used herein to describe various information, these information should not be limited by these terms. These terms are only used to distinguish one type of information from another. For example, a first message may also be referred to as a second message, and similarly, a second message may also be referred to as a first message, without departing from the scope of the present application. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In the related art, because the thermal expansion coefficients of the metal ceramic substrate and the plastic package material are greatly different, stress is generated at the interface between the metal ceramic substrate and the plastic package material due to heat curing and cooling of the plastic package material or severe change of the plastic package temperature in the plastic package process, so that layering phenomenon is easy to occur between the metal ceramic substrate and the plastic package material, and the stability of the power semiconductor module is poor.
Fig. 1a is a schematic side view structure of a combination of a metal ceramic substrate and a molding compound, and fig. 1b is a schematic top view structure of a combination of a metal ceramic substrate and a molding compound, so that it can be seen that an obvious layering phenomenon occurs between the metal ceramic substrate 1 and the molding compound 2, so that a power semiconductor module is easy to fail, and the stability of the power semiconductor module is reduced.
Aiming at the problems, the embodiment of the application provides a power semiconductor module which can reduce the probability of layering phenomenon between a metal ceramic substrate and a plastic package material and improve the stability of the power semiconductor module.
The following describes the technical scheme of the embodiments of the present application in detail with reference to the accompanying drawings.
Fig. 2 is a schematic structural diagram of a power semiconductor module according to an embodiment of the present application, referring to fig. 2, the power semiconductor module includes a component X1, a component X2, a molding compound SFL, and a cermet substrate JB.
The power semiconductor module includes at least one component, and the components X1 and X2 shown in fig. 2 are only one specific example and do not constitute a limitation of the present application. As one possible embodiment of the present application, the component may be at least one of a chip, a terminal, a wire, and the like.
The component X1 and the component X2 are disposed on the first metal surface of the cermet substrate JB, and specifically may be disposed on the first metal surface by soldering or the like.
At least one first groove GC is arranged on the first metal surface of the metal ceramic substrate JB, the first groove GC is used for forming a conductive line meeting electrical isolation on the first metal surface, the conductive line is communicated with at least one component, and in fig. 2, the conductive line is communicated with the component X1 and the component X2.
The shape of the first groove is not limited in this application, and may be one or more of a strip shape, a circular shape, a rectangular shape, and the like. As a possible embodiment of the present application, fig. 3 shows a partial schematic view of the first metal surface provided with the first trench, and the black area is the first trench.
At least one component, such as component X1 and component X2, is disposed on the first metal surface and may cover a portion or all of the first trenches GC.
In this application, the region of the first metal surface where the at least one component is disposed and the region where the first trench is disposed are referred to as a first region, and the first metal surface further includes a second region, which is different from the first region.
The molding compound SFL is used for molding the at least one component and the metal ceramic substrate, and in some embodiments, the molding compound SFL may be made of epoxy resin, phenolic resin, silica powder, and the like.
At least part of the second area has target characteristics, and the target characteristics are obtained by processing in a preset processing mode.
It should be noted that, the target feature can enable the molding compound to be attached to the first metal surface, that is, the second area of the first metal surface treated by the preset treatment mode has the target feature, after the molding compound is used for molding the metal ceramic substrate, the first groove and at least one component arranged on the metal ceramic substrate, the target feature can enable the molding compound to be attached to the metal ceramic substrate tightly, so that the possibility of layering is reduced.
As a possible implementation manner of the present application, fig. 4 is a schematic top view of a first metal surface of a cermet substrate before plastic packaging shown in an embodiment of the present application.
The first metal surface of the cermet substrate JB is provided with a first trench GC1, a chip X2, and a terminal X3.
The areas where the first grooves GC1, the chips X2, and the terminals X3 are located are the first areas of the first metal surface, and it should be noted that the chips X1, the chips X2, and the terminals X3 may be in communication with conductive lines formed on the first metal surface by the first grooves GC1, for example, part of the components may be connected by wires, or may be connected by welding.
The areas other than the first area are the second areas of the first metal surface, i.e., the white areas shown in fig. 4 are the second areas.
At least part of the second area is provided with target features, the target features are obtained by processing in a preset processing mode, and the target features enable the plastic packaging material to be attached to the first metal surface when the plastic packaging material is used for plastic packaging of the first metal surface.
Since delamination generally occurs from the edge of the first metal surface, in some embodiments, the target feature may be obtained by processing the region between the border of the cermet substrate and the first region in the second region in a preset manner, so as to reduce the probability of delamination from the edge of the first metal surface.
In other embodiments, all the regions of the second region may be processed by a preset processing manner to obtain the target feature, so as to reduce the probability of delamination between the first metal surface and the molding compound to the greatest extent.
It can be seen that the present application provides a power semiconductor module, including at least one component, a molding compound, and a cermet substrate, wherein a first metal surface of the cermet substrate includes a first region and a second region different from the first region, and the at least one component and a first trench are disposed in the first region; at least part of the second area is provided with target features, the target features are obtained by processing in a preset processing mode, and the formed target features can be more tightly attached to the first metal surface and the plastic package material by processing at least part of the second area of the first metal surface in the preset processing mode, so that layering phenomenon is not easy to occur between the first metal surface and the plastic package material in the plastic package process, namely, the probability of layering phenomenon is reduced, and the stability of the power semiconductor module is improved.
In some embodiments, as shown in fig. 5, the cermet substrate includes a first metal layer J1, a second metal layer J2, and a ceramic layer J3; wherein the ceramic layer J3 is located between the first metal layer J1 and the second metal layer J2.
In some embodiments, the first metal layer J1 and the second metal layer J2 may be made of copper, which, of course, is not limited to the present application, and conductive metal layers made of other materials are all within the scope of the present application.
The first metal surface may be a metal surface of the first metal layer J1 or the second metal layer J2.
As a possible embodiment of the present application, at least a part of the second area has a target feature, including: at least part of the second area is provided with at least one groove, wherein the groove is used for accommodating the plastic package material.
Fig. 6 shows another schematic side view of the combination of the metal ceramic substrate and the molding compound, and as shown in fig. 6, a groove is formed on the metal ceramic substrate JB, and the groove is used for accommodating the molding compound SFL when the molding compound SFL performs the molding on the first metal surface.
In some embodiments, when at least two grooves are formed in at least a portion of the area, the at least two grooves are disposed in parallel and/or in a cross arrangement. Fig. 7 shows a schematic top view of a first metal surface of a metal ceramic substrate before plastic packaging, and as shown in fig. 7, a second area of the first metal surface of the metal ceramic substrate JB is provided with a plurality of grooves AC, some of the grooves are arranged in parallel, and some of the grooves are arranged in a crossing manner.
In some embodiments, the placement region of the recess may be a region between the bezel of the cermet substrate and the first region. In other embodiments, the placement area of the groove may be all of the second area.
In some embodiments, referring to fig. 5, the first metal layer J1 of the cermet substrate has a first metal surface; and the first metal layer J1 has a first thickness and the groove has a first depth, the first depth being less than or equal to the first thickness.
In some embodiments, the first depth of the recess is between 20um and 1000 um.
The preset treatment mode of the groove can comprise one or more of a mechanical manufacturing mode, an etching manufacturing mode and a laser manufacturing mode.
It should be noted that the processing manner of the groove may be the same as that of the first groove, that is, the groove is obtained by adopting the same preset processing manner as that of the first groove; or the processing mode of the groove can be different from that of the first groove, namely the groove is obtained by adopting a preset processing mode different from that of the first groove.
In the application, at least one groove is formed by processing at least part of the second area of the first metal surface in a preset processing mode, and the plastic packaging material is contained when the plastic packaging material is packaged on the first metal surface through the groove, so that the first metal surface and the plastic packaging material can be tightly attached to each other, and layering phenomenon is prevented.
In one possible embodiment of the present application, at least a part of the second area has a target feature, including: at least part of the second area is provided with at least one second groove, wherein the second groove is used for accommodating the plastic package material when the plastic package material is used for plastic packaging the first metal surface.
In order to improve the convenience of processing the second region, in this embodiment, the second trench is formed by extending the first trench, that is, the second trench and the first trench are formed by the same process, but the effects are different, the second trench has the function of preventing layering, and the first trench has the function of electrical isolation.
From another point of view, the second trench is obtained by the same predetermined processing as the first trench.
Wherein the first trench for forming a conductive line satisfying electrical isolation has a first depth; the second trench has a second depth; the second depth is less than or equal to the first depth. That is, the same processing means that the manufacturing process is the same, but the depths of both may be the same or different.
In some embodiments, the shape of the second trench may be the same as the shape of the first trench, and if the first metal surface includes multiple shapes of the first trench, the second trench may be the same as a portion of the first trench, although the second trench may include all of the shapes of the first trench.
In some embodiments, the second trench is circular or rectangular. Fig. 8 shows another schematic top view of the first metal surface of the cermet substrate before plastic encapsulation, and the first metal surface of the cermet substrate JB has a second groove GC2 thereon, and the shape includes a circle and a rectangle.
The second groove is arranged to accommodate the plastic package material when the plastic package material is used for plastic package of the first metal surface, so that the first metal surface and the plastic package material are tightly connected, and layering phenomenon is prevented.
In some embodiments, a region between the rim and the first region of the cermet substrate may be provided with a second trench. In other embodiments, all of the second region may be provided with the second trench.
In this application, through to the second regional at least some regional adoption of adoption is predetermine processing method and is handled and obtain at least one second slot, and the second slot is the extension that goes on the basis of first slot, can increase the compactness that first metal surface and plastic envelope material laminate, prevents to take place layering phenomenon.
As a possible embodiment of the present application, at least a part of the second area has a target feature, including: at least a portion of the second region has a first roughness.
Wherein the at least partial region of the second region has a second roughness prior to being treated by the predetermined treatment means.
The first roughness is greater than the second roughness.
It should be noted that, before the treatment in the preset treatment mode, the at least part of the second area may be a smooth surface, i.e. the second roughness is zero.
It can be appreciated that the delamination phenomenon is prevented by making the first metal surface closely adhere to the molding compound by increasing the roughness of at least a part of the second region.
Fig. 9 is a schematic diagram of still another partial top view structure of the first metal surface of the cermet substrate before plastic packaging, where the schematic diagram is that the at least partial area of the second area is treated by a preset treatment mode to obtain the first roughness.
Wherein the target feature may be characterized as having a micro-roughened surface in at least a portion of the second region. In some embodiments, the surface of the region between the rim and the first region of the cermet substrate may be treated to have a first roughness. In other embodiments, the surface of all regions of the second region may be treated to have the first roughness.
The preset treatment mode of the surface with the first roughness can comprise one or more of a microetching manufacture mode, a sand blasting manufacture mode and a sputtering manufacture mode.
In the application, the first roughness is obtained by processing the at least partial area of the second area in a preset processing mode, and the friction force between the first metal surface and the plastic packaging material can be increased when the plastic packaging material is used for plastic packaging the first metal surface due to the fact that the first roughness is larger than the second roughness before the processing in the preset processing mode, so that the first metal surface and the plastic packaging material can be tightly attached to each other, and layering phenomenon is prevented.
Corresponding to the embodiment of the application function realizing device, the application also provides a packaging method of the power semiconductor module and a corresponding embodiment.
Fig. 10 is a flowchart of a packaging method of a power semiconductor module according to an embodiment of the present application, and referring to fig. 10, the method may include the following steps:
step 1001: obtaining a metal ceramic substrate;
wherein the first metal surface of the cermet substrate comprises a first region and a second region different from the first region;
the first region is provided with a first trench for forming a conductive line on the first metal surface that satisfies electrical isolation, and at least one component with which the conductive line communicates.
Step 1002: processing at least part of the second region by adopting a preset processing mode, so that the at least part of the second region generates target characteristics;
step 1003: and adopting plastic packaging material to carry out plastic packaging on the first metal surface with the target characteristics to obtain the packaged power semiconductor module.
Therefore, the metal ceramic substrate with the first metal surface comprising the first area and the second area different from the first area is obtained, at least part of the second area is processed in a preset processing mode, the at least part of the second area generates target characteristics, and the metal surface with the target characteristics is subjected to plastic package by adopting plastic package materials, so that the packaged power semiconductor module is obtained; in the application, the processing of the preset processing mode is carried out on at least part of the second area of the first metal surface, so that the formed target feature can be tightly attached to the first metal surface and the plastic package material, layering phenomenon is not easy to occur between the first metal surface and the plastic package material in the plastic package process, namely, the probability of layering phenomenon is reduced, and the stability of the power semiconductor module is improved.
As a possible implementation manner of the present application, the processing at least a part of the second area by using a preset processing manner, so that the generating, by using the at least part of the second area, the target feature includes:
and manufacturing at least one groove or at least one groove in the at least partial area of the second area by adopting a preset processing mode.
It should be noted that, the processing mode of the groove may be the same as that of the first groove, that is, the groove is obtained by adopting the same preset processing mode as that of the first groove; or the processing mode of the groove can be different from that of the first groove, namely the groove is obtained by adopting a preset processing mode different from that of the first groove.
In order to improve the convenience of the second region processing, in some embodiments, the second trench is a trench that is formed by extending on the basis of the first trench, that is, the processing manner of the second trench and the first trench is the same, in other words, the second trench is obtained by adopting the same preset processing manner as the first trench. It will be appreciated that although the second trench is formed by the same process as the first trench, the effect is not the same, the second trench acts to prevent delamination and the first trench acts as an electrical isolation.
As a possible implementation manner of the present application, the processing at least a part of the second area by using a preset processing manner, so that the generating, by using the at least a part of the second area, the target feature includes:
carrying out surface roughening treatment on at least part of the second area by adopting a preset treatment mode, so that the surface of the at least part of the second area has first roughness; the at least partial region of the second region has a second roughness before the processing in the preset processing mode, and the first roughness is larger than the second roughness.
As a possible implementation manner of the present application, the preset processing manner processes at least a part of the second area, so that the at least part of the second area generates the target feature, including:
and processing at least part of the second region by at least one of a mechanical manufacturing mode, an etching manufacturing mode, a laser manufacturing mode, a microetching manufacturing mode, a sand blasting manufacturing mode and a sputtering manufacturing mode so that the at least part of the second region generates target features.
The aspects of the present application have been described in detail hereinabove with reference to the accompanying drawings. In the foregoing embodiments, the descriptions of the embodiments are focused on, and for those portions of one embodiment that are not described in detail, reference may be made to the related descriptions of other embodiments. Those skilled in the art will also appreciate that the acts and modules referred to in the specification are not necessarily required in the present application. In addition, it can be understood that the steps in the method of the embodiment of the present application may be sequentially adjusted, combined and pruned according to actual needs, and the modules in the apparatus of the embodiment of the present application may be combined, divided and pruned according to actual needs.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the application herein may be implemented as electronic hardware, computer software, or combinations of both.
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems and methods according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
The embodiments of the present application have been described above, the foregoing description is exemplary, not exhaustive, and not limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various embodiments described. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or the improvement of technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims (10)

1. A power semiconductor module, comprising:
plastic packaging material;
a cermet substrate;
wherein the cermet substrate comprises a first metal surface comprising a first region and a second region distinct from the first region; the first region is provided with a first groove and at least one component, the first groove is used for forming a conductive circuit meeting electrical isolation on the first metal surface, and the conductive circuit is communicated with the at least one component;
at least part of the second area has target characteristics, and the target characteristics are obtained by processing in a preset processing mode.
2. The power semiconductor module of claim 1, wherein at least a portion of the second region has a target feature, comprising: at least part of the second area is provided with at least one groove, wherein the groove is used for accommodating the plastic package material;
or at least part of the second area is provided with at least one second groove, wherein the second groove is used for accommodating the plastic package material.
3. A power semiconductor module according to claim 2, characterized in that at least two grooves are arranged in parallel and/or crosswise when formed in the at least partial region.
4. The power semiconductor module of claim 2, wherein the cermet substrate comprises a first metal layer having the first metal surface;
the first metal layer has a first thickness;
wherein the groove has a first depth that is less than or equal to the first thickness.
5. The power semiconductor module of claim 2, wherein the first trench is of a first depth using the predetermined process; the second trench has a second depth;
the second depth is less than or equal to the first depth.
6. The power semiconductor module of claim 1, wherein at least a portion of the second region has a target feature, comprising: at least a portion of the second region has a first roughness;
wherein the at least partial region of the second region has a second roughness prior to being treated in the predetermined treatment mode;
the first roughness is greater than the second roughness.
7. A method of packaging a power semiconductor module, comprising:
acquiring a metal ceramic substrate, wherein a first metal surface of the metal ceramic substrate comprises a first area and a second area which is different from the first area; wherein the first region is provided with a first groove and at least one component, the first groove is used for forming a conductive circuit meeting electrical isolation on the first metal surface, and the conductive circuit is communicated with the at least one component;
processing at least part of the second region by adopting a preset processing mode, so that the at least part of the second region generates target characteristics;
and adopting plastic packaging material to carry out plastic packaging on the first metal surface with the target characteristics to obtain the packaged power semiconductor module.
8. The packaging method according to claim 7, wherein the processing at least a part of the second area by a preset processing manner, so that the at least a part of the second area generates the target feature, includes:
and manufacturing at least one groove or at least one groove in at least part of the second area by adopting a preset processing mode.
9. The packaging method according to claim 7, wherein the processing at least a part of the second area by a preset processing manner, so that the at least a part of the second area generates the target feature, includes:
carrying out surface roughening treatment on at least part of the second area by adopting a preset treatment mode, so that the surface of the at least part of the second area has first roughness; the at least partial area has a second roughness before being processed by the preset processing mode, and the first roughness is larger than the second roughness.
10. The packaging method according to claim 7, wherein the processing at least a part of the second area by the preset processing manner, so that the at least a part of the second area generates the target feature, includes:
and processing at least part of the second region by at least one of a mechanical manufacturing mode, an etching manufacturing mode, a laser manufacturing mode, a microetching manufacturing mode, a sand blasting manufacturing mode and a sputtering manufacturing mode so that the at least part of the second region generates target features.
CN202310658528.7A 2023-06-05 2023-06-05 Power semiconductor module and packaging method thereof Pending CN116469846A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310658528.7A CN116469846A (en) 2023-06-05 2023-06-05 Power semiconductor module and packaging method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310658528.7A CN116469846A (en) 2023-06-05 2023-06-05 Power semiconductor module and packaging method thereof

Publications (1)

Publication Number Publication Date
CN116469846A true CN116469846A (en) 2023-07-21

Family

ID=87177377

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310658528.7A Pending CN116469846A (en) 2023-06-05 2023-06-05 Power semiconductor module and packaging method thereof

Country Status (1)

Country Link
CN (1) CN116469846A (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050285147A1 (en) * 2004-06-29 2005-12-29 Sanyo Electric Co., Ltd. Circuit apparatus and method of manufacturing the same
CN101075597A (en) * 2007-04-29 2007-11-21 江苏长电科技股份有限公司 Method for packing against semiconductor plastic sealer internal device lamination
US20080099924A1 (en) * 2005-05-04 2008-05-01 Icemos Technology Corporation Silicon Wafer Having Through-Wafer Vias With A Predetermined Geometric Shape
US20100320579A1 (en) * 2009-06-22 2010-12-23 Texax Instruments Incorporated Metallic Leadframes Having Laser-Treated Surfaces for Improved Adhesion to Polymeric Compounds
KR20220013663A (en) * 2020-07-27 2022-02-04 주식회사 아모센스 Power module

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050285147A1 (en) * 2004-06-29 2005-12-29 Sanyo Electric Co., Ltd. Circuit apparatus and method of manufacturing the same
US20080099924A1 (en) * 2005-05-04 2008-05-01 Icemos Technology Corporation Silicon Wafer Having Through-Wafer Vias With A Predetermined Geometric Shape
CN101075597A (en) * 2007-04-29 2007-11-21 江苏长电科技股份有限公司 Method for packing against semiconductor plastic sealer internal device lamination
US20100320579A1 (en) * 2009-06-22 2010-12-23 Texax Instruments Incorporated Metallic Leadframes Having Laser-Treated Surfaces for Improved Adhesion to Polymeric Compounds
KR20220013663A (en) * 2020-07-27 2022-02-04 주식회사 아모센스 Power module

Similar Documents

Publication Publication Date Title
CN109417854B (en) Ceramic substrate and method for manufacturing same
US6924170B2 (en) Diamond-silicon hybrid integrated heat spreader
US10559535B2 (en) High-frequency module and manufacturing method therefor
US10546987B2 (en) Method for producing a component, and a component
US10629781B2 (en) Semiconductor element and method for production thereof
WO2022009527A1 (en) Circuit board and circuit module using same
AU6469499A (en) Method for producing a microtransponder
US20040036181A1 (en) Connection of integrated circuit to a substrate
WO2007105880A1 (en) Manufacturing method of radiant heat circuit board
CN116469846A (en) Power semiconductor module and packaging method thereof
US20170133340A1 (en) Method for producing a chip module
WO2007105879A1 (en) Manufacturing method of radiant heat circuit board
CN112714539A (en) Electronic component and method of manufacturing an electronic component
US11640925B2 (en) System and method for a device package
KR102031727B1 (en) Ceramic board and manufacturing method thereof
CN211792251U (en) Embedded copper structure for microelectronic package
EP3751603A2 (en) Semiconductor package with a heat sink bonded to a semiconductor chip with a bonding layer and to a molding material with a thermal interface material
US10925163B2 (en) Printed circuit board
KR20170104757A (en) Plugging Method for Via Hall of Ceramic Board and Filler for Via Hall of Ceramic Board using the same
KR102119142B1 (en) Method for fabriating Wafer Level Package's Carrier using lead frame
EP3457434B1 (en) Method for producing a semiconductor substrate for a power semiconductor module arrangement
US20230230906A1 (en) Manufacturing of electronic components
KR20100107543A (en) Method of enhancing the sticking strength of an embedded chip for embedded printed circuit board
KR20190119000A (en) Ceramic board and manufacturing method thereof
JP2003332503A (en) Circuit board having heat sink and its manufacturing method

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
TA01 Transfer of patent application right

Effective date of registration: 20231016

Address after: No. 33, Longhu Avenue, High-tech Zone, Zhaoqing City, Guangdong Province, 526238

Applicant after: ZHAOQING XIAOPENG AUTOMOBILE Co.,Ltd.

Address before: 510000 No.8 Songgang street, Cencun, Tianhe District, Guangzhou City, Guangdong Province

Applicant before: GUANGZHOU XIAOPENG MOTORS TECHNOLOGY Co.,Ltd.

TA01 Transfer of patent application right