CN116467979A - Cross-FPGA chip static analysis method, device, equipment and medium containing TDM program blocks - Google Patents

Cross-FPGA chip static analysis method, device, equipment and medium containing TDM program blocks Download PDF

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Publication number
CN116467979A
CN116467979A CN202310507876.4A CN202310507876A CN116467979A CN 116467979 A CN116467979 A CN 116467979A CN 202310507876 A CN202310507876 A CN 202310507876A CN 116467979 A CN116467979 A CN 116467979A
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tdm
data
program
block
graph
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杨鑫钰
杜旗
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Shanghai Sierxin Technology Co ltd
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Shanghai Sierxin Technology Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3315—Design verification, e.g. functional simulation or model checking using static timing analysis [STA]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/331—Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
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  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

The invention provides a method, a device, equipment and a medium for static analysis of a cross-FPGA chip containing TDM program blocks, which belong to the field of electronic design automation, and the method comprises the steps of analyzing signal connection data among different FPGA chips from a segmentation file, and carrying out abstract mapping on connection of the different FPGA chips in a system according to the signal connection data to obtain a first abstract graph; when the FPGA chip is judged to have the TDM program blocks, acquiring all transmission data transmitted through the TDM program blocks from the signal connection data, and storing the transmission data through a hash table; adjusting TDM program blocks in the first abstract graph as points based on the hash table, and generating a directed acyclic graph; and obtaining delay information of the TDM program blocks according to the hash table, and marking the delay information on the directed acyclic graph to obtain a static analysis graph for displaying the delay information of each TDM program block. By the processing scheme, the cross-FPGA chip containing the TDM program blocks is rapidly patterned, and delay information in the TDM program blocks is rapidly acquired.

Description

Cross-FPGA chip static analysis method, device, equipment and medium containing TDM program blocks
Technical Field
The invention relates to the field of electronic design automation, in particular to a method, a device, equipment and a medium for static analysis of a cross-FPGA chip containing TDM program blocks.
Background
In the existing integrated circuit design, each different stage needs to perform timing sequence inspection on the circuit design to ensure that the designed circuit can meet the preset timing sequence requirement. Static timing analysis (STA, static timing analysis) is a method of estimating the expected timing of a circuit without performing simulations. Sometimes, one task cannot be realized by one FPGA resource, and a plurality of FPGA chips are matched to realize the task, so that different data can be transmitted across the FPGA chips.
When performing time sequence analysis across the FPGA, the prior method needs to build graphs of all time sequence logic device pins, all combination logic device pins and all top-layer ports so as to screen out the maximum delay path information. When TDM (time-division multiplexing: time division multiplexing) blocks exist between the FPGA chips, the TDM blocks contain a large amount of sequential logic and combinational logic information. When analyzing the user design file containing the TDM module, the TDM and Cable delays are considered in the timing path. So when analyzing the timing path across the FPGA, once the data is transferred through the TDM block, all the combinational and sequential logic under the TDM block is spread out when patterning. After synthesis, when the delay value of the time sequence path is calculated, delay information in the TDM program block is added into path delay calculation factors, and the TDM module occupies resources far larger than user design contents, so that a large amount of unnecessary calculation and analysis are increased, the efficiency of the whole system-level static time sequence analysis is slowed down, and the purpose of STA rapid analysis is violated.
Disclosure of Invention
Therefore, in order to overcome the defects in the prior art, the invention provides a cross-FPGA chip static analysis method, a device, equipment and a medium for rapidly patterning a cross-FPGA chip containing a TDM program block and rapidly acquiring delay information in the TDM program block.
In order to achieve the above object, the present invention provides a static analysis method for a cross-FPGA chip including TDM blocks, including: analyzing signal connection data among different FPGA chips from a segmentation file, and carrying out abstract mapping on connection of the different FPGA chips in a system according to the signal connection data to obtain a first abstract graph; when the FPGA chip is judged to have the TDM program blocks, acquiring all transmission data transmitted through the TDM program blocks from the signal connection data, and storing the transmission data through a hash table; adjusting the TDM program blocks in the first abstract graph to be points based on the hash table, and generating a directed acyclic graph; and obtaining delay information of the TDM program blocks according to the hash table, and marking the delay information on the directed acyclic graph to obtain a static analysis graph for displaying the delay information of each TDM program block.
In one embodiment, the abstracting the connection of different FPGA chips in the system according to the signal connection data to obtain a first abstract graph includes: determining a circuit node serving as a starting node of a first abstract graph, and extracting a data path of a transmission cable signal of the starting node from the signal connection data; and carrying out abstract mapping based on the data path of the starting node to obtain a first abstract graph.
In one embodiment, the acquiring all transmission data transmitted by the TDM block from the signal connection data and storing the transmission data by a hash table includes: screening transmission data of all TDM program blocks from the signal connection data; determining a TDM transmitting program block-circuit line-TDM receiving program block data pair corresponding to the transmission data according to the current type of the TDM program block, the information transmission direction and the data transmission corresponding relation; all TDM transmit block-circuit line-TDM receive block data pairs are stored by a hash table.
In one embodiment, the determining the TDM transmit block-circuit line-TDM receive block data pair corresponding to the transmission data according to the current type of the TDM block, the information transmission direction, and the data transmission correspondence includes: determining the current type of a first TDM program block corresponding to the transmission data, and determining the signal interest rate, the signal delay value and the corresponding information transmission direction corresponding to the current type of the first TDM program block; determining a second FPGA chip where a second TDM program block is located based on the information transmission direction; determining the second TDM program block corresponding to the transmission data in the second FPGA chip; and determining TDM transmitting program block-circuit line-TDM receiving program block data pairs corresponding to the transmission data according to the first TDM program block, the second TDM program block, the information transmission direction, the signal interest rate and the signal delay value.
A cross-FPGA chip static analysis apparatus comprising TDM blocks, the apparatus comprising: the first mapping module is used for analyzing signal connection data among different FPGA chips from the segmentation file, and carrying out abstract mapping on the connection of the different FPGA chips in the system according to the signal connection data to obtain a first abstract graph; the hash table construction module is used for acquiring all transmission data transmitted through the TDM program blocks from the signal connection data when the TDM program blocks exist in the FPGA chip, and storing the transmission data through a hash table; the second mapping module is used for adjusting the TDM program blocks in the first abstract graph to be points based on the hash table and generating a directed acyclic graph; and the analysis display module is used for acquiring the delay information of the TDM program blocks according to the hash table, marking the delay information on the directed acyclic graph, and obtaining a static analysis graph for displaying the delay information of each TDM program block.
A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor implements the steps of the above method when executing the computer program.
A computer readable storage medium having stored thereon a computer program, characterized in that the computer program when executed by a processor realizes the steps of the above method.
Compared with the prior art, the invention has the advantages that: the method has the advantages that the TDM program blocks are subjected to abstract construction by using a single construction point mode, logic contained in the TDM program blocks is not required to be unfolded, the construction time is reduced, unnecessary node construction is reduced, and the complexity of time sequence construction is reduced; and the delay value information of the TDM program block is rapidly determined from signal connection data in the partition file, superposition operation is not needed after logic contained in the TDM program block is unfolded, the data operation amount is further reduced, and the delay value information passing through the TDM can be intuitively and rapidly displayed when the time sequence path delay value is rapidly formed and calculated.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow diagram of a method of static analysis across an FPGA chip with TDM blocks in an embodiment of the invention;
FIG. 2 is an expanded schematic diagram of a TDM block when the TDM block is a transmit block in an embodiment of the present invention;
FIG. 3 is an expanded schematic diagram of a TDM block when the TDM block is a receive block in an embodiment of the present invention;
FIG. 4 is a directed acyclic graph generated in an embodiment of the invention;
FIG. 5 is a block diagram of a static analysis device across an FPGA chip containing TDM blocks in one embodiment;
fig. 6 is an internal structural diagram of a computer device in one embodiment.
Detailed Description
Embodiments of the present application are described in detail below with reference to the accompanying drawings.
Other advantages and effects of the present application will become apparent to those skilled in the art from the present disclosure, when the following description of the embodiments is taken in conjunction with the accompanying drawings. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. The present application may be embodied or carried out in other specific embodiments, and the details of the present application may be modified or changed from various points of view and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
It is noted that various aspects of the embodiments are described below within the scope of the following claims. It should be apparent that the aspects described herein may be embodied in a wide variety of forms and that any specific structure and/or function described herein is merely illustrative. Based on the present application, one skilled in the art will appreciate that one aspect described herein may be implemented independently of any other aspect, and that two or more of these aspects may be combined in various ways. For example, apparatus may be implemented and/or methods practiced using any number and aspects set forth herein. In addition, such apparatus may be implemented and/or such methods practiced using other structure and/or functionality in addition to one or more of the aspects set forth herein.
It should also be noted that the illustrations provided in the following embodiments merely illustrate the basic concepts of the application by way of illustration, and only the components related to the application are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.
In addition, in the following description, specific details are provided in order to provide a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects may be practiced without these specific details.
As shown in fig. 1, the embodiment of the present application provides a static analysis method of a cross-FPGA chip with TDM program blocks, which may be applied to a terminal or a server, where the terminal may be, but is not limited to, various personal computers, notebook computers, smartphones, tablet computers and portable intelligent devices, and the server may be implemented by an independent server or a server cluster formed by a plurality of servers, and the method includes the following steps:
and step 101, analyzing signal connection data among different FPGA chips from the segmentation file, and carrying out abstract mapping on connection of the different FPGA chips in the system according to the signal connection data to obtain a first abstract graph.
The division file contains the division data of all circuit nodes in the design file, wherein the division data comprises the number of the circuit nodes on each FPGA chip, the signal connection data such as circuit connection, data transmission direction and the like, and the division file can be in an xml format. After the processes of layout and wiring, the FPGA chips are powered on and run at the same time, and alternating current signals can be communicated through interconnection lines among the FPGA chip arrays. The server can verify the logic in the chip design file by listening for different signals on the FPGA chip.
The design file is used for describing the structure of each circuit node of the circuit system and the connection relation among the circuit nodes. The design file contains a plurality of logic blocks (modules), the logic blocks have nesting or parallel relations, and each logic block corresponds to each circuit node of the circuit system. The circuit node may be one or more electronic components. Communication signals are provided between the logic blocks, and the signals can also pass through the logic blocks to the inside.
The split data includes signal connection data on all FPGA chips and between FPGA chips. The signal connection data comprise internal connection data between different electronic elements in each FPGA chip and external connection data between different FPGA chips.
The server may parse the signal connection data from the split file. The server can abstract and map external connection data of different FPGA chips in the system based on the signal connection data to obtain a first abstract graph. At this time, the server does not need to spread and pattern the internal connection on the FPGA chip, and only needs to reserve a port connected with the external chip during the pattern formation.
And 102, when the FPGA chip is judged to have the TDM program block, acquiring all transmission data transmitted through the TDM program block from the signal connection data, and storing the transmission data through a hash table.
The server judges whether the FPGA chip has the TDM program blocks, and when judging that the FPGA chip has the TDM program blocks, acquires all transmission data transmitted through the TDM program blocks from the signal connection data and stores the transmission data through a hash table (Config table). The server can acquire transmission data such as TDM transmit block information/TDM receive block information, transmission paths, signal interest rates (ratios), signal delay values (delay values), and the like from the signal connection data. The ratio is the interest rate of the transmitted signal or the received signal in the TDM block, for example, if there are 8 signal lines in one TDM transmission block, the ratio is 8, and the calculation of the delay value can be obtained by the ratio value of the TDM block. The Config table is a TDM ratio and delay corresponding relation lookup table, and a final TDM program block delay value is obtained through the difference that the TDM program block is a transmitting program block or a receiving program block and then the corresponding ratio value. When the composition calculates the complete cross-FPGA delay value, the time sequence path passes through the TDM program block, and the TDM end delay value which is abstracted into a point can be quickly obtained through the config table.
The hash table stores the signal correspondence (correspondence between the current FPGA's transmit block signal and the target FPGA's TDM receive block signal) across FPGAs transmitted via the TDM blocks. All signal names passing through the TDM transmitting program block and the receiving program block (the signal names are unique on one FPGA) can be obtained through the hash table, all signal names crossing the FPGA on the current FPGA can be stored by taking the FPGA names as keywords, and the hash table also stores signal information on other FPGAs connected with the signals, including signal names and direction, ratio information. The key of the hash table is the signal name and the value is the contiguous signal name.
When the server judges that the FPGA chip does not have the TDM program blocks, the server adjusts the first abstract graph into a directed acyclic graph based on external connection data, and outputs the directed acyclic graph to obtain a static analysis graph of the corresponding segmentation file.
And step 103, adjusting the TDM program blocks in the first abstract graph to be points based on the hash table, and generating the directed acyclic graph.
The server adjusts the TDM blocks in the first abstract graph as points based on the hash table and generates a directed acyclic graph. The server can abstract the TDM program blocks positioned at the boundary of the FPGA into a point which is stored in the directed acyclic graph, if the TDM program blocks are transmitting program blocks (as shown in figure 2), the direction of the point points to the outside of the current FPGA, the input end is connected with the r1/regester_reg/Q end of the FPGA, and the outside is connected with the TDM receiving end of the non-current FPGA (F2); if the TDM module is a receiving block (as shown in fig. 3), the point points to the inside of the current FPGA, the former node is the TDM transmitting end of the non-current FPGA, and the latter node is the r2/regester_reg/D end of the current FPGA (F2), and the final obtained directed acyclic graph is shown in fig. 4. In fig. 4, 10 is a data path (data path), 20 is a clock path (clock path), W1 of F1 is a TDM transmitting end, and W1 of F2 is a TDM receiving end.
And 104, acquiring delay information of the TDM program blocks according to the hash table, and marking the delay information on the directed acyclic graph to obtain a static analysis graph for displaying the delay information of each TDM program block.
And the server acquires the delay information of the TDM program blocks according to the hash table, marks the delay information on the directed acyclic graph, and obtains a static analysis graph for displaying the delay information of each TDM program block. The server judges whether the current TDM program block of the FPGA is a transmitting end or a receiving end, obtains a delay value of the current TDM program block according to the ratio value, and marks delay information of the TDM program block in the constructed directed acyclic graph.
As shown in fig. 4, F1 and F2 are signaled by TDM transmit blocks and TDM receive blocks, in fig. 2 TDM blocks tdm_bank37_tx_inst contain a lot of combinational and sequential logic content, when the user only needs to know the following path values in static analysis: the sequential logic device F1/NGLE/FPGA_F1_XCVU440FLGA2892_s2cExGrp/r 1/regester_reg/C- > F2/NGLE/FPGA_F2_XCVU440FLGA2892_s2cExGrp/r2/regester_reg/D in the FPGA F1, and the path passes through the TDM program blocks, in order not to introduce a great deal of redundant design, the TDM can be abstractly patterned in a way of a directed acyclic graph, and corresponding delay values are output. The delay value is obtained through a configuration table. The configuration table in the hash table has ratio information, and ratio and delay are inherent properties of the TDM device and can be provided by IP design.
The method uses a mode of independent construction points to carry out abstract construction on the TDM program blocks, logic contained in the TDM program blocks is not required to be unfolded, the construction time is reduced, unnecessary node construction is reduced, and the complexity of time sequence construction is reduced; and the delay value information of the TDM program block is rapidly determined from signal connection data in the partition file, superposition operation is not needed after logic contained in the TDM program block is unfolded, the data operation amount is further reduced, and the delay value information passing through the TDM can be intuitively and rapidly displayed when the time sequence path delay value is rapidly formed and calculated.
In one embodiment, abstract mapping is performed on connections of different FPGA chips in a system according to signal connection data to obtain a first abstract map, including the following steps: determining a circuit node serving as a starting node of a first abstract graph, and extracting a data path of a transmission cable signal of the starting node from signal connection data; and carrying out abstract mapping based on the data path of the starting node to obtain a first abstract graph.
In parsing (Parse) a design file, modules may be instantiated as logical instances (instances), which are nodes in the syntax tree graph, and form a hierarchical tree structure-syntax tree (InstanceTree) graph. The instances contain logic functions, and a connection relationship exists between the instances. Each Instance corresponds to one Module only, and the nested relation among the modules forms the connection relation of the parent-child nodes in the grammar tree, and the logical relation in the parent nodes also comprises the connection relation among the child nodes.
The division is to divide different circuit nodes of the grammar tree into a designated number of different parts, and each part is distributed to different FPGA chips. So the grammar tree graph which is segmented to the corresponding FPGA chip can be extracted from the segmentation file. As shown in fig. 2, the server can pattern the FPGA chip, and the nodes of the top port search inwards and pass through the middle-level non-positionable point r1/D until the positionable point r1/regester_reg/D in the bottom node is determined; and then a data path (data path) finds out the r1/regester_reg/C end, and the map is built through the r1/regester_reg/C- > r1/regester_reg/Q to find out the positionable points r1/regester_reg/C and r 1/regester_reg/Q.
In one embodiment, obtaining all transmission data transmitted through the TDM block from the signal connection data and storing the transmission data through the hash table includes: screening transmission data of all TDM program blocks from the signal connection data; determining a TDM transmitting program block-circuit line-TDM receiving program block data pair corresponding to transmission data according to the current type of the TDM program block, the information transmission direction and the data transmission corresponding relation; all TDM transmit block-circuit line-TDM receive block data pairs are stored by a hash table.
The server screens out the transmission data of all TDM program blocks from the signal connection data.
The current types of TDM blocks include TDM transmit blocks and TDM receive blocks. The server determines TDM transmitting program block-circuit line-TDM receiving program block data pairs corresponding to the transmission data according to the current type of the TDM program block, the information transmission direction and the data transmission corresponding relation. The server stores all TDM transmit chunk-circuit line-TDM receive chunk data pairs through a hash table. The server stores signals which are transmitted and received across the FPGA and through TDM into a hash table, wherein keys of the hash table are signal names, and values are connected signal names.
In one embodiment, determining a TDM transmit block-circuit line-TDM receive block data pair corresponding to the transmission data according to the current type of the TDM block, the information transmission direction, and the data transmission correspondence, includes: determining the current type of a first TDM program block corresponding to the transmission data, and determining the signal interest rate, the signal delay value and the corresponding information transmission direction corresponding to the current type of the first TDM program block; determining a second FPGA chip where a second TDM program block is located based on the information transmission direction; determining a second TDM program block corresponding to the transmission data in a second FPGA chip; and determining the TDM transmitting program block-circuit line-TDM receiving program block data pair corresponding to the transmission data according to the first TDM program block, the second TDM program block, the information transmission direction, the signal interest rate and the signal delay value.
In one embodiment, as shown in fig. 5, a static analysis device containing TDM blocks and crossing FPGA chips is provided, where the device includes a first mapping module 501, a hash table construction module 502, a second mapping module 503, and an analysis display module 504.
The first mapping module 501 is configured to analyze signal connection data between different FPGA chips from the partition file, and abstract mapping connection of different FPGA chips in the system according to the signal connection data, so as to obtain a first abstract graph.
The hash table construction module 502 is configured to obtain all transmission data transmitted through the TDM program block from the signal connection data when it is determined that the FPGA chip has the TDM program block, and store the transmission data through the hash table.
A second mapping module 503 is configured to adjust the TDM blocks in the first abstract graph to be points based on the hash table, and generate a directed acyclic graph.
And the analysis display module 504 is configured to obtain delay information of the TDM blocks according to the hash table, and mark the delay information on the directed acyclic graph, so as to obtain a static analysis graph displaying the delay information of each TDM block.
In one embodiment, the first mapping module includes:
and the extraction unit is used for determining a circuit node serving as a starting node of the first abstract graph and extracting a data path of a transmission cable signal of the starting node from the signal connection data.
The first mapping unit is used for carrying out abstract mapping based on the data path of the starting node to obtain a first abstract graph.
In one embodiment, the hash table construction module comprises:
and the screening unit is used for screening the transmission data of all the TDM program blocks from the signal connection data.
And the data pair determining unit is used for determining the TDM transmitting program block-circuit line-TDM receiving program block data pair corresponding to the transmission data according to the current type of the TDM program block, the information transmission direction and the data transmission corresponding relation.
And the storage unit is used for storing all TDM transmitting program block-circuit line-TDM receiving program block data pairs through a hash table.
In one embodiment, the hash table construction module comprises:
and the judging unit is used for judging the current type of the first TDM program block corresponding to the transmission data and determining the signal interest rate, the signal delay value and the corresponding information transmission direction corresponding to the current type of the first TDM program block.
And the second chip determining unit is used for determining a second FPGA chip where the second TDM program block is located based on the information transmission direction.
And the second program block determining unit is used for determining a second TDM program block corresponding to the transmission data in the second FPGA chip.
And a data pair determining unit for determining a TDM transmitting block-circuit line-TDM receiving block data pair corresponding to the transmission data according to the first TDM block, the second TDM block, the information transmission direction, the signal interest rate and the signal delay value.
For specific limitations of the static analysis device containing TDM blocks and across FPGA chips, reference may be made to the above limitation of the static analysis method containing TDM blocks and across FPGA chips, which is not described herein. The modules in the above-mentioned static analysis device containing TDM blocks and crossing FPGA chips can be all or partially implemented by software, hardware and their combination. The above modules may be embedded in hardware or may be independent of a processor in the computer device, or may be stored in software in a memory in the computer device, so that the processor may call and execute operations corresponding to the above modules.
In one embodiment, a computer device is provided, which may be a server, the internal structure of which may be as shown in fig. 6. The computer device includes a processor, a memory, a network interface, and a database connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The database of the computer device is used for storing data such as hash tables. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program, when executed by a processor, implements a method of static analysis across FPGA chips that includes TDM blocks.
It will be appreciated by those skilled in the art that the structure shown in fig. 6 is merely a block diagram of some of the structures associated with the present application and is not limiting of the computer device to which the present application may be applied, and that a particular computer device may include more or fewer components than shown, or may combine certain components, or have a different arrangement of components.
In one embodiment, a computer device is provided comprising a memory storing a computer program and a processor that when executing the computer program performs the steps of: analyzing signal connection data among different FPGA chips from the segmentation file, and carrying out abstract mapping on connection of the different FPGA chips in the system according to the signal connection data to obtain a first abstract graph; when the FPGA chip is judged to have the TDM program blocks, acquiring all transmission data transmitted through the TDM program blocks from the signal connection data, and storing the transmission data through a hash table; adjusting TDM program blocks in the first abstract graph as points based on the hash table, and generating a directed acyclic graph; and obtaining delay information of the TDM program blocks according to the hash table, and marking the delay information on the directed acyclic graph to obtain a static analysis graph for displaying the delay information of each TDM program block.
In one embodiment, the abstract mapping of connections of different FPGA chips in the system according to signal connection data implemented when the processor executes the computer program, to obtain a first abstract map, includes: determining a circuit node serving as a starting node of a first abstract graph, and extracting a data path of a transmission cable signal of the starting node from signal connection data; and carrying out abstract mapping based on the data path of the starting node to obtain a first abstract graph.
In one embodiment, the method for obtaining all transmission data transmitted through the TDM program block from the signal connection data implemented when the processor executes the computer program, and storing the transmission data through the hash table includes: screening transmission data of all TDM program blocks from the signal connection data; determining a TDM transmitting program block-circuit line-TDM receiving program block data pair corresponding to transmission data according to the current type of the TDM program block, the information transmission direction and the data transmission corresponding relation; all TDM transmit block-circuit line-TDM receive block data pairs are stored by a hash table.
In one embodiment, determining a TDM transmit block-circuit line-TDM receive block data pair corresponding to the transmission data according to a current type of the TDM block, an information transmission direction, and a data transmission correspondence implemented when the processor executes the computer program, includes: determining the current type of a first TDM program block corresponding to the transmission data, and determining the signal interest rate, the signal delay value and the corresponding information transmission direction corresponding to the current type of the first TDM program block; determining a second FPGA chip where a second TDM program block is located based on the information transmission direction; determining a second TDM program block corresponding to the transmission data in a second FPGA chip; and determining the TDM transmitting program block-circuit line-TDM receiving program block data pair corresponding to the transmission data according to the first TDM program block, the second TDM program block, the information transmission direction, the signal interest rate and the signal delay value.
In one embodiment, a computer readable storage medium is provided having a computer program stored thereon, which when executed by a processor, performs the steps of: analyzing signal connection data among different FPGA chips from the segmentation file, and carrying out abstract mapping on connection of the different FPGA chips in the system according to the signal connection data to obtain a first abstract graph; when the FPGA chip is judged to have the TDM program blocks, acquiring all transmission data transmitted through the TDM program blocks from the signal connection data, and storing the transmission data through a hash table; adjusting TDM program blocks in the first abstract graph as points based on the hash table, and generating a directed acyclic graph; and obtaining delay information of the TDM program blocks according to the hash table, and marking the delay information on the directed acyclic graph to obtain a static analysis graph for displaying the delay information of each TDM program block.
In one embodiment, the abstract mapping of connections of different FPGA chips in the system according to signal connection data implemented when the computer program is executed by the processor, to obtain a first abstract map, includes: determining a circuit node serving as a starting node of a first abstract graph, and extracting a data path of a transmission cable signal of the starting node from signal connection data; and carrying out abstract mapping based on the data path of the starting node to obtain a first abstract graph.
In one embodiment, a computer program, when executed by a processor, obtains all transmission data transmitted through TDM blocks from signal connection data, and stores the transmission data through a hash table, including: screening transmission data of all TDM program blocks from the signal connection data; determining a TDM transmitting program block-circuit line-TDM receiving program block data pair corresponding to transmission data according to the current type of the TDM program block, the information transmission direction and the data transmission corresponding relation; all TDM transmit block-circuit line-TDM receive block data pairs are stored by a hash table.
In one embodiment, determining a TDM transmit block-circuit line-TDM receive block data pair corresponding to the transmission data according to a current type of the TDM block, an information transmission direction, and a data transmission correspondence implemented when the computer program is executed by the processor, includes: determining the current type of a first TDM program block corresponding to the transmission data, and determining the signal interest rate, the signal delay value and the corresponding information transmission direction corresponding to the current type of the first TDM program block; determining a second FPGA chip where a second TDM program block is located based on the information transmission direction; determining a second TDM program block corresponding to the transmission data in a second FPGA chip; and determining the TDM transmitting program block-circuit line-TDM receiving program block data pair corresponding to the transmission data according to the first TDM program block, the second TDM program block, the information transmission direction, the signal interest rate and the signal delay value.
The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions easily conceivable by those skilled in the art within the technical scope of the present application should be covered in the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (7)

1. A method for static analysis of a cross-FPGA chip containing TDM program blocks is characterized by comprising the following steps:
analyzing signal connection data among different FPGA chips from a segmentation file, and carrying out abstract mapping on connection of the different FPGA chips in a system according to the signal connection data to obtain a first abstract graph;
when the FPGA chip is judged to have the TDM program blocks, acquiring all transmission data transmitted through the TDM program blocks from the signal connection data, and storing the transmission data through a hash table;
adjusting the TDM program blocks in the first abstract graph to be points based on the hash table, and generating a directed acyclic graph;
and obtaining delay information of the TDM program blocks according to the hash table, and marking the delay information on the directed acyclic graph to obtain a static analysis graph for displaying the delay information of each TDM program block.
2. The method of claim 1, wherein abstracting connections of different FPGA chips in the system according to the signal connection data to obtain a first abstract graph comprises:
determining a circuit node serving as a starting node of a first abstract graph, and extracting a data path of a transmission cable signal of the starting node from the signal connection data;
and carrying out abstract mapping based on the data path of the starting node to obtain a first abstract graph.
3. The method of claim 1, wherein the obtaining all transmission data transmitted through the TDM block from the signal connection data and storing the transmission data through the hash table comprises:
screening transmission data of all TDM program blocks from the signal connection data;
determining a TDM transmitting program block-circuit line-TDM receiving program block data pair corresponding to the transmission data according to the current type of the TDM program block, the information transmission direction and the data transmission corresponding relation;
all TDM transmit block-circuit line-TDM receive block data pairs are stored by a hash table.
4. A method according to claim 3, wherein said determining a TDM transmit block-circuit line-TDM receive block data pair corresponding to said transmission data based on a current type of said TDM block, an information transmission direction, and said data transmission correspondence comprises:
determining the current type of a first TDM program block corresponding to the transmission data, and determining the signal interest rate, the signal delay value and the corresponding information transmission direction corresponding to the current type of the first TDM program block;
determining a second FPGA chip where a second TDM program block is located based on the information transmission direction;
determining the second TDM program block corresponding to the transmission data in the second FPGA chip;
and determining TDM transmitting program block-circuit line-TDM receiving program block data pairs corresponding to the transmission data according to the first TDM program block, the second TDM program block, the information transmission direction, the signal interest rate and the signal delay value.
5. A cross-FPGA chip static analysis apparatus comprising TDM blocks, the apparatus comprising:
the first mapping module is used for analyzing signal connection data among different FPGA chips from the segmentation file, and carrying out abstract mapping on the connection of the different FPGA chips in the system according to the signal connection data to obtain a first abstract graph;
the hash table construction module is used for acquiring all transmission data transmitted through the TDM program blocks from the signal connection data when the TDM program blocks exist in the FPGA chip, and storing the transmission data through a hash table;
the second mapping module is used for adjusting the TDM program blocks in the first abstract graph to be points based on the hash table and generating a directed acyclic graph;
and the analysis display module is used for acquiring the delay information of the TDM program blocks according to the hash table, marking the delay information on the directed acyclic graph, and obtaining a static analysis graph for displaying the delay information of each TDM program block.
6. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor implements the steps of the method of any of claims 1 to 4 when the computer program is executed.
7. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the method according to any one of claims 1 to 4.
CN202310507876.4A 2023-05-08 2023-05-08 Cross-FPGA chip static analysis method, device, equipment and medium containing TDM program blocks Pending CN116467979A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117787162A (en) * 2023-12-27 2024-03-29 苏州异格技术有限公司 Multi-terminal-angle static time sequence analysis method, device, computer equipment and medium

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117787162A (en) * 2023-12-27 2024-03-29 苏州异格技术有限公司 Multi-terminal-angle static time sequence analysis method, device, computer equipment and medium

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