CN116449245A

CN116449245A - Burr detector

Info

Publication number: CN116449245A
Application number: CN202211601470.4A
Authority: CN
Inventors: 王则坚
Original assignee: MediaTek Inc
Current assignee: MediaTek Inc
Priority date: 2022-01-14
Filing date: 2022-12-13
Publication date: 2023-07-18

Abstract

The invention provides a burr detector, which comprises a first logic circuit, a second logic circuit, a first capacitor and a second capacitor. The first logic circuit is connected between a supply voltage and a ground voltage and is configured to receive a first signal at a first node to generate a second signal to a second node. The second logic circuit is connected between a power supply voltage and a ground voltage and is configured to receive a second signal at a second node to generate a first signal to the first node. A first pole of the first capacitor is coupled to the supply voltage, and a second pole of the first capacitor is coupled to the first node. The first electrode of the second capacitor is coupled to the ground voltage, and the second electrode of the second capacitor is coupled to the second node. The invention can improve the accuracy of burr detection.

Description

Burr detector

Technical Field

Embodiments of the present invention relate generally to detection technology and, more particularly, to a burr detector with high reliability.

Background

A hacker injects a power burr (power burrs) into a chip (chip) to interrupt its operation, thereby implanting malware to gain control over the chip. In order to prevent the chip from being damaged by fault injection such as power supply burrs, one or more burr detectors are designed inside the chip to detect whether the chip has power supply burrs or not, and if the power supply burrs are detected, the chip can take appropriate action to avoid being implanted with malicious software. However, the conventional burr detector cannot accurately detect burrs (glitches).

Disclosure of Invention

In view of this, the following summary is illustrative only and is not intended to be in any way limiting. That is, the following summary is provided to introduce a selection of concepts, emphasis, benefits, and advantages of the novel and non-obvious techniques described herein. Selected embodiments are further described in the detailed description below. Accordingly, the following summary is not intended to identify essential features of the claimed subject matter, nor is it intended to be used to determine the scope of the claimed subject matter.

The invention aims to provide a burr detector which can improve the accuracy of detecting burrs.

In a first aspect, the present invention provides a burr detector comprising: a first logic circuit coupled between a power supply voltage and a ground voltage for receiving a first signal at a first node to generate a second signal to a second node; a second logic circuit coupled between the power supply voltage and the ground voltage for receiving the second signal at the second node to generate the first signal to the first node; a first capacitor having a first pole coupled to the power supply voltage and a second pole coupled to the first node; and a second capacitor having a first electrode coupled to the ground voltage and a second electrode coupled to the second node.

In some embodiments, the spur detector further comprises: the warning signal generator is coupled to the first node or the second node, and is configured to determine whether the power supply voltage has an undervoltage glitch according to a voltage level of the first signal or a voltage level of the second signal, so as to determine whether to output a warning signal.

In some embodiments, the first signal has a first logic value and the second signal has a second logic value different from the first logic value when the supply voltage is not subject to undervoltage glitches; and after the power supply voltage is subjected to undervoltage burr, the warning signal generator determines whether the power supply voltage is subjected to undervoltage burr by detecting whether the first signal is changed to the second logic value or detecting whether the second signal is changed to the first logic value.

In some embodiments, the spur detector further comprises: at least one first discharging path coupled to the first node for selectively charging/discharging charges of the first node; and at least one second discharging path coupled to the second node for selectively charging/discharging charges of the second node.

In some embodiments, when the power supply voltage is undervoltage and glitch occurs, the at least one first discharging path charges/discharges the charge of the first node, and the at least one second discharging path charges/discharges the charge of the second node.

In some embodiments, the at least one first discharge path includes a first P-type transistor for selectively providing a current path between the power supply voltage and the first node, and a first N-type transistor for selectively providing a current path between the ground voltage and the first node.

In some embodiments, the at least one second discharge path includes a second P-type transistor for selectively providing a current path between the supply voltage and the second node, and a second N-type transistor for selectively providing a current path between the ground voltage and the second node.

In some embodiments, each of the first P-type transistor, the first N-type transistor, the second P-type transistor, and the second N-type transistor is a diode-connected transistor.

In some embodiments, the first logic circuit and the second logic circuit include an inverter, a nand gate, and/or a nor gate.

In a second aspect, the present invention provides a burr detector comprising: a first logic circuit coupled between a power supply voltage and a ground voltage for receiving a first signal at a first node to generate a second signal to a second node; a second logic circuit coupled between the power supply voltage and the ground voltage for receiving the second signal at the second node to generate the first signal to the first node; at least one first discharging path coupled to the first node for selectively charging/discharging charges of the first node; and at least one second discharging path coupled to the second node for selectively charging/discharging charges of the second node.

These and other objects of the present invention will be readily understood by those skilled in the art after reading the following detailed description of the preferred embodiments as illustrated in the accompanying drawings. The detailed description will be given in the following embodiments with reference to the accompanying drawings.

Drawings

The accompanying drawings, in which like numerals indicate like components, illustrate embodiments of the invention. The accompanying drawings are included to provide a further understanding of embodiments of the disclosure, and are incorporated in and constitute a part of the embodiments of the disclosure. The drawings illustrate implementations of embodiments of the present disclosure and, together with the description, serve to explain principles of embodiments of the present disclosure. It is to be understood that the drawings are not necessarily to scale, because some components may be shown out of scale from actual implementation to clearly illustrate the concepts of the embodiments of the disclosure.

Fig. 1A is a schematic diagram of a burr detector according to an embodiment of the invention.

Fig. 1B is a schematic diagram of a burr detector according to an embodiment of the invention.

Fig. 1C is a schematic diagram of a spur detector according to an embodiment of the present invention.

Fig. 2 shows that the discharging path of the glitch detector can shorten the reset time when the under-voltage glitch occurs.

Fig. 3 is a schematic diagram of a spur detector according to an embodiment of the present invention.

Fig. 4 shows that the capacitor can pull up signal Vm and pull down signal Vmb after the under-voltage glitch, according to an embodiment of the invention.

Fig. 5 is a schematic diagram of a spur detector according to an embodiment of the present invention.

In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of embodiments of the invention. It will be apparent, however, that one or more embodiments may be practiced without these specific details, and that different embodiments may be combined as desired and should not be limited to the embodiments set forth in the drawings.

Detailed Description

The following description is of preferred embodiments of the invention, which are intended to illustrate the technical features of the invention, but not to limit the scope of the invention. Certain terms are used throughout the description and claims to refer to particular elements, and it will be understood by those skilled in the art that manufacturers may refer to a like element by different names. Therefore, the present specification and claims do not take the difference in names as a way of distinguishing elements, but rather take the difference in functions of elements as a basis for distinction. The terms "element," "system," and "apparatus" as used in the present invention may be a computer-related entity, either hardware, software, or a combination of hardware and software. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to …". Furthermore, the term "coupled" means an indirect or direct electrical connection. Thus, if one device is coupled to another device, that device can be directly electrically connected to the other device or indirectly electrically connected to the other device through other devices or connection means.

Wherein corresponding numerals and symbols in the various drawings generally refer to corresponding parts, unless otherwise indicated. The drawings are clearly illustrative of relevant portions of the embodiments and are not necessarily drawn to scale.

The term "substantially" or "approximately" as used herein means that within an acceptable range, a person skilled in the art can solve the technical problem to be solved, substantially to achieve the technical effect to be achieved. For example, "substantially equal" refers to a manner in which a technician can accept a certain error from "exactly equal" without affecting the accuracy of the result.

Fig. 1A is a schematic diagram of a burr detector (glove detector) 100 according to an embodiment of the invention. As shown in fig. 1A, a glitch detector (e.g., latch-type glitch detector) 100 includes a latch (latch) that generates signals Vm and Vmb at nodes N1 and N2, respectively, and the present invention can determine whether an over-power glitch occurs based on the signals Vm and/or Vmb at the nodes N1 and/or N2 of the latch, that is, the latch is used to present a detection result indicating the power glitch. For example (see fig. 2), before the occurrence of the power supply glitch, the signal Vm has a low level, the signal Vmb has a high level, and when the power supply glitch occurs (for example, the glitch causes the power supply voltage VDD to decrease to the ground voltage VSS, such as 0V), the signal Vmb will decrease, when the signal Vmb decreases to near Vm (i.e., vmb and Vm are substantially the same/equal), if the power supply voltage VDD returns to normal, the inverters 310 and 320 normally operate, vm will probabilistically (e.g., 50%) become high level, and correspondingly, if Vm is high level, vmb is low level, so that it can be known from the signals Vm and Vmb whether the power supply glitch has just occurred when the power supply voltage VDD returns to normal. In an example, the latch includes two logic circuits (e.g., inverters 110 and 120 connected in a latch type), which are illustrated as inverters 110 and 120 in this embodiment, but the present invention is NOT limited thereto. For example, as shown in fig. 1B and 1C, the latch may also be implemented by a logic circuit such as a NAND gate (NAND), a NOR gate (NOR), and in the example of fig. 1B and 1C, the signals SET and RESET are RESET/SET signals as will be understood. In the example embodiment of fig. 1A, each of the inverter 110 and the inverter 120 may be implemented by using a P-type transistor and an N-type transistor connected between a supply voltage (also referred to as a "supply voltage") VDD and a ground voltage (ground voltage) VSS, the inverter 110 being configured to receive the signal Vm at the node N1 to generate the signal Vmb at the node N2, and the inverter 120 being configured to receive the signal Vmb at the node N2 to generate the signal Vm at the node N1. Furthermore, the glitch detector 100 further includes a plurality (e.g., four are shown in fig. 1A) of discharging paths (discharging paths), and the discharging paths may be implemented by using P-type transistors MP1, MP2 (e.g., diode-connected, i.e., the control terminal (e.g., gate terminal) and source terminal of the transistors are coupled together) and N-type transistors MN1 and MN2 (e.g., diode-connected), wherein the P-type transistor MP1 is configured to selectively provide a current path (current path, also referred to as "current path") between the power supply voltage VDD and the node N1, the P-type transistor MP2 is configured to selectively provide a current path between the power supply voltage VDD and the node N2, the N-type transistor MN1 is configured to selectively provide a current path between the node N1 and a ground voltage, and the N-type transistor MN2 is configured to selectively provide a current path between the node N2 and the ground voltage. For example, in normal situations (e.g., when no power supply glitch occurs on the supply voltage and ground voltage), the transistors MP1, MP2, MN1, and MN2 are off, and the parasitic diodes (which may also be described as "body diodes") within these transistors are also non-conductive, so that the transistors MP1, MP2, MN1, and MN2 do not provide a current path between the respective nodes. When a supply glitch occurs at the supply voltage VDD and/or the ground voltage VSS (for example, an undervoltage glitch occurs at the supply voltage VDD such that the supply voltage VDD drops, in particular, for example, below the threshold voltage Vth of the on transistor), then, on the one hand, the voltage of the signal Vmb at the node N2 drops due to the action of the parasitic diode in the latch (for example, the parasitic diode/body diode of the transistor in the inverter), and on the other hand, the voltage of the signal Vmb at the node N2 also forms a discharge path/current path from the second node to the supply voltage VDD due to the action of the parasitic diode/body diode between the drain (drain) to the source (source) of the P-type transistor MP2 such that the voltage at the second node N2 is reduced more rapidly (as can be seen from the graph shown in fig. 2: in the embodiment with MP1/MP2/MN1/MN2, the voltage drop of the signal Vmb is faster, i.e. the voltage drop speed of the undervoltage occurs at the supply voltage VDD) can be detected more accurately and the same time as the reset voltage glitch occurs. It should be noted that the present invention is not limited to detecting a power supply glitch on the power supply voltage VDD, but may be used to detect a glitch on the ground voltage VSS (e.g., a glitch that causes the voltage of the ground voltage VSS to rise), and in some cases, the glitch may even cause the ground voltage VSS to have a higher potential than the power supply voltage VDD, or an undervoltage glitch may cause the power supply voltage VDD to drop significantly or even lower than the ground voltage VSS. As can be understood, as shown in fig. 2, vm=0 initially, so that the parasitic capacitance between VDD and Vm has a voltage of VDD, and the voltage of the parasitic capacitance between Vm and VSS is 0; when the burr occurs such that VSS is higher than VDD, the voltage of Cvdd-Vm (parasitic capacitance between VDD and Vm) may decrease, and the voltage of Cvss-Vm (parasitic capacitance between Vm and VSS) may increase, and thus, the voltage increase may be represented as charge and the voltage decrease may be represented as discharge. For example, in some embodiments, when a power supply glitch occurs at the power supply voltage VDD such that the power supply voltage VDD decreases and/or a glitch occurs at the ground voltage VSS such that the ground voltage VSS increases (e.g., such that the voltage level at the power supply voltage VDD is lower than the voltage level at the ground voltage VSS), on the one hand, the voltage of the signal Vmb at the node N2 decreases due to the effect of the parasitic diode in the latch (e.g., the parasitic diode/body diode of the transistor within the inverter), on the other hand, the voltage of the signal Vmb at the node N2 is also decreased faster due to the parasitic diode/body diode between the drain and source of the P-type transistor MP2, and the voltage level of the ground voltage VSS is higher than the voltage level of the power supply voltage VDD due to the glitch, so that the transistor MP2 is turned on (at this time, the voltage of the terminal at which the transistor MP2 is connected to the node N2 is higher than the voltage of its control terminal, so that MP2 is turned on, i.e., the transistor MP2 exhibits an on resistance), and thus the voltage of the signal b at the node N2 can be decreased faster; meanwhile, since the burr makes the voltage of the ground voltage VSS higher than the voltage of the power supply voltage VDD at this time, the transistor MN2 is turned on (i.e., the transistor MN2 exhibits an on-resistance), thereby forming a discharging path from the ground voltage VSS to the power supply voltage VDD via the second node N2, so that the signal Vmb of the second node N2 can be more quickly approximated to the signal Vm of the first node N1; similarly, since the burr makes the voltage of the ground voltage VSS higher than the voltage of the power supply voltage VDD, both the transistors MN1 and MP1 are turned on, i.e., a current path from the ground voltage VSS to the power supply voltage VDD via the first node N1 is formed, and eventually, vm and Vmb will reach substantially the same potential. It follows that the transistors MP1/MP2/MN1/MN2 may appear to be off or providing a current path (e.g., parasitic diodes within the transistors are on and/or the transistors are on) in circuit operation depending on the actual voltage conditions of the circuit, i.e., the current path can be selectively provided autonomously, without requiring additional control by control signals and/or control circuitry to shorten the reset time to enable more accurate detection of glitches. For example, when no power glitch occurs, the current path is not on; at least one current path (e.g., the current path in which MP2 is located) is automatically turned on when a power glitch occurs, e.g., in the example in which a power glitch occurs but the potential of the power supply voltage VDD is still higher than the ground voltage VSS, the current path in which MP2 is located is automatically turned on (e.g., a current path to the power supply voltage VDD is formed via a parasitic diode within MP 2), and, for example, in the example in which a power glitch occurs but the potential of the ground voltage VSS becomes higher than the power supply voltage VDD, the current paths in which MP1, MP2, MN1, MN2 are all automatically turned on. Therefore, in the embodiment of the present invention, the diode-connected transistors MP1, MN1 and MP2, MN2 as shown in fig. 1A can selectively provide the current paths/current paths to the nodes N1 and N2, i.e., can selectively charge/discharge the nodes N1 and N2. It should be noted that the embodiments of the present invention should not be limited to the four discharge paths shown in the drawings, for example, in some embodiments, only the P-type transistor MP2 may be included, and in other embodiments, the P-type transistor MP2 and the N-type transistor MN2 may be included.

The glitch detector 100 is configured to detect an under-voltage glitch (i.e., a glitch that causes the power supply voltage VDD to drop, for example, a power supply glitch that causes the power supply voltage VDD to be lower than the threshold voltage Vth (which may also be described as "threshold voltage Vth of a transistor") that causes the transistor to be turned on, according to the voltage level (which may also be described as "voltage level") of the signal Vm or the signal Vmb. In particular, when the power supply voltage VDD has a normal (normal) voltage level (i.e., a logic value of "1") (i.e., when there is no glitch on the power supply voltage VDD), the signal Vm is controlled to have a low voltage level (i.e., a logic value of "0"), and the signal Vmb is controlled to have a high voltage level (i.e., a logic value of "1"). Then, when the glitch detector 100 encounters an under-voltage glitch (also described as "present", "suffering", "encountering", etc.) (e.g., when the supply voltage VDD is glitched such that the supply voltage drops), the voltage level of the signal Vmb will drop. Finally, when the power supply voltage VDD returns to the original (original) voltage level (i.e., normal voltage level, logic value "1") there is a certain probability (e.g., 50%) that the signal Vm is at a high voltage level. Thus, once the signal Vm has a high voltage level, the glitch detector 100 can determine that the chip is under-voltage glitch, and optionally can further trigger the alert signal generator (warning signal generator) 130 to notify the processing circuit of the under-voltage glitch of the supply voltage VDD, thereby facilitating the processing circuit to take some appropriate action. After the warning signal generator 130 notifies the processing circuit, a reset circuit (not shown) can control the signals Vm and Vmb to have a low voltage level and a high voltage level, respectively, to determine the next undervoltage glitch.

In another embodiment, the alarm signal generator 130 may be connected to the node N2, and the alarm signal generator 130 is triggered to output an alarm signal when the signal Vmb becomes a logic value "0". Such alternative designs should fall within the scope of the invention. It will be appreciated that when the power supply voltage VDD drops to a logic value of "0" due to the power supply glitch, the signal Vmb will ideally change to a logic value of "0" (i.e. the same voltage as Vm), at which time, since the glitch causes the power supply voltage VDD to be a logic value of 0, the alert signal generator 130 will typically not operate properly for the duration of the glitch present, and therefore, until the glitch is removed (i.e. when the power supply voltage VDD returns to normal, or is described as "after the glitch occurs in the power supply voltage"), the alert signal generator 130 will not be able to learn from the signals Vm and/or Vmb whether the glitch has just occurred. For example, a glitch may be considered to occur if the signal Vm is detected to be high and/or Vmb is detected to be low.

Conventional spur detectors do not detect a spur with high accuracy, e.g. are not able to detect short spurs (i.e. spurs of short duration, e.g. nanoseconds (10 ^-9 S) level of burrs). To solve this problem, P-type transistors MP1, MP2 and N-type transistors MN1, MN2 are used in the glitch detector 100 so that the voltages of the second node and the first node can be more quickly brought close to the same, i.e., the reset time (reset time) in response to the under-voltage glitch is reduced so that the glitch detector 100 can detect the short glitch. In particular, referring to fig. 2, if the glitch detector 100 does not have the P-type transistors MP1, MP2 and the N-type transistors MN1, MN2, when the under-voltage glitch occurs in the power supply voltage VDD, the glitch detector 100 requires a longer reset time to make the voltage level of the signal Vmb approach/substantially equal to the voltage level of the signal Vm (assuming that the power supply voltage VDD drops to the ground voltage), and then, when the power supply voltage VDD is restored to the original voltage level, the signal Vm can have a certain probability (e.g., 50%) to be represented as a high voltage level. On the other hand, if the glitch detector 100 has P-type transistors MP1, MP2 and N-type transistors MN1, MN2 for selectively charging/discharging the charges of the nodes N1, N2 when a glitch occurs (e.g., an undervoltage glitch occurs in the power supply voltage VDD), or is described as "selectively forming a current path through the nodes N1, N2"), only a short reset time is required to bring the voltage level of the signal Vmb close to the voltage level of the signal Vm. Therefore, the burr detector 100 can detect short burrs, thereby improving the accuracy of detecting burrs.

Fig. 3 is a schematic diagram of a spur detector 300 according to an embodiment of the present invention. As shown in fig. 3, glitch detector 300 includes a latch that includes two logic circuits (e.g., two inverters connected in a latch-type manner), which in this embodiment are inverters 310 and 320. Each of the inverter 310 and the inverter 320 may be implemented by using a P-type transistor and an N-type transistor connected between the power supply voltage VDD and the ground voltage, the inverter 310 for receiving the signal Vm at the node N1 to generate the signal Vmb at the node N2, and the inverter 320 for receiving the signal Vmb at the node N2 to generate the signal Vm at the node N1. In addition, the burr detector 300 further includes capacitors (capacitors) C1 and C2. The capacitor C1 is coupled between the power voltage VDD and the node N1, i.e., one pole (also referred to as "one end") of the capacitor C1 is coupled to the power voltage VDD, and the other pole (the other end) of the capacitor C1 is coupled to the node N1. The capacitor C2 is coupled between the node N2 and the ground voltage, i.e., one pole of the capacitor C2 is coupled to the ground voltage, and the other pole of the capacitor C2 is coupled to the node N2, wherein the capacitors C1 and C2 are intentionally provided in the glitch detector 300, i.e., the capacitors C1 and C2 are not parasitic capacitances (parasitic capacitance).

In an example embodiment, spur detector 300 is configured to detect undervoltage spur from the voltage level of signal Vm or signal Vmb. In particular, when the power supply voltage VDD has a normal voltage level (e.g., in a normal case where no glitch occurs), the signal Vm is controlled to have a low voltage level (i.e., a logic value "0"), and the signal Vmb is controlled to have a high voltage level (i.e., a logic value "1"). Then, when the glitch detector 300 develops an under-voltage glitch (e.g., an under-voltage glitch occurs at the supply voltage VDD), the signal Vmb will drop to a voltage level close to the supply voltage VDD (in the case of a glitch occurring at the supply voltage VDD). Finally, when the supply voltage VDD returns to the original voltage level, the signal Vm will have a high voltage level, while the signal Vmb has a low voltage level. Thus, once the signal Vm has a high voltage level, the glitch detector 300 can determine that the chip is undervoltage glitch and trigger the alert signal generator 330 to notify the processing circuitry of the undervoltage glitch of the supply voltage VDD. After the alert signal generator 330 notifies the processing circuitry, a reset circuit (not shown) can control the signals Vm and Vmb to have a low voltage level and a high voltage level, respectively, to determine the next undervoltage glitch.

In another embodiment, the alarm signal generator 330 is connected to the node N2, and the alarm signal generator 330 is triggered to output an alarm signal when the signal Vmb becomes a logic value "0". Such alternative designs should fall within the scope of the invention.

As described in the background of the invention, conventional spur detectors do not always output an alarm signal when a power spur occurs, i.e. the signal Vm may still have a low voltage level after an under-voltage spur has occurred, i.e. the accuracy of detecting the power spur is not high. In an embodiment of the present invention, if the under-voltage glitch is such that the supply voltage is lower than VDD/2, for example, more particularly, as long as the under-voltage glitch is such that the supply voltage is lower than the threshold voltage of the transistors in the inverter 310/320 (i.e., the inverter is not able to operate properly, that is, the under-voltage glitch will change the logic value of the inverter output), the capacitors C1 and C2 can ensure that the signal Vm has a high voltage level all the time after the under-voltage glitch has passed. In particular, referring to fig. 4, initially, the power supply voltage VDD is at a normal level (e.g., 1V, it should be noted that 1V is only described as an example, and the present invention is not limited thereto), the signal Vm is at a low voltage level (e.g., VSS, 0V), and the signal Vmb is at a high voltage level (e.g., 1V), at which time the cross voltage (cross voltage) of each of the capacitors C1 and C2 is about VDD (e.g., 1V). When the power supply voltage VDD develops an undervoltage glitch, for example, the power supply voltage drops to (1/3) ×vdd (e.g., 0.3V), the voltage level of the signal Vmb also drops to (1/3) ×vdd (e.g., 0.3V) due to the P-type transistor in the inverter 310. At this time, the voltage across each of the capacitors C1 and C2 is about (1/3) ×vdd (e.g., 0.3V). Then, when the power supply voltage VDD returns to the original voltage level (e.g., 1V), the voltage across the capacitor C1 pulls the signal Vm high (e.g., from 0V up to VDD minus the voltage across the capacitor C1) because the voltage across the capacitor cannot change suddenly, i.e., the power supply voltage VDD returns from the reduced voltage (e.g., (1/3) VDD, such as 0.3V) to the normal voltage (e.g., VDD, such as 1V), and the voltage level of the signal Vm b is still (1/3) VDD. In addition, when the power supply voltage VDD is restored to be normal (the inverters 310 and 320 can normally operate), since the voltage level of the signal Vm is higher than the voltage level of the signal Vmb, the inverters 310 and 320 form a positive feedback loop, and thus when the power supply voltage VDD is restored to the original voltage level, the signal Vm is pulled up (e.g., pulled up to be close to the power supply voltage VDD) and the signal Vmb is pulled down (e.g., pulled down to be close to the ground voltage VSS). That is, after the undervoltage burr vanishes/eliminates (dispears), the signal Vm is equal to the logic value "1", and the signal Vmb is equal to the logic value "0". However, in the case where the capacitors C1 and C2 are not present, before the glitch occurs and the power supply voltage VDD returns to normal, the voltage level of the signal Vm is a low voltage level (e.g., VSS, 0V), the voltage level of the signal Vmb is (1/3) ×vdd (e.g., 0.3V), and when the power supply voltage VDD returns to normal, since the inverters 310 and 320 constitute a positive feedback structure, the higher one of the signals Vm and Vmb rapidly approaches the power supply voltage VDD, and the other one approaches the ground voltage VSS, that is, when the power supply voltage VDD returns to normal, the signal Vmb is a high voltage level (e.g., VDD), and the signal Vm is a low voltage level (e.g., VSS), so that the occurrence of the glitch cannot be detected by the signals Vmb and Vm. Therefore, burrs occurring at the power supply voltage VDD can be accurately detected by deliberately arranging the capacitors C1 and C2, that is, the accuracy of detecting burrs is improved, and short burrs can be more accurately detected than in the case of not having the capacitors C1 and C2.

Referring to the embodiment shown in fig. 3 and 4, when a significant (meaningfull) under-voltage glitch occurs in the power supply voltage VDD (e.g., a glitch that causes the power supply voltage VDD to be lower than the threshold voltage Vth), the signal Vm will always be at a high voltage level to trigger the alert signal generator 330 to notify the processing circuit so that the glitch detector 300 will not miss any significant under-voltage glitch, thereby improving reliability.

In alternative embodiments, the spur detector 100 shown in fig. 1A and the spur detector 300 shown in fig. 3 may be combined so that the spur detector is able to detect shorter spurs without missing any significant power supply spurs. That is, the burr detector 100 may be modified to: capacitors C1 and C2 shown in fig. 3 are added; alternatively, the burr detector 300 may be modified to: transistors MP1, MP2, MN1, and MN2 shown in fig. 1A are added. Fig. 5 is a schematic diagram illustrating a spur detector 500 according to an embodiment of the present invention. As shown in fig. 5, the glitch detector 500 includes a latch, for example, two latch-type connected logic circuits, which in this embodiment are inverters 510 and 520. Each of the inverter 510 and the inverter 520 may be implemented by a P-type transistor and an N-type transistor connected between the power supply voltage VDD and the ground voltage, the inverter 510 for receiving the signal Vm at the node N1 to generate the signal Vmb at the node N2, and the inverter 520 for receiving the signal Vmb at the node N2 to generate the signal Vm at the node N1. In addition, the glitch detector 500 further includes four discharging paths, and these discharging paths are implemented by using P-type transistors MP1, MP2 for selectively providing a current path between the power supply voltage VDD and the node N1, and N-type transistors MN1, MN2 for selectively providing a current path between the node N1 and the ground voltage, and P-type transistor MP2 for selectively providing a current path between the node N2 and the ground voltage. The spur detector 500 further includes capacitors C1 and C2. The capacitor C1 is coupled between the power supply voltage VDD and the node N1, and the capacitor C2 is coupled between the node N2 and the ground voltage, wherein the capacitors C1 and C2 are intentionally provided in the glitch detector 500, i.e., the capacitors C1 and C2 are not parasitic capacitances. The glitch detector 500 may further include an alert signal generator 530, wherein the alert signal generator 530 outputs an alert signal when the signal Vm changes from a low voltage level to a high voltage level. For a similar description, please refer to the embodiment shown in fig. 1A and fig. 3, and the description of the same parts will not be repeated here for brevity.

In the present embodiment, some or all of the P-type transistors MP1, MP2 and the N-type transistors MN1, MN2 are used to charge/discharge the charges of the nodes N1, N2 when a glitch (e.g., an under-voltage glitch) occurs, and the capacitors C1, C2 are used to pull up the signal Vm and pull down the signal Vmb when the glitch (e.g., the under-voltage glitch) disappears. Therefore, the burr detector 500 is able to detect short burrs and the accuracy of detecting burrs is improved without missing any significant under-voltage burrs.

In the claims, ordinal terms such as "first," "second," "third," etc., are used to modify a claim element, and do not by itself connote any priority, precedence, or order of one claim element over another or the temporal order in which acts of a method are performed, but are used merely as labels to distinguish one claim element having a same name from another claim element having a same name using the ordinal term.

While the invention has been described by way of example and in terms of preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as will be apparent to those skilled in the art), e.g., combinations or alternatives of the different features in the different embodiments. The scope of the following claims is, therefore, to be accorded the broadest interpretation so as to encompass all such modifications and similar structures.

Claims

1. A spur detector, comprising:

a first logic circuit coupled between a power supply voltage and a ground voltage for receiving a first signal at a first node to generate a second signal to a second node;

a second logic circuit coupled between the power supply voltage and the ground voltage for receiving the second signal at the second node to generate the first signal to the first node;

a first capacitor having a first pole coupled to the power supply voltage and a second pole coupled to the first node; the method comprises the steps of,

a second capacitor having a first electrode coupled to the ground voltage and a second electrode coupled to the second node.

2. The spur detector as in claim 1, further comprising:

the warning signal generator is coupled to the first node or the second node, and is configured to determine whether the power supply voltage has an undervoltage glitch according to a voltage level of the first signal or a voltage level of the second signal, so as to determine whether to output a warning signal.

3. The glitch detector of claim 2 in which the first signal has a first logic value and the second signal has a second logic value different from the first logic value when the undervoltage glitch is not occurring in the supply voltage; and after the power supply voltage is subjected to undervoltage burr, the warning signal generator determines whether the power supply voltage is subjected to undervoltage burr by detecting whether the first signal is changed to the second logic value or detecting whether the second signal is changed to the first logic value.

4. The spur detector as in claim 1, further comprising:

at least one first discharging path coupled to the first node for selectively charging/discharging charges of the first node; the method comprises the steps of,

at least one second discharging path coupled to the second node for selectively charging/discharging the charge of the second node.

5. The glitch detector of claim 4, in which the at least one first discharge path charges/discharges the charge of the first node and the at least one second discharge path charges/discharges the charge of the second node when the undervoltage glitch occurs.

6. The spur detector of claim 4, wherein the at least one first discharge path comprises a first P-type transistor and a first N-type transistor, the first P-type transistor being configured to selectively provide a current path between the supply voltage and the first node, and the first N-type transistor being configured to selectively provide a current path between the ground voltage and the first node.

7. The spur detector of claim 6, wherein the at least one second discharge path comprises a second P-type transistor and a second N-type transistor, the second P-type transistor for selectively providing a current path between the supply voltage and the second node, and the second N-type transistor for selectively providing a current path between the ground voltage and the second node.

8. The spur detector of claim 7, wherein each of the first P-type transistor, the first N-type transistor, the second P-type transistor, and the second N-type transistor is a diode-connected transistor.

9. The spur detector of claim 1, wherein the first logic circuit and the second logic circuit comprise inverters, nand gates, or nor gates.

10. A spur detector, comprising:

at least one second discharging path coupled to the second node for selectively charging/discharging charges of the second node.

11. The spur detector as in claim 10, further comprising:

12. The glitch detector of claim 11 in which the first signal has a first logic value and the second signal has a second logic value different from the first logic value when the undervoltage glitch is not occurring in the supply voltage; and after the power supply voltage is subjected to undervoltage burr, the warning signal generator determines whether the power supply voltage is subjected to undervoltage burr by detecting whether the first signal is changed to the second logic value or detecting whether the second signal is changed to the first logic value.

13. The glitch detector of claim 10 in which the at least one first discharge path charges/discharges the charge of the first node and the at least one second discharge path charges/discharges the charge of the second node when the supply voltage is undervoltage glitch occurs.

14. The spur detector of claim 10, wherein the at least one first discharge path comprises a first P-type transistor and a first N-type transistor, the first P-type transistor being configured to selectively provide a current path between the supply voltage and the first node, and the first N-type transistor being configured to selectively provide a current path between the ground voltage and the first node.

15. The spur detector of claim 14, wherein the at least one second discharge path comprises a second P-type transistor and a second N-type transistor, the second P-type transistor being configured to selectively provide a current path between the supply voltage and the second node, and the second N-type transistor being configured to selectively provide a current path between the ground voltage and the second node.

16. The spur detector of claim 15, wherein each of the first P-type transistor, the first N-type transistor, the second P-type transistor, and the second N-type transistor is a diode-connected transistor.

17. The spur detector of claim 10, wherein the first logic circuit and the second logic circuit comprise an inverter, a nand gate, and/or a nor gate.