CN116436289A

CN116436289A - Minimum on-time clamping circuit, DCDC converter and control module thereof

Info

Publication number: CN116436289A
Application number: CN202310315783.1A
Authority: CN
Inventors: 李林真; 林涛; 虞海燕
Original assignee: Suzhou Novosense Microelectronics Co ltd
Current assignee: Suzhou Novosense Microelectronics Co ltd
Priority date: 2023-03-28
Filing date: 2023-03-28
Publication date: 2023-07-14

Abstract

The application discloses a minimum on-time clamping circuit, a DCDC converter and a control module thereof, wherein the minimum on-time clamping circuit is applied to the DCDC converter, and the DCDC converter controls electric energy conversion through the switching action of a controllable device; the minimum on-time clamping circuit is configured to obtain a modulation current by modulating the programmable current in a charging and discharging process according to the on-time of the controllable device, so that the modulation current is clamped in a set range when the on-time of the controllable device is smaller than a set threshold value; the modulating current is used for charging and discharging the capacitor to generate a clock signal with a set frequency. The method and the device realize self-adaptive adjustment of the output current according to the opening time of the controllable device, and further can set the minimum conduction time of the DCDC converter.

Description

Minimum on-time clamping circuit, DCDC converter and control module thereof

Technical Field

The application belongs to the technical field of integrated circuit design, and particularly relates to a minimum conduction time clamping circuit, a DCDC converter and a control module thereof.

Background

The DC-DC converter is a voltage converter that converts an input voltage and then efficiently outputs a fixed voltage. DC-DC converters fall into three general categories, BUCK, BOOST, BUCKBOOST. Various control modes can be adopted according to the needs. PWM control type efficiency is high, and output voltage ripple and noise are good. Even if PFM control is used for a long period of time, there is an advantage of low power consumption especially in the case of a small load. The PWM/PFM conversion realizes PFM control when the load is small, and automatically switches to PWM control when the load is heavy. At present, the DC-DC converter is widely applied to products such as mobile phones, MP3, digital cameras, portable media players and the like. Belongs to the chopper circuit in the circuit type classification.

In recent years, a wide input range, such as 4v to 100v, is demanded for DC-DC converters; a wide operating frequency, such as 300k to 3MHZ, has become a necessity. In this case, a high voltage is input and a low voltage is output, and the system operates at a small duty cycle.

Current DCDC converters generally employ either a peak current mode or a constant on-time (COT) control mode. The switching frequency of the peak current mode is fixed, which is determined by the clock signal CLK generated by the oscillator. If the frequency set outside the system is high frequency operation at this time and the output of the system is a small voltage, i.e. the system will operate at a small duty cycle, in which case the time the upper tube of the DCDC is on will encounter the minimum on time min_on, at which time the output of the error amplifier EA will oscillate, the control loop of the DC-DC converter is open-loop and the operation of the DCDC will enter an erroneous operation state.

Disclosure of Invention

In view of the above problems, an objective of the present application is to provide a minimum on-time clamping circuit, a DCDC converter and a control module thereof, which avoid that the DCDC converter outputs a low voltage at VIN high voltage or vout, and when the on-time hits the minimum on-time min_on under the high operating frequency operating condition, the loop is opened, which causes the DCDC converter to work abnormally and output oscillation.

According to a first aspect of the present application, a minimum on-time clamp circuit is provided, which is applied to a DCDC converter controlling the conversion of electrical energy by a switching action of a controllable device;

the minimum on-time clamping circuit is configured to modulate the programmable current according to the on-time of the controllable device to obtain a modulation current through a charging and discharging process, so that the modulation current is clamped in a set range when the on-time of the controllable device is smaller than a set threshold.

Further, the minimum on-time clamp circuit comprises a first current mirror, a current mirror unit, a first branch, a second branch and a third branch;

the first current mirror mirrors the programmable current input by the first branch into the third branch; the second branch comprises a reference current source, a charging and discharging module and a MOS tube MP0 connected between the reference current source and the charging and discharging module; a modulation voltage output point is arranged between the MOS tube MP0 and the charge-discharge module; the grid electrode of the MOS tube MP0 is connected with the inverse signal of the starting signal of the controllable device; the third branch comprises an MOS tube NM, and the grid electrode of the MOS tube NM is connected with the modulation voltage output point; the current mirror unit is connected with the third branch and the charge-discharge module, and is used for obtaining the modulation current and feeding the modulation current back to the charge-discharge module in a mirror image mode to serve as the discharge current of the modulation voltage output point.

Still further, the first current mirror includes: the MOS tube MN0 is arranged on the first branch, the drain electrode of the MOS tube MN0 is connected with the grid electrode of the MOS tube MN0, and the drain electrode of the MOS tube MN0 is connected with the programmable current;

the MOS tube MN2 is arranged on the third branch, and the grid electrode of the MOS tube MN0 is connected with the grid electrode of the MOS tube MN 2; the source electrode of the MOS tube NM is connected with the drain electrode of the MOS tube MN2 through a resistor Rm.

Still further, the charge-discharge module includes a first charge capacitor Cm and a MOS transistor MN1; the current mirror unit realizes modulation current mirror feedback through the MOS tube MN1;

the drain electrode of the MOS tube MN1 is connected with one end of the first charging capacitor Cm;

the drain electrode of the MOS tube MP0 is connected with the drain electrode of the MOS tube MN1, and the source electrode of the MOS tube MP0 is connected with the reference current source;

the other end of the first charging capacitor Cm is connected with the reference potential point; and a source electrode of the MOS tube MN1 is connected with the reference potential point.

Still further, the current mirror unit includes a second current mirror, a third current mirror, and a fourth current mirror; the minimum on-time clamping circuit further comprises a fourth branch, a fifth branch and an output branch; the second current mirror, the third current mirror and the fourth current mirror are cascode current mirrors;

the second current mirror mirrors the current in the third leg into the fourth leg; the third current mirror mirrors the current in the fourth branch to the fifth branch, the fourth current mirror mirrors the current in the fifth branch to obtain the modulation current, and the modulation current is output through the output branch; the common gate of the third current mirror is connected to the gate of the MOS transistor MN 1.

Still further, the second current mirror includes a MOS transistor MP1 disposed in the third branch and a MOS transistor MP2 disposed in the fourth branch, the third current mirror includes a MOS transistor MN3 disposed in the fourth branch and a MOS transistor MN4 disposed in the fifth branch, and the fourth current mirror includes a MOS transistor MP3 disposed in the fifth branch and a MOS transistor MP4 disposed in the output branch;

the source electrode of the MOS tube MP1 is connected with a power supply, and the drain electrode of the MOS tube MP1 is connected with the drain electrode of the MOS tube NM; the grid electrode of the MOS tube MP1 is connected with the drain electrode of the MOS tube MP 1;

the grid electrode of the MOS tube MP2 is connected with the grid electrode of the MOS tube MP 1; the source electrode of the MOS tube MP2 is connected with a power supply; the drain electrode of the MOS tube MP2 is connected with the drain electrode of the MOS tube MN 3;

the drain electrode of the MOS tube MN3 is connected with the grid electrode of the MOS tube MN3, and the grid electrode of the MOS tube MN3 is connected with the grid electrode of the MOS tube MN1; the source electrode of the MOS tube MN3 is connected with the reference potential point;

the grid electrode of the MOS tube MN4 is connected with the grid electrode of the MOS tube MN 3; the source electrode of the MOS tube MN4 is connected with the reference potential point; the drain electrode of the MOS tube MN4 is connected with the drain electrode of the MOS tube MP 3; the source electrode of the MOS tube MP3 is connected with a power supply, the drain electrode of the MOS tube MP3 is connected with the grid electrode of the MOS tube MP3, the grid electrode of the MOS tube MP3 is connected with the grid electrode of the MOS tube MP4, and the source electrode of the MOS tube MP4 is connected with the power supply; the drain electrode of the MOS tube MP4 obtains the modulation current.

Still further, the width ratio of the MOS transistor MN1, the MOS transistor MN3, and the MOS transistor MN4 is 1: b: and B, wherein B is the ratio of the width to the length of the MOS tube.

Still further, by setting the reference current source, a minimum on-time of the controllable device is set.

According to a second aspect of the present application, there is provided a control module of a DCDC converter, comprising:

an oscillator configured to charge and discharge a capacitor by the modulation current to generate a clock signal of a set frequency;

a minimum on-time clamp circuit as provided by any one of the possible implementations of the first aspect; the minimum conduction time clamping circuit is used for outputting the modulation current so that the frequency of a clock signal generated by the oscillator meets the set requirement;

and the switch control unit is used for generating a switch signal of the controllable device according to the clock signal so as to control the conduction state of the controllable device.

According to a third aspect of the present application, there is provided a DCDC converter, the controllable device circuit comprising a high-side device and a low-side device, the high-side device and the low-side device being used to control the transfer of electrical energy from an input to an output;

and a control circuit comprising a control module of the DCDC converter as provided in any one of the possible embodiments of the second aspect, for generating a switching signal to control the on-states of the high-side device and the low-side device.

According to a fourth aspect of the present application, there is provided an electronic device comprising a DCDC converter as provided in any one of the possible embodiments of the third aspect.

The beneficial technical effects that this application obtained:

the minimum on-time clamping circuit provided by the application can modulate the programmable current through the charge-discharge process according to the opening time of a controllable device (such as a high-side device); the modulated current can be set by setting the reference current source, so that the output current can be adaptively adjusted according to the starting time HSon of the high-side device, and the second minimum conduction time min_On2 of the DCDC converter can be set as a set threshold value.

The control module of the DCDC converter adds the minimum conduction time clamping circuit based on the opening time of the controllable device, so as to obtain a frequency modulation loop comprising a switch control unit, the minimum conduction time clamping circuit and an oscillator, and when the conduction time of an upper tube is smaller than a set threshold value, the working frequency of the loop self-adaptive adjustment system is realized; when the system encounters the second minimum conduction time min_on2, the switching frequency is automatically reduced, and the first minimum conduction time min_on1 triggered to the DCDC converter during the small duty ratio duty is avoided, so that the system oscillates.

The DCDC converter can be automatically and smoothly switched between the fixed frequency and the frequency modulation mode, complicated manual control is not needed, or the working frequency is preset according to the input and output voltage, so that the DCDC converter can work in a larger input and output voltage range.

Drawings

The drawings described herein are for illustration purposes only and are not intended to limit the scope of the present disclosure in any way. In addition, the shapes, proportional sizes, and the like of the respective components in the drawings are merely illustrative for aiding the understanding of the present application, and are not particularly limited. Those skilled in the art who have the benefit of the teachings of this application may select various possible shapes and scale dimensions to practice this application as the case may be. In the drawings:

FIG. 1 is a functional schematic of a prior art oscillator module;

FIG. 2 is a schematic diagram of an oscillator frequency modulation principle according to an embodiment of the present disclosure;

FIG. 3 is a schematic circuit diagram of a minimum on-time clamp circuit according to an embodiment of the present application;

FIG. 4 is a schematic diagram of a voltage at a modulation voltage output point Vmodule when the minimum on-time clamp modulation is active in accordance with one embodiment of the present application;

fig. 5 is a schematic structural diagram of a DCDC converter according to an embodiment of the present application;

FIG. 6 is a schematic diagram of an electronic device according to an embodiment of the present disclosure;

reference numerals: 100-DCDC converter, 200-control module, 210-minimum on-time clamp circuit, 220-oscillator, 230-switch control unit, 110-high side device, 120-inductor, 130-low side device, 300-electronic device, 2101-first branch, 2102-second branch, 2103-third branch, 2104-fourth branch, 2105-fifth branch, 2106-power supply, 2107-first current mirror, 2108-charge-discharge module, 2109-second current mirror, 2110-third current mirror, 2111-fourth current mirror, 2112-reference potential point, 2113-reference current source, 2114-modulated voltage output point, 2115-output branch.

Detailed Description

In order to better understand the technical solutions in the present application, the following description will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, shall fall within the scope of the present application.

It should be understood that in the following description, "circuit" refers to an electrically conductive loop formed by at least one element or sub-circuit through electrical or electromagnetic connection. When an element or circuit is referred to as being "connected to" another element or being "connected between" two nodes, it can be directly coupled or connected to the other element or intervening elements may be present, the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled to" or "directly connected to" another element, it means that there are no intervening elements present between the two.

The present application may be presented in various forms, some examples of which are described below.

DCDC converters are also known as DCDC power converters or voltage regulators. The switching control of the DCDC converter may employ a current mode control (e.g., a peak current mode control), the switching frequency of the switching signal being constant, the switching frequency being determined by the clock signal CLK generated by the oscillator. The oscillator may be implemented using any known oscillator circuit known in the art.

The conventional peak current mode DCDC converter may include a current detection unit, a ramp signal generation unit, a PWM comparator unit, an Error Amplifier (EA), and a control circuit. The reference voltage source is connected with the positive input end of the Error Amplifier (EA), the output voltage feedback signal of the DCDC converter is connected with the negative input end of the Error Amplifier (EA), the output end of the Error Amplifier (EA) is connected with the reverse input end of the PWM comparator unit, the positive input end of the PWM comparator unit is respectively connected with the current detection unit and the ramp signal generation unit, the output end of the PWM comparator unit is connected with the control circuit, the control circuit comprises an oscillator, the oscillator generates a clock signal with set frequency, and the control circuit generates a switching signal of the controllable device. It should be noted that the principle of the peak current mode DCDC converter is prior art, and will not be described in detail in this application.

An oscillator circuit of a conventional peak current mode DCDC converter is shown in fig. 1. As shown in fig. 1, the clock frequency of the system is determined by setting a current through an external circuit, so that at a fixed frequency, the programmable current Iprogram is a fixed current value, and similarly, the Ccap capacitor is a capacitor for generating a charge and discharge of the internal clock of the system, and is also a fixed value.

From fig. 1, it can be derived that:

iprogram tclk=cca vref=constant (I)

Wherein Tclk is a fixed frequency of a system clock, cca is a charging capacitor in an oscillator, and Vref is a reference voltage.

Peak current mode is often the first choice for fixed frequency mode operation because a fixed frequency system clock Tclk is generated. The clock frequency generated by the oscillator is fixed, so the switching frequency of the DCDC converter is also fixed. The disadvantage is that when the DCDC converter is operated at a low duty cycle (the ratio between the on-time and the switching period is often referred to as the duty cycle) and at high frequency, the on-time HSon of the upper tube (e.g. the high side device 110 in fig. 5) is shorter and shorter, the upper tube is prone to encounter the minimum on-time min_on, and the DCDC converter system is not operating properly. It is therefore desirable to have the DCDC converter operate at a small duty cycle while at high frequency, limiting the on-time HSon of the high-side device 110 to a set value.

As shown in fig. 2, the present application considers that the programmable current Iprogram is modulated by a charge-discharge process to obtain a modulation current, and can clamp the modulation current within a set range when the programmable current Iprogram works at a low duty cycle and a high frequency, so as to limit the on time HSon of the high-side device 110 to a set value.

The embodiment of the present application provides a minimum on-time clamping circuit 210, which is applied to a DCDC converter 100, wherein the DCDC converter 100 uses controllable devices (including a high-side device 110 and a low-side device 130) to control electric energy to be transmitted from an input terminal to an output terminal, so as to generate an output voltage according to an input voltage; the DCDC converter 100 controls the power conversion by the switching actions of the high-side device 110 and the low-side device 130.

The minimum on-time clamp circuit 210 is configured to obtain the modulation current Icharge by modulating the programmable current Iprogram through a charge-discharge process according to the controllable device on-time (optionally, such as the on-time HSon of the high-side device 110), such that the modulation current Icharge is clamped within a set range when the on-time HSon of the high-side device 110 is less than a set threshold. The modulation current Icharge may be used to charge and discharge a capacitor in the oscillator 220 to generate a clock signal with a set frequency.

According to the embodiment of the application, through the minimum on-time clamping circuit 210, the programmable current Iprogram can be modulated according to the on-time HSon of the high-side device 110 through the charge-discharge process, the modulated current can be set through setting the reference current source 2113, the output current can be adaptively adjusted according to the on-time HSon of the high-side device 110, and then the second minimum on-time min_on2 of the DCDC converter 100 can be set, wherein the second minimum on-time min_on2 is the set threshold.

In a particular embodiment, the minimum on-time clamp 210 includes a first current mirror 2107, a current mirror unit, a first leg 2101, a second leg 2102, and a third leg 2103;

the first current mirror 2107 mirrors the programmable current Iprogram input by the first branch 2101 into the third branch 2103; the second branch 2102 includes a reference current source 2113 and a charge-discharge module 2108, and a MOS transistor MP0 connected between the reference current source 2113 and the charge-discharge module 2108; a modulation voltage output point 2114 is arranged between the MOS tube MP0 and the charge-discharge module 2108; the grid electrode of the MOS tube MP0 is connected with the inverse signal of the starting signal of the high-side device 110; the third branch 2103 comprises a MOS tube NM, and a grid electrode of the MOS tube NM is connected with a modulation voltage output point 2114; the current mirror unit is connected to the third branch 2103 and the charge-discharge module 2108, and is configured to obtain a modulation current Icharge, and mirror-feed the modulation current Icharge back to the charge-discharge module 2108 as a discharge current of the modulation voltage output point 2114.

During the on time HSon of the high-side device 110, the charge and discharge module 2108 is charged by the current Iref output by the reference current source 2113 in the second branch 2102, and when the charge voltage of the charge and discharge module 2108 meets the setting, the MOS transistor MP0 is turned on as a switch. The charge and discharge module 2108 typically includes a charge capacitor. In this application, the third branch 2103 is used to feed back the discharge current of the charge and discharge module 2108, so as to obtain a circuit for charging and discharging the charge and discharge module 2108.

The modulated voltage vmoduate is obtained by discharging the modulated voltage output point 2114 through the charge-discharge module 2108 throughout a period, including the on time HSon and the off time HSoff of the high-side device 110. The MOS transistor NM plays a role in reducing the charging current.

The discharge current is mirrored out by a current mirror unit (e.g., may include the second current mirror 2109, the third current mirror 2110, and the fourth current mirror 2111 shown in fig. 3) to obtain a modulated current Icharge, and the modulated current Icharge is mirrored back to the charge-discharge module 2108 as a discharge current of the modulated voltage output point 2114. By setting the current Iref output by the reference current source 2113, the modulation current can be clamped within a set range when the on-time HSon duty of the high-side device 110 is smaller than a set threshold.

As shown in fig. 3, fig. 3 is a schematic circuit diagram of a minimum on-time clamping circuit 210 according to an embodiment of the present application. The first current mirror 2107 includes: the MOS tube MN0 is arranged on the first branch 2101, the drain electrode of the MOS tube MN0 is connected with the grid electrode of the MOS tube MN0, and the drain electrode of the MOS tube MN0 is connected with the programmable current Iprogram;

the MOS tube MN2 is arranged on the third branch 2103, and the grid electrode of the MOS tube MN0 is connected with the grid electrode of the MOS tube MN 2; the source electrode of the MOS tube NM is connected with the drain electrode of the MOS tube MN 2; the source of the MOS transistor MN0 and the source of the MOS transistor MN2 are connected with a reference potential point 2112.

And the MOS tube NM is utilized to reduce the charging current, namely the MOS tube NM presses the MOS tube MN2 into a linear region, so that the Iprogram of the MOS tube MN0 mirrored by the MOS tube MN2 is reduced. When the modulating voltage Vmodulate voltage is reduced to a stable voltage, the current smaller than Iprogram mirrored through the MOS transistor MN2 is also stabilized, and thus the frequency of the system is also reduced to a stable value.

In a specific embodiment, the reference potential point 2112 includes a wiring to which a reference potential (for example, a ground potential) is supplied. The power supply 2106 voltage is greater than the reference potential voltage.

Optionally, in some embodiments, the charge-discharge module 2108 includes a first charge capacitor Cm and a MOS transistor MN1; the current mirror unit realizes mirror feedback of the modulation current Icharge through the MOS tube MN1;

the drain electrode of the MOS tube MP0 is connected with the drain electrode of the MOS tube MN1, and the source electrode of the MOS tube MP0 is connected with the reference current source 2113;

the other end of the first charging capacitor Cm and the source electrode of the MOS transistor MN1 are connected to the reference potential point 2112.

Optionally, in some embodiments, the current mirror unit includes a second current mirror 2109, a third current mirror 2110, and a fourth current mirror 2111; the minimum on-time clamp 210 further includes a fourth leg 2104, a fifth leg 2105, and an output leg 2115; the first current mirror 2107, the second current mirror 2109, the third current mirror 2110 and the fourth current mirror 2111 are cascode current mirrors;

the second current mirror 2109 mirrors the current in the third leg 2103 into the fourth leg 2104; third current mirror 2110 mirrors the current in fourth leg 2104 into fifth leg 2105, fourth current mirror 2111 mirrors the current in fifth leg 2105 to obtain modulated current Icharge, which is output through output leg 2115; the common gate of the third current mirror 2110 is connected to the gate of the MOS transistor MN1, and forms a current mirror with the MOS transistor MN1, so as to feedback the modulated current Icharge mirror image to the charge-discharge module 2108.

The second current mirror 2109 includes a MOS transistor MP1 disposed on the third branch 2103 and a MOS transistor MP2 disposed on the fourth branch 2104, the third current mirror 2110 includes a MOS transistor MN3 disposed on the fourth branch 2104 and a MOS transistor MN4 disposed on the fifth branch 2105, and the fourth current mirror 2111 includes a MOS transistor MP3 disposed on the fifth branch 2105 and a MOS transistor MP4 disposed on the output branch 2115.

Specifically, as shown in fig. 3, the source of the MOS transistor MP1 is connected to the power supply 2106, the drain of the MOS transistor MP1 is connected to the drain of the MOS transistor NM, and the gate of the MOS transistor MP1 is connected to the drain of the MOS transistor MP 1;

the grid electrode of the MOS tube MP2 is connected with the grid electrode of the MOS tube MP 1; the source electrode of the MOS tube MP2 is connected with a power supply 2106; the drain electrode of the MOS tube MN3 is connected with the grid electrode of the MOS tube MN3, the drain electrode of the MOS tube MN3 is connected with the drain electrode of the MOS tube MP2, and the grid electrode of the MOS tube MN3 is connected with the grid electrode of the MOS tube MN1; the grid electrode of the MOS tube MN4 is connected with the grid electrode of the MOS tube MN 3; the source electrode of the MOS tube MP3 is connected with the power supply 2106, the drain electrode of the MOS tube MP3 is connected with the grid electrode of the MOS tube MP3, and the drain electrode of the MOS tube MP3 is connected with the drain electrode of the MOS tube MN 4; the source electrode of the MOS tube MP4 is connected with the source electrode of the MOS tube MP3, the grid electrode of the MOS tube MP4 is connected with the grid electrode of the MOS tube MP3, and the drain electrode of the MOS tube MP4 outputs current Icharge;

the source of the MOS transistor MN0, the other end of the first charging capacitor Cm, the source of the MOS transistor MN1, the source of the MOS transistor MN2, the source of the MOS transistor MN3 and the source of the MOS transistor MN4 are connected with a reference potential point 2112 (e.g. ground GND).

The charging current Iprogram to the capacitance in the oscillator 220OSC is regulated by regulating the gate of the MOS transistor NM, i.e. the modulation voltage output point 2114, to modulate the voltage Vmodulate. Iprogram is a programmable current, which is a current set by an external circuit. The minimum on-time clamp circuit 210 is capable of implementing a current modulation function (Modulator as shown in fig. 2) that modulates the input programmable current Iprogram to an output current Icharge to charge the OSC capacitor, i.e., the second charge capacitor Ccap, in the oscillator 220.

In a specific embodiment, the programmable current Iprogram is optionally set by an external resistor.

Optionally, the reference current source 2113 is a mirrored reference current source, and the purpose of the reference current source 2113 is to control the length of time of the second on-time min_on2 set by the system.

During the period when the upper tube is on, the reference current source 2113 charges the first charge capacitor Cm, and the first charge capacitor Cm is discharged by the current of KIcharge during the whole clock period.

As shown in fig. 3, the width ratio of the MOSFET is: MN1: MN3: mn4=1: b: b, B is the ratio of the width to the length of the MOS tube, and other current mirrors are all of the same size, so that the discharge current multiple K=1/B.

The MOS transistor MP0 is used as a switch, and is turned on during the on time HSon of the high-side device 110, so as to charge the first charging capacitor Cm. The modulation voltage output point 2114 providing the modulation voltage vmodule is discharged with the MOS transistor MN1 for the entire period (including the on time HSon and the off time HSoff of the high side device 110).

The amount of change in the modulation voltage Vmodulate in one cycle is:

when Δvmodule >0, the modulation voltage vmmodule will be gradually increased, and finally the MOS transistor NM is completely turned on, which is as follows: icharge=iprogram; in this operating state, the switching frequency is the clock frequency set by the external resistor.

When the external power supply 2106VIN increases or the output voltage VOUT of the DCDC converter 100 decreases, the on-time HSon of the high-side device 110 gradually decreases to the second minimum on-time min_o2, Δvmodule=0, and the modulated voltage vmmodule stabilizes at a relatively low voltage value, and the MOS transistor MN2 is pushed linearly, which is as follows: icharge < Iprogram.

When Δvmodule=0, in combination with formula (I), it is possible to obtain:

the on-time HSon of the high-side device 110 at this time is the set second minimum on-time min_o2:

as shown by equation (IV), by setting the appropriate reference current source 2113, the desired second minimum on-time min on2 of the system can be obtained,

from equation (IV), and the charging current Icharge of the system to the oscillator 220 decreases, the clock period Tclk is lengthened, and the switching frequency of the system is reduced to a frequency at which the on-time HSon of the high-side device 110 is set to the second minimum on-time min_o2.

As shown in fig. 4, the modulated voltage vmodule has ripple in each period of charging and discharging, and meanwhile, the current gain of the output current Icharge controlled by the MOS transistor NM may be large, which may cause loop instability. Therefore, in a specific embodiment, a resistor Rm may be added to reduce loop gain, that is, the source of the MOS transistor NM is connected to the drain of the MOS transistor MN2 through the resistor Rm; the linearity from the voltage Vmodulation to the output current Icharge can be increased, namely, the voltage Vmodulation has good linearity in the whole period fluctuation range.

Some control schemes in DCDC conversion products exist, and a control method of reducing the frequency in a sectional manner (i.e. reducing the frequency in a sectional manner) can be realized by comparing the voltage proportions of the input and the output. The disadvantage of this approach is that the operating frequency of DCDC cannot be applied to its very high extent. Such as a fixed high input voltage and a lower output voltage, and the frequency is also set at a frequency that is ultra high for the current configuration of the system. The switching frequency must be reduced in order to stabilize the system since the current frequency setting is high. Due to the limitation of the minimum on-time min_on, the loop can work stably, assuming that the DCDC loop can be lowered in frequency to 500K. But the segmented down conversion is to let the system operate at 400K or 300K frequency.

Fig. 5 is a schematic structural diagram of the DCDC converter 100 according to an embodiment of the present application, as shown in fig. 3, the embodiment of the present application further provides a control module 200 of the DCDC converter 100, including:

an oscillator 220, the oscillator 220 being configured to generate a clock signal of a set frequency by charging and discharging the second charge capacitor Ccap by modulating the current Icharge;

the minimum on-time clamp circuit 210 of the above embodiment is configured to output the modulation current Icharge, so that the frequency of the clock signal generated by the oscillator 220 meets the set requirement;

and a switch control unit 230, the switch control unit 230 being configured to generate switching signals of the high-side device 110 and the low-side device 130 to control the on states of the high-side device 110 and the low-side device 130.

As shown in fig. 2, specifically, the oscillator 220 includes a current source 2113 and a second charging capacitor cca connected between the power source 2106 and the reference potential point 2112, and the current source outputs a modulated current obtained by modulating based on a programmable current; the NMOS switch tube is connected in parallel with two ends of the second charging capacitor Ccap and is used for providing a discharging path of the capacitor; and the comparator is used for comparing the voltage of the node on the connection line between the current source and the second charging capacitor Ccap with the reference voltage Vref to generate a clock signal.

The present application provides for DCDC converter 100 to automatically lower the switching frequency to maintain proper operation of the loop when it encounters a second on-time min_on 2.

The present application also provides a DCDC converter 100, comprising:

a controllable device circuit including a high-side device 110 and a low-side device 130, the high-side device 110 and the low-side device 130 being used to control the transmission of electrical energy from an input terminal to an output terminal, thereby realizing the generation of an output voltage according to an input voltage;

control circuit, control circuit includes control module 200 of DCDC converter 100 as above.

As shown in fig. 5, DCDC converter 100 includes a controllable device circuit including a high-side device 110M1 and a low-side device 130M2, high-side device 110M1 and low-side device 130M2 are connected in series between an input terminal and a ground terminal, an inductor 120Lx is connected between an intermediate node of high-side device 110M1 and low-side device 130M2 and an output terminal VOUT, and an output capacitor Cout is connected between the output terminal and the ground terminal. The DCDC converter 100 has an input terminal connected to the input voltage Vin and an output terminal providing the output voltage VOUT. The high-side device 110M1 and the low-side device 130M2 may be MOS transistors.

It will be appreciated that the control module 200 of the DCDC converter 100 shown in fig. 5 may be only a part of the control circuit of the DCDC converter 100 in peak current mode, and that other structures of the control loop, such as the Error Amplifier (EA), etc., may be included in other embodiments not shown.

As shown in fig. 5, the switch control unit 230 is configured to output switch control signals to the high-side device 110M1 and the low-side device 130M2, where the switch control signals include an on-time HSon control signal of the high-side device 110M1, an off-time HSoff control signal, an on-time LSon control signal of the low-side device 130M2, and an off-time LSoff control signal of the low-side device 130M 2.

The present application reasonably proposes a circuit that can stably operate, when the DCDC converter 100 operates at the minimum on time min_on, instead of operating under subharmonic oscillation. The core idea is that two minimum on-times min_on are set in the system, the first minimum on-time min_on1 is conventional, and the minimum on-time min_on which can be achieved and the minimum on-time of the upper tube are determined by the circuit in general. The other second minimum on-time min_on2 is set to be a time, and typically, the second minimum on-time min_on2 is 50% longer than the first minimum on-time min_on 1. When the output voltage is fixed and the VIN voltage is increased, the opening time of the upper tube is smaller and smaller, and when the opening time of the upper tube is as short as the time of opening the upper tube by only a second minimum conduction time min_on2, the system does not further reduce the conduction time of the upper tube to reduce the duty ratio of the conduction time of the upper tube, but reduces the frequency to meet the duty ratio required by the system. Because the upper tube on-time is clamped at the second minimum on-time min_on2, the peak current of each cycle is also fixed, and at this time, the output of the Error Amplifier (EA) will be stabilized at an effective output corresponding to the peak current at this time, the loop is stable, the system works in a positive field, the output voltage is stable, and the oscillation will not occur.

Because the programmable current Iprogram can be modulated by introducing the minimum on-time clamp 210, reducing the clock frequency, and at the same time being introduced into the control loop of the DCDC, it is often necessary to take the first charge capacitor Cm to a larger value, or to let the modulation voltage Vmodulate change sufficiently slowly, to meet the bandwidth of the modulation circuit being much smaller than the switching frequency, in order not to affect each other between the two loops. The DCDC converter 100 incorporates a modulation circuit frequency modulation loop that operates in conjunction with a loop controlled by an Error Amplifier (EA), the output of which controls the load current of the system, and the added frequency modulation loop controls the output voltage.

According to the method, the frequency modulation loop comprising the minimum on-time clamping circuit is added into the DCDC converter 100, so that the frequency modulation loop comprising the minimum on-time clamping circuit 210, the oscillator 220 and the switch control unit 230 is obtained, and the problem that when the traditional structure encounters a small duty ratio, the loop is opened or the working frequency of the system needs to be manually adjusted in a segmented mode, so that the accuracy of output voltage is poor can be effectively solved;

the DCDC converter 100 provided by the present application can automatically and smoothly switch between the fixed frequency and the frequency modulation mode, and does not need complicated manual control or preset operating frequency according to the input/output voltage, so that the DCDC converter can operate in a larger input/output voltage range.

The embodiment of the application also provides an electronic device 300, as shown in fig. 6, including the DCDC converter 100 as above.

It is to be understood that the above description is intended to be illustrative, and not restrictive. Many embodiments and many applications other than the examples provided will be apparent to those of skill in the art upon reading the above description. The scope of the present teachings should, therefore, be determined not with reference to the above description, but instead should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled. The disclosures of all articles and references, including patent applications and publications, are incorporated herein by reference for the purpose of completeness. The omission of any aspect of the subject matter disclosed herein in the preceding claims is not intended to forego such subject matter, nor should the applicant be deemed to have such subject matter not considered to be part of the subject matter of the disclosed application.

Claims

1. A minimum on-time clamp circuit, wherein the minimum on-time clamp circuit is applied to a DCDC converter, and the DCDC converter controls electric energy conversion through switching actions of a controllable device;

2. The minimum on-time clamp circuit of claim 1, wherein the minimum on-time clamp circuit comprises a first current mirror, a current mirror unit, a first leg, a second leg, and a third leg;

the first current mirror mirrors the programmable current input by the first branch into the third branch;

the second branch comprises a reference current source, a charging and discharging module and a MOS tube MP0 connected between the reference current source and the charging and discharging module; a modulation voltage output point is arranged between the MOS tube MP0 and the charge-discharge module;

the grid electrode of the MOS tube MP0 is connected with the inverse signal of the starting signal of the controllable device; the third branch comprises an MOS tube NM, and the grid electrode of the MOS tube NM is connected with the modulation voltage output point; the current mirror unit is connected with the third branch and the charge-discharge module, and is used for obtaining the modulation current and feeding the modulation current back to the charge-discharge module in a mirror image mode to serve as the discharge current of the modulation voltage output point.

3. The minimum on-time clamp circuit of claim 2, wherein the first current mirror comprises:

the MOS tube MN0 is arranged on the first branch, the drain electrode of the MOS tube MN0 is connected with the grid electrode of the MOS tube MN0, and the drain electrode of the MOS tube MN0 is connected with the programmable current;

4. The minimum on-time clamp circuit of claim 3, wherein the charge-discharge module comprises a first charge capacitor Cm and a MOS transistor MN1; the current mirror unit realizes modulation current mirror feedback through the MOS tube MN1;

5. The minimum on-time clamp circuit of claim 4, wherein the current mirror unit comprises a second current mirror, a third current mirror, and a fourth current mirror; the minimum on-time clamping circuit further comprises a fourth branch, a fifth branch and an output branch; the second current mirror, the third current mirror and the fourth current mirror are cascode current mirrors;

6. The minimum on-time clamp circuit of claim 5, wherein the second current mirror comprises a MOS transistor MP1 disposed in the third branch and a MOS transistor MP2 disposed in the fourth branch, the third current mirror comprises a MOS transistor MN3 disposed in the fourth branch and a MOS transistor MN4 disposed in the fifth branch, and the fourth current mirror comprises a MOS transistor MP3 disposed in the fifth branch and a MOS transistor MP4 disposed in the output branch;

the grid electrode of the MOS tube MP2 is connected with the grid electrode of the MOS tube MP 1; the source electrode of the MOS tube MP2 is connected with the power supply; the drain electrode of the MOS tube MP2 is connected with the drain electrode of the MOS tube MN 3;

7. The minimum on-time clamp circuit of claim 6, wherein a width ratio of the MOS transistor MN1, the MOS transistor MN3, and the MOS transistor MN4 is 1: b: and B, wherein B is the ratio of the width to the length of the MOS tube.

8. The minimum on-time clamp circuit of claim 2, wherein the set threshold is set by setting the reference current source.

A control module for a dcdc converter, comprising:

a minimum on-time clamp circuit as claimed in any one of claims 1 to 8; the minimum conduction time clamping circuit is used for outputting the modulation current so that the frequency of a clock signal generated by the oscillator meets the set requirement;

10. A DCDC converter, comprising:

the controllable device circuit comprises a high-side device and a low-side device, and the high-side device and the low-side device are adopted to control electric energy to be transmitted from an input end to an output end;

and a control circuit comprising a control module of the DCDC converter of claim 9 for generating a switching signal to control the on-state of the high-side device and the low-side device.

11. An electronic device comprising the DCDC converter of claim 10.