CN116434811A

CN116434811A - Test access circuit, method, chip and readable storage medium

Info

Publication number: CN116434811A
Application number: CN202310369389.6A
Authority: CN
Inventors: 茹敏强
Original assignee: Beijing Eswin Computing Technology Co Ltd; Guangzhou Quanshengwei Information Technology Co Ltd
Current assignee: Beijing Eswin Computing Technology Co Ltd; Guangzhou Quanshengwei Information Technology Co Ltd
Priority date: 2023-04-07
Filing date: 2023-04-07
Publication date: 2023-07-14

Abstract

The application discloses test access circuit belongs to integrated circuit technical field, the circuit includes: the device comprises a main port module and N cascaded test access modules, wherein the N test access modules are connected with the main port module, N is a positive integer, and the test access modules comprise test access ports; the main port module is used for receiving a configuration signal sent by the test register, configuring the N test access modules according to the configuration signal, and determining a target test access module corresponding to the register to be tested from the N test access modules according to a configuration result; the target test access module is used for receiving the test data sent by the test register, sending the test data to the register to be tested through a test access port in the target test access module, and sending a test result of the register to be tested to the test register. The test hardware cost can be reduced.

Description

Test access circuit, method, chip and readable storage medium

Technical Field

The application belongs to the technical field of integrated circuits, and particularly relates to a test access circuit, a test access method, a test access chip and a readable storage medium.

Background

The joint Test workgroup (Joint Test Action Group, JTAG) tests the chip by setting a Test Access Port (TAP) inside the chip and accessing the Test register of the chip by the Test register of the JTAG through the TAP.

In the prior art, when the number of test registers and test access ports in a test access circuit in a chip increases, the number of test registers and test access ports corresponding to the number of test registers increases, resulting in an increase in the cost of test hardware of the chip.

Disclosure of Invention

An object of the embodiments of the present application is to provide a test access circuit, a method, a chip, and a readable storage medium, which can solve the problem that the test hardware cost increases with the number of registers to be tested.

In a first aspect, embodiments of the present application provide a test access circuit, the circuit comprising: the device comprises a main port module and N cascaded test access modules, wherein the N test access modules are connected with the main port module, N is a positive integer, and the test access modules comprise test access ports;

the main port module is used for receiving a configuration signal sent by the test register, configuring the N test access modules according to the configuration signal, and determining a target test access module corresponding to the register to be tested from the N test access modules according to a configuration result;

The target test access module is used for receiving the test data sent by the test register, sending the test data to the register to be tested through a test access port in the target test access module, and sending a test result of the register to be tested to the test register.

Optionally, the main port module includes a first input interface and a first output interface, where the first input interface is connected with a test output interface of the test register; the test access module comprises a second input interface and a second output interface; the N test access modules comprise a multi-level test access module;

the second input interface of a first stage test access module in the multi-stage test access module is connected with the first output interface, the second input interface of an Mth stage test access module is connected with the second output interface of an Mth-1 stage test access module, the second input interface of an Nth stage test access module is connected with the second output interface of an Nth-1 stage test access module, the second output interface of the Nth stage test access module is connected with the test input interface of the test register, and M is an integer more than 1 and less than N;

The main port module is further configured to receive, through the first input interface, the configuration signal sent by the test register through the test output interface.

Optionally, the main port module further includes a first bypass, and the first bypass is connected with the test output interface, the first output interface and the second input interface of the first stage test access module;

the first bypass device is used for receiving a first bypass signal and conducting connection between the test output interface and the second input interface according to the first bypass signal.

Optionally, the test access module further includes a second bypass;

the second bypass device of the first-stage test access module is connected with the first output interface of the main port module, the second output interface of the first-stage test access module and the second input interface of the second-stage test access module, and is used for conducting connection between the first output interface and the second input interface of the second-stage test access module according to a second bypass signal sent by the main port module;

the second bypass device of the M-th level test access module is connected with the second output interface of the M-1-th level test access module, the second input interface of the M-th level test access module and the second input interface of the M+1th level test access module, and is used for conducting connection between the second output interface of the M-1-th level test access module and the second input interface of the M+1th level test access module according to the second bypass signal sent by the main port module;

The second bypass of the N-level test access module is connected with the second output interface of the N-1-level test access module, the second input interface of the N-level test access module and the test input interface of the test register, and is used for conducting connection between the second output interface of the N-1-level test access module and the test input interface according to the second bypass signal sent by the main port module.

Optionally, the test access module further includes a first bus interface;

when the test access module is used as a target test access module, the target test access module is used for connecting the first bus interface with the second bus interface of the register to be tested, sending the test data to the register to be tested through the first bus interface, and receiving a test result of the register to be tested through the first bus interface;

the test data are used for testing the register to be tested and controlling the register to be tested to send the test result to the test access module through the second bus interface.

Optionally, the test access module further includes a data conversion sub-module, an interface address sub-module, and a bypass sub-module; the bypass submodule is connected with the first bus interface;

The data conversion sub-module is used for receiving the operation address sent by the test register through the second input interface, carrying out serial-parallel conversion on the operation address and sending the converted operation address to the interface address sub-module under the condition that the test access module is taken as a target test access module;

the interface address sub-module is used for carrying out bus protocol matching on the converted operation address according to the bus protocol corresponding to the second bus interface, and sending the matched operation address to the bypass sub-module;

the bypass submodule is used for connecting with a second bus interface of the register to be tested through the first bus interface according to the matched operation address; the operation address is the address corresponding to the register to be tested.

Optionally, the data conversion sub-module is further configured to receive the test data through the second input interface, perform serial-parallel conversion on the test data, and send the converted test data to the interface address sub-module;

the interface address sub-module is further configured to perform bus protocol matching on the converted test data according to a bus protocol corresponding to the second bus interface, and send the matched test data to the bypass sub-module;

The bypass sub-module is further configured to send the matched test data to the register to be tested through the first bus interface.

Optionally, the bypass submodule is further configured to, when the bus signal received by the first bus interface indicates that the register to be tested sends the test result, conduct connection between the first bus interface and the interface address submodule;

the interface address sub-module is further configured to receive the test result sent by the first bus interface, and send the test result to the data conversion sub-module;

the data conversion sub-module is also used for carrying out parallel-serial conversion on the test result and sending the converted test result to a test access port in the target test access module;

and the test access port in the target test access module is used for outputting the test result through the second output interface.

Optionally, the test access module further includes an interface control sub-module, and the interface control sub-module is connected with the test access port;

the interface control sub-module is used for receiving a first control signal sent by a test access port in the target test access module, converting the first control signal into a second control signal corresponding to the second bus interface, and sending the second control signal to the bypass sub-module;

The bypass sub-module is further configured to send the second control signal to the register to be tested through the first bus interface; the second control signal is used for controlling the register to be tested to receive the test data and sending the test result to the first bus interface.

In a second aspect, an embodiment of the present application provides a test access method, applied to the test access circuit in the first aspect, where the circuit includes: the device comprises a main port module and N cascaded test access modules, wherein the N test access modules are connected with the main port module, N is a positive integer, the test access modules comprise test access ports, and the method comprises the following steps:

receiving a configuration signal sent by a test register through the main port module, configuring the N test access modules according to the configuration signal, and determining a target test access module corresponding to a register to be tested of a chip from the plurality of test access modules according to a configuration result;

and receiving test data sent by the test register through the target test access module, sending the test data to the register to be tested through a test access port in the target test access module, and sending a test result of the register to be tested to the test register.

the second input interface of a first stage test access module in the multi-stage test access module is connected with the first output interface, the second input interface of an Mth stage test access module is connected with the second output interface of an Mth-1 stage test access module, the second input interface of an Nth stage test access module is connected with the second output interface of an Nth-1 stage test access module, the second output interface of the Nth stage test access module is connected with the test input interface of the test register, and M is an integer more than 1 and less than N; the method further comprises the steps of:

and receiving the configuration signal sent by the test register through the test output interface through the first input interface by the main port module.

Optionally, the main port module further includes a first bypass, and the first bypass is connected with the test output interface, the first output interface and the second input interface of the first stage test access module; the method further comprises the steps of:

And receiving a first bypass signal through the first bypass device, and conducting connection between the test output interface and the second input interface according to the first bypass signal.

Optionally, the test access module further includes a second bypass;

the second bypass of the first-stage test access module is connected with the first output interface of the main port module, the second output interface of the first-stage test access module and the second input interface of the second-stage test access module;

the second bypass of the M-th level test access module is connected with the second output interface of the M-1-th level test access module, the second input interface of the M-th level test access module and the second input interface of the M+1-th level test access module;

the second bypass of the Nth-level test access module is connected with the second output interface of the N-1 th-level test access module, the second input interface of the Nth-level test access module and the test input interface of the test register; the method further comprises the steps of:

the connection between the first output interface and the second input interface of the second stage test access module is conducted through a second bypass device of the first stage test access module according to a second bypass signal sent by the main port module;

The second bypass device of the M-th level test access module is used for conducting connection between a second output interface of the M-1-th level test access module and a second input interface of the M+1-th level test access module according to a second bypass signal sent by the main port module;

and the second bypass device of the Nth-1-stage test access module is used for conducting connection between a second output interface of the Nth-1-stage test access module and the test input interface according to a second bypass signal sent by the main port module.

Optionally, the test access module further includes a first bus interface; in the case where the test access module is regarded as a target test access module, the method further includes:

connecting a first bus interface of the target test access module with a second bus interface of the register to be tested through the test access module, sending the test data to the register to be tested through the first bus interface, and receiving a test result of the register to be tested through the first bus interface; the test data are used for testing the register to be tested and controlling the register to be tested to send the test result to the test access module through the second bus interface.

Optionally, the test access module further includes a data conversion sub-module, an interface address sub-module, and a bypass sub-module; the bypass submodule is connected with the first bus interface; in the case that the test access module is used as a target test access module, the connecting, by the test access module, the first bus interface of the target test access module with the second bus interface of the register under test includes:

receiving an operation address sent by the test register through the second input interface by the data conversion sub-module, carrying out serial-parallel conversion on the operation address, and sending the converted operation address to the interface address sub-module;

the interface address sub-module performs bus protocol matching on the converted operation address according to the bus protocol corresponding to the second bus interface, and sends the matched operation address to the bypass sub-module;

the bypass sub-module is connected with a second bus interface of the register to be tested through the first bus interface according to the matched operation address; the operation address is the address corresponding to the register to be tested.

Optionally, the sending, through the first bus interface, the test data to the register under test includes:

receiving the test data through the second input interface by the data conversion sub-module, performing serial-parallel conversion on the test data, and sending the converted test data to the interface address sub-module;

the interface address sub-module is used for carrying out bus protocol matching on the converted test data according to the bus protocol corresponding to the second bus interface, and the matched test data is sent to the bypass sub-module;

and sending the matched test data to the register to be tested through the first bus interface by the bypass submodule.

Optionally, the receiving, by the first bus interface, a test result of the register under test includes:

under the condition that bus signals received by the first bus interface represent the register to be tested to send the test result, the bypass submodule is used for conducting connection between the first bus interface and the interface address submodule;

receiving the test result sent by the first bus interface through the interface address submodule, and sending the test result to the data conversion submodule;

The data conversion sub-module is used for carrying out parallel-serial conversion on the test result and sending the converted test result to a test access port in the target test access module;

and outputting the test result through the second output interface through a test access port in the target test access module.

Optionally, the test access module further includes an interface control sub-module, and the interface control sub-module is connected with the test access port; the method further comprises the steps of:

receiving a first control signal sent by a test access port in the target test access module through the interface control sub-module, converting the first control signal into a second control signal corresponding to the second bus interface, and sending the second control signal to the bypass sub-module;

sending the second control signal to the register to be tested through the first bus interface by-pass submodule; the second control signal is used for controlling the register to be tested to receive the test data and sending the test result to the first bus interface.

In a third aspect, an embodiment of the present application provides a chip, including the test access circuit according to the first aspect, for performing the test access method according to the second aspect.

In a fourth aspect, embodiments of the present application provide a readable storage medium having stored thereon a program or instructions which, when executed by a processor, implement the steps of the test access method as described in the second aspect.

In a fifth aspect, an embodiment of the present application provides an electronic device, including a test access circuit according to the first aspect, for performing the test access method according to the second aspect.

In a sixth aspect, embodiments of the present application provide a computer program product stored in a storage medium, the program product being executable by at least one processor to implement the test access method as described in the second aspect.

The test access circuit of the embodiment of the application comprises: the device comprises a main port module and N cascaded test access modules, wherein the N test access modules are connected with the main port module, N is a positive integer, and the test access modules comprise test access ports; the main port module is used for receiving a configuration signal sent by the test register, configuring the N test access modules according to the configuration signal, and determining a target test access module corresponding to the register to be tested from the N test access modules according to a configuration result; the target test access module is used for receiving the test data sent by the test register, sending the test data to the register to be tested through a test access port in the target test access module, and sending a test result of the register to be tested to the test register. In this way, compared with the mode that the test register and the test access port are increased along with the increase of the register to be tested in the prior art, for the newly increased register to be tested, each test access module can be configured through the main port module, the currently available test access module is multiplexed from the cascaded N test access modules according to the configuration result, the currently available test access module is used as the target test access module of the register to be tested, test data are sent to the register to be tested through the test access port in the target test access module, the test result of the register to be tested is obtained, and the test result is sent to the test register, so that the access and the test of the register to be tested are realized, the test access port corresponding to the register to be tested does not need to be increased, and the number of the test registers connected with the main port module does not need to be increased no matter how the number of the registers to be tested is changed, therefore, the hardware overhead of the test registers and the test access ports to be tested is avoided, and the hardware cost of the test access ports to be tested is reduced to a certain extent.

Drawings

FIG. 1 is a schematic diagram of a test access circuit according to an embodiment of the present application;

FIG. 2 is a schematic diagram of another test access circuit according to an embodiment of the present application;

FIG. 3 is a schematic diagram of the structure of a jtag2apb provided in an embodiment of the present application;

FIG. 4 is a flow chart of steps of a test access method provided by an embodiment of the present application;

fig. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present application;

fig. 6 is a schematic structural diagram of another electronic device according to an embodiment of the present application;

fig. 7 is a schematic structural diagram of still another electronic device according to an embodiment of the present application.

Detailed Description

Technical solutions in the embodiments of the present application will be clearly described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application are within the scope of the protection of the present application.

The terms first, second and the like in the description and in the claims, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate, such that embodiments of the present application may be implemented in sequences other than those illustrated or described herein, and that the objects identified by "first," "second," etc. are generally of a type and not limited to the number of objects, e.g., the first object may be one or at least two. Furthermore, in the description and claims, "and/or" means at least one of the connected objects, and the character "/", generally means that the associated object is an "or" relationship.

It should be noted that JTAG is an international standard test protocol, and is mainly used for testing the inside of the chip. JTAG may be compatible with the IEEE 1149.1 standard protocol, and a standard JTAG interface may define the following signal pins: TMS test mode select signal, TCK test clock signal, TDI test data input signal, TDO test data output signal, TRST internal TAP controller reset signal, etc.

The basic principle of JTAG is to define a TAP inside the chip, and test the inside of the chip by a special JTAG test tool. Registers to be tested inside the chip can be accessed through the TAP. The control of the TAP can be accomplished by a TAP controller, which can be a 16-bit state machine, which can implement data and instruction inputs by responding to TMS and TCK signals in JTAG interface signals to change states.

The test circuit provided by the embodiment of the application is described in detail below by means of specific embodiments and application scenes thereof with reference to the accompanying drawings.

Fig. 1 is a schematic structural diagram of a test access circuit according to an embodiment of the present application, and as shown in fig. 1, the test access circuit 10 includes: the device comprises a main port module 101 and N cascaded test access modules, wherein the N test access modules are connected with the main port module 101, N is a positive integer, and the test access module 102 comprises a test access port 1021;

The main port module 101 is configured to receive a configuration signal sent by a test register, configure the N test access modules according to the configuration signal, and determine a target test access module corresponding to the register to be tested from the N test access modules according to a configuration result;

the target test access module is configured to receive test data sent by the test register, send the test data to the register to be tested through a test access port 1021 in the target test access module, and send a test result of the register to be tested to the test register.

In this embodiment, the Main port module 101 may include a test access port, as a Main test access port (Main TAP) of the test access circuit 10, the Main port module 101 may include a test data register (Test Data Registers, TDR), and the Main port module 101 may send an enable signal and a bypass signal to the test access module 102 connected to the Main port module 101 through the TDR, and control the enabling and bypass of the test access module 102 through the enable signal and the bypass signal.

Alternatively, the main port module 101 may comply with the standard IEEE1149.1 protocol, including the following signal pins: TMS test mode select signal, TCK test clock signal, TDI test data input, TDO test data output, TRST internal TAP controller reset signal. This is by way of example only, and the embodiments of the present application are not limited thereto.

In this embodiment of the present application, N test access modules may be cascaded in a manner of being connected to each other by an input interface and an output interface, that is, the output interface of the test access module of the previous stage is connected to the input interface of the test access module of the next stage.

In this embodiment of the present application, N test access modules and the main port module 101 may be connected in a daisy-chain structure, specifically, an input interface of a first stage test access module of the N cascaded test access modules may be connected to an output interface of the main port module 101, and an input interface of a second stage test access module starts a subsequent stage test access module to be connected to an output interface of a previous stage test access module, so as to implement a daisy-chain structure in which the main port module 101 and the N cascaded test access modules are connected end to end with each other.

In an embodiment of the present application, the test access module 102 may include the following signal pins: TMS test mode select signal, TCK test clock signal, TDITRST internal TAP controller reset signal test data input signal, TDO test data output signal, and are respectively connected to signal pins corresponding to the main port module 101, and can share TMS, TCK, TRST signals with the main port module 101. Among the N cascaded test access modules, the output interface TDO of the test access module of the previous stage may be connected to the input interface TDI of the test access module of the next stage, and the input interface TDI of the test access module of the first stage may be connected to the output interface TDO of the main port module 101. This is by way of example only, and the embodiments of the present application are not limited thereto.

In an embodiment of the present application, the test access module 102 may include a test access port 1021 (TAP), and the test access port 1021 may include the following signal pins: TMS test mode select signal, TCK test clock signal, TDI test data input signal, TDO test data output signal, TRST internal TAP controller reset signal, and are respectively connected to signal pins corresponding to test access module 102, and can share TMS, TCK, TRST signals with main port module 101.

In this embodiment, the test Register may include an instruction Register (Instruclion Register, IR) and a Data Register (DR), where the instruction Register is used to store an instruction related to a test, and the instruction Register receives the instruction through TDI, generates a control signal through instruction decoding, and performs a test operation through the control signal or accesses the Data Register. The data registers may include Bypass Registers (BR) and Boundary-Scan registers (Boundary-Scan registers), device indication registers, and the like. The bypass register can send out bypass signals, and the bypass signals control the bypass of the device, and the boundary scan register is used for testing the connection of external pins of the chip or collecting data inside the chip, and the boundary scan register is a large serial shift register taking TDI as input and TDO as output.

In the embodiment of the application, the configuration signal may include an enable signal and a bypass signal sent by the test register. The main port module 101 receives the first enable signal and the first bypass signal sent by the test register, and may send a second enable signal to a currently available test access module 102 of the N test access modules according to the first enable signal, so as to control the enable or start working state of the test access module 102 through the second enable signal, and send a second bypass signal to a test access module 102 that does not need to be enabled of the N test access modules, so as to control the test access module 102 that does not need to be enabled to be bypassed through the second bypass signal, namely to disconnect from the test access circuit 10, thereby configuring the N test access modules, where the configuration result is the enable or bypass result of the N test access modules.

In this embodiment of the present application, the enabled test access module 103 currently available in the N test access modules may be determined as the target test access module corresponding to the register to be tested of the chip according to the configuration result. Specifically, when the main port module 101 performs configuration, the available test access module 102 closest to the register to be tested in the N test access modules may be configured to be in an enabled state, or the available test access module 102 with the shortest access path to the register to be tested in the N test access modules may be configured to be in an enabled state, which is only illustrated herein, and the embodiment of the present application does not limit the present application.

In the embodiment of the application, the register to be tested may be a register inside a central processing unit (Central Processing Unit, CPU) or inside a peripheral device of the chip. It will be appreciated that the chip interior may be divided into a CPU and peripherals, which are connected by a bus. Specifically, the register to be tested may be a general register, a flag register, etc. in the CPU, or a register in the peripheral devices such as a timer component, an analog-to-digital conversion component, etc. around the chip core. This is by way of example only, and the embodiments of the present application are not limited thereto.

In this embodiment, the test data may be an operand sent by the test register to the register to be tested, where the operand specifies an amount of digital operation performed by the register to be tested. The target test access module receives the operand sent by the test register, accesses the register to be tested through the test access port 1021 in the target test access module, and sends the operand to the register to be tested. Specifically, the target test access module may receive an operation address sent by the test register, where the operation address may be a memory address of the register to be tested, and the test access port 1021 in the target test access module may send an operand to the register to be tested according to the operation address through a bus interface mounted on the target test access module and a bus connected to the register to be tested. The bus to which the register to be tested is connected may be an advanced peripheral interface bus (Advanced Peripheral Bus, APB), an advanced high-performance bus (Advanced High Performance Bus, AHB), etc., and the bus interface on which the target test access module is mounted may be an APB bus or a bus interface corresponding to the AHB bus, which is only illustrated herein, and the embodiment of the present application does not limit the present application.

In this embodiment of the present application, the test result may be a result obtained by performing digital operation on a register value stored in the register to be tested according to an operand received by the register to be tested and sent by the target test access module through the test access port 1021 in the target test access module, and the result is used as a test result and returned to the target test access module. The target test access module receives a test result returned by the register to be tested, and can send the test result of the register to be tested to the test register through the TDO of the target test access module so that the test result can be designated by the test register, for example, the test result is sent to a JTAG test tool and the like. This is by way of example only, and the embodiments of the present application are not limited thereto.

Compared with the prior art, the test access circuit of the embodiment of the application is characterized in that the test access circuit can configure each test access module through the main port module for the newly added test access module in a mode that the test register and the test access port are added when the test register is added, the currently available test access modules are multiplexed from the cascaded N test access modules according to the configuration result, the test access modules serve as target test access modules of the test registers, test data are sent to the test registers through the test access ports in the target test access modules, test results of the test registers are obtained, and the test results are sent to the test registers, so that access and test of the test registers are realized, the number of the test access ports corresponding to the test registers does not need to be increased, no matter how the number of the test registers changes, the number of the test registers connected with the main port module does not need to be increased, therefore, the hardware overhead of the test registers and the test access ports along with the number of the test registers can be reduced, and the hardware cost of the test access ports can be reduced to a certain extent.

In this embodiment of the present application, the first Input interface may be a Test Data Input interface (TDI), the first output interface may be a Test Data output interface (TDO), the Test output interface of the Test register may be TDO, the second Input interface may be TDI, and the second output interface may be TDO. The TDI of the main port module may be connected with the TDO of the test register.

In this embodiment of the present application, N test access modules may be cascaded through a manner of connecting TDI and TDO with each other, that is, TDO of a test access module of a previous stage is connected to TDI of a test access module of a subsequent stage, so that N test access modules form a multi-stage test access module.

In the embodiment of the application, the TDI of the first-stage test access module is connected with the TDO of the main port module, the TDI of the M-stage test access module is connected with the TDO of the M-1-stage test access module, the TDI of the N-stage test access module is connected with the TDO of the N-1-stage test access module, the TDO of the N-stage test access module is connected with the TDO of the test register, and the main port module and the N test access modules form a daisy chain structure.

In this embodiment of the present application, the TDI of the main port module is connected to the TDO of the test register, and the test register may send the configuration signal through the TDO, and the main port module may receive the configuration signal sent by the test register through its TDI. The main port module can be connected to any one stage of test access module in the N test access modules through the TDO according to the configuration signal and configured.

According to the method and the device, the main port module can receive the configuration signals sent by the test registers through the test output interfaces through the first output interfaces, and because the multi-stage test access modules are connected with each other, the main port module can be connected to the second input interface of any stage of test access module in the N test access modules through the first output interfaces, so that the connected test access modules are configured according to the configuration signals.

In this embodiment of the present application, the first bypass may be a two-out multiplexer, and may include two input interfaces and an output interface, where the two input interfaces are connected to the test output interface and the first output interface respectively, and the one output interface may be connected to the second input interface of the first stage test access module.

In this embodiment of the present invention, the first bypass signal may be a control signal sent by the test register to the first bypass device through the test output interface when the configuration of the test access module by the main port module is completed, and is used for controlling the first bypass device to bypass the main port module, that is, to conduct the connection between the test output port and the second input interface of the first stage test access module, and disconnect the connection between the first output interface and the second input interface of the first stage test access module. The main port module can be bypassed from the test access circuit, so that the first-stage test access module is directly connected to the test output interface of the test register, the transmission path of test data sent by the test register can be shortened, the data transmission speed is improved, and the test efficiency is improved to a certain extent.

For example, the first bypass signal may be byp_mtap=1, the first bypass is a one-out-of-two multiplexer, the signal of byp_mtap=1 is received, the connection between the first output port and the second input interface of the first stage test access module is selected to be conducted, the connection between the first output interface and the second input interface of the first stage test access module is disconnected, and the first stage test access module in the daisy-chain structure is directly connected to the test output interface of the test register.

The first bypass device can conduct connection of the test output interface and the second input interface according to the first bypass signal, so that the main port module is bypassed, the second output interface of the first-stage test access module is directly connected to the test output interface of the test register, the transmission path of test data is shortened, the data transmission speed is improved, and the test efficiency is improved to a certain extent.

Optionally, the test access module further includes a second bypass;

the second bypass device of the N-th stage test access module is connected with the second output interface of the N-1-th stage test access module, the second input interface of the N-th stage test access module and the test input interface of the test register, and is used for conducting connection between the second output interface of the N-1-th stage test access module and the test input interface according to the second bypass signal sent by the main port module.

In this embodiment of the present application, the second bypass device may be a two-out multiplexer, and may include two input interfaces and one output interface. The two input interfaces of the second bypass of the first-stage test access module are respectively connected with the first output interface of the main port module and the second output interface of the first-stage test access module, and one output interface can be connected with the second input interface of the second-stage test access module. Two input interfaces of the second bypass of the M-stage test access module are respectively connected with a second output interface of the M-1 stage test access module and a second input interface of the M-stage test access module, and one output interface can be connected with a second input interface of the M+1 stage test access module. Two input interfaces of the second bypass of the N-level test access module are respectively connected with a second output interface of the N-1 level test access module and a second input interface of the N-level test access module, and one output interface can be connected with a test input interface of the test register.

In this embodiment of the present invention, the second bypass signal may be generated by the main port module according to the configuration signal sent by the test register, and is sent to a control signal of the second bypass device, so as to control the second bypass device to bypass the current test access module, so that the current test access module is bypassed from the test access circuit, and thus, the second input interface of the next stage test access module is directly connected to the second output interface of the previous stage test access module, which can shorten the transmission path of the test data sent by the test register, improve the data transmission speed, and improve the test efficiency to a certain extent. For example, the second bypass signal may be byp_j2a=1, and the second bypass device is a one-out-of-two multiplexer, and selects to bypass the current test access module when receiving the byp_j2a=1 signal.

The second bypass device can bypass the test access module according to the second bypass signal, so that the target test access module is connected to the test register through the shortest path, the transmission path of test data is shortened, the data transmission speed is improved, and the test efficiency is improved to a certain extent.

Optionally, the test access module further includes a first bus interface;

In this embodiment of the present application, the test access circuit and the register to be tested may be connected through a bus, such as an APB bus or an AHB bus. The first bus interface and the second bus interface may be bus interfaces corresponding to buses connected between the test access circuit and the register to be tested, such as an APB bus interface or an AHB bus interface. This is by way of example only, and the embodiments of the present application are not limited thereto.

In this embodiment, when the test access module is used as the target test access module, the target test access module may access the second bus interface through the first bus interface according to the operation address corresponding to the register to be tested sent by the test register, that is, connect the first bus interface with the second bus interface of the register to be tested. The test access module can send test data to the register to be tested through the first bus interface according to the operation address corresponding to the register to be tested, and receive a test result sent to the test access module by the register to be tested through the second bus interface through the first bus interface.

In this embodiment of the present application, the test data may be an operand sent by a test register, where the register to be tested receives an operand sent by the target test access module through the first bus interface, performs digital operation on a register value stored in the register to be tested according to the operand to obtain a test result, and sends the test result to the target test access module through the second bus interface.

In the embodiment of the application, under the condition that the test access module is used as the target test access module, the first bus interface of the target test access module is connected with the second bus interface of the corresponding register to be tested, so that the target test access module can access the register to be tested through the first bus interface and the second bus interface and transmit test data and test results, and the practicability of the test access circuit is improved.

Optionally, the main port module includes a first instruction register and a first state machine, and the test access port includes a second instruction register and a second state machine;

the main port module is further configured to adjust, according to the configuration signal, a second instruction register of the test access ports of the P test access modules to be consistent with the register length of the first instruction register, so as to adjust the first state machine and the second state machines of the test access ports of the P test access modules to be in a synchronous state, where P is an integer less than or equal to N.

In this embodiment, the register length of the first instruction register is matched with the number of states included in the first state machine, and the register length of the second instruction register is matched with the number of states included in the second state machine. The first instruction register and the second instruction register may be serial shift registers, one shift action of the first instruction register corresponding to one state change of the first state machine, one shift action of the second instruction register corresponding to one state change of the second state machine.

For example, the first instruction register has a register length of 16 bits, the first state machine includes 16 states, the first state machine in JTAG is the TAP controller of the main port module, and the second state machine is the TAP controller of the test access port of the test access module. The TAP controller comprises 16 states, the states of the TAP controller are controlled by TMS, TCK and TRST signals, the states change when the TCK signal rises, and the next state is determined by the TMS signal and the state machine where the TAP controller is currently located. The TMS, TCK, and TRST signals enter the TAP controller, generating different control signals based on different states. These control signals include dedicated control signals to the instruction register IR: capture IR, shift IR, update IR, including dedicated control signals to the data register DR: capture DR, shift DR, update DR. The states of the TAP controller may be referred to related descriptions in the prior art, and will not be described herein.

In this embodiment of the present application, the main port module may send, according to a configuration signal, a control signal to second instruction registers of test access ports of P available test access modules in the N test access modules, so as to control lengths of the second instruction registers of the test access ports of the P test access modules to be consistent with lengths of the first instruction registers. The P test access modules are test access modules indicated by the configuration signals, and the value of P is consistent with the number of registers to be tested corresponding to the test. After the lengths of the second instruction register and the first instruction register of the test access ports of the P test access modules are adjusted to be consistent, TRST, TCK and TMS signals shared by the P test access modules and the main port module can be synchronized, so that the state time of the second state machine and the state of the first state machine are synchronized and each changed state is synchronized, the first state machine and the second state machine of the P test access modules are adjusted to be in a synchronous state, and thus, the main port module can configure the P test access modules simultaneously under the same state of the first state machine and the second state machine, and the configuration efficiency of the main port module is improved.

In this embodiment of the present application, after the register lengths of the second instruction registers of the P test access modules and the first instruction registers are adjusted to be consistent, the register lengths of the corresponding second instruction registers of the P test access modules are also consistent, so that the second state machines of the P test access modules are also in a synchronous state. After the configuration of the P test access modules by the main port module is completed, the P test access modules are used as target test access modules, the test registers can bypass the main port module through the first bypass device, so that the target test access modules are independent of the main port module, and the target test access modules are directly read and written at the same time, namely, the test data and the test results are transmitted through the target test access modules, and the registers to be tested are accessed and tested, so that the data transmission efficiency of the test access circuit is improved.

In another possible implementation, when the register length of the first instruction register is inconsistent with the register length of the second instruction register of a certain test access module, the first state machine is not synchronous with the second state machine of the test access module, the main port module can be bypassed through the first bypass device, and the test access module is directly accessed by the test register to configure the test access module.

In this embodiment of the present application, the bus to which the register to be tested is connected may be a parallel bus, and the test register may send the operation address and the operation instruction to the test access module in a serial manner, where the data conversion submodule is connected to the second input interface and the interface address submodule respectively. The data conversion sub-module can receive the operation address and the operation instruction in series through the second input interface, convert the serial operation address and the operation instruction into the parallel operation address and the operation instruction, namely perform serial-parallel conversion, and then send the converted operation address and operation instruction to the interface address sub-module. The operation instructions may include a write instruction and a read instruction, among others. It should be noted that, the serial-parallel conversion method may refer to the prior art, and the embodiment of the present application does not limit this.

In this embodiment of the present application, the interface address submodule may be connected with the data conversion submodule and the bypass submodule respectively, and may match the converted operation address and operation instruction with the current bus transmission timing according to the bus protocol corresponding to the second bus interface, and send the matched operation address and operation instruction to the bypass submodule when the bus connected between the first bus interface and the second bus interface is in the write state.

In this embodiment of the present application, the bypass sub-module may send, according to an operation address, that is, an address corresponding to the register to be tested, the matched operation address and the operation instruction to the second bus interface of the register to be tested through the first bus interface, so as to connect with the second bus interface of the register to be tested through the first bus interface. The operation instruction may include a write instruction or a read instruction, where the write instruction is used to instruct the register to be tested to receive the test data and perform digital operation on the register value corresponding to the operation address to obtain a test result, and the read instruction is used to instruct the register to be tested to return the test result corresponding to the operation address.

In the embodiment of the application, serial-parallel conversion can be conveniently performed through the data conversion sub-module, so that the serial operation address sent by the test register is converted into the parallel operation address corresponding to the second bus interface, bus protocol matching can be performed on the parallel operation address through the interface address sub-module, the side sub-module can be connected to the second bus interface of the register to be tested according to the matched operation address, test data and test results are transmitted through the first bus interface and the second bus interface, and the practicability of the test access circuit is improved.

In this embodiment of the present application, after the test access module sends the operation address and the write identifier to the register to be tested, the register to be tested is ready to receive the test data, and the data conversion sub-module may receive the test data sent by the test register through the second input interface, and perform serial-parallel conversion on the test data, and send the converted test data to the interface address sub-module. The interface address sub-module can match the converted test data with the current bus transmission time sequence according to the bus protocol corresponding to the second bus interface, and sends the matched test data to the side sub-module when the bus connected between the first bus interface and the second bus interface is in a writing state. The side sub-module can send the matched test data to the register to be tested through the first bus interface, and the register to be tested can receive the test data through the second bus interface. The test data may be an operand, and the register to be tested may perform digital operation on a register value corresponding to the operation address according to the operand to obtain a test result.

In the embodiment of the application, serial-parallel conversion is performed on the test data sent by the test register in series through the data conversion sub-module, so that the serial test data sent by the test register is converted into parallel test data corresponding to the second bus interface, bus protocol matching is performed on the parallel test data through the interface address sub-module, and further, the bypass sub-module sends the matched test data to the register to be tested through the first bus interface, so that the second bus interface can receive the matched test data, and therefore transmission of the test data between the test access module and the register to be tested is achieved, and the practicability of the test access circuit is improved.

Optionally, the bypass submodule is further configured to conduct connection between the first bus interface and the interface address submodule when the bus signal received by the first bus interface characterizes that the test register sends the test result;

In this embodiment of the present application, the bypass submodule may be further connected to a functional signal interface of the first bus interface, for example, a clock, reset, enable, and other functional signal interfaces. And when the test access module is used as the target test access module, the bypass sub-module is used for receiving the functional signals sent by the second bus interface to the first bus interface, and when the test result is read, the bypass sub-module can bypass the functional signal interface of the first bus interface and directly connect the read data interface of the first bus interface with the interface address sub-module.

In this embodiment of the present application, when the test access module is used as the target test access module, after the target test access module sends the operation address and the read identifier to the register to be tested, the register to be tested prepares to send the test result to the target test access module, and sends the read-write control signal, i.e., the bus signal, to the first bus interface through the second bus interface, where the read-write control signal indicates that the bus connected between the first bus interface and the second bus interface is in a read state, i.e., the bus signal received by the first bus interface indicates that the test register sends the test result.

In the embodiment of the application, the bypass sub-module bypasses the functional signal interface of the first bus interface and directly conducts the connection between the read data interface of the first bus interface and the interface address sub-module under the condition that the bus signal received by the first bus interface represents the test result sent by the register to be tested. The interface address sub-module receives a test result sent by the register to be tested through the second bus interface through the data reading interface of the first bus interface, and sends the test result to the data conversion sub-module.

In the embodiment of the application, the data conversion sub-module can perform parallel-serial conversion on the test result to obtain a serial test result, and send the converted test result to the test access port in the target test access module, and the test access port in the target test access module outputs the test result through the second output interface.

In the embodiment of the application, under the condition that the bus signal received by the first bus interface characterizes the register to be tested to send the test result, the connection between the first bus interface and the interface address sub-module is conducted, so that the test result can be directly read from the first bus interface through the interface address sub-module, the test data and the test result are prevented from being sent and read by different modules, the test hardware cost is reduced, the test result is converted into serial test data through the data conversion sub-module, the serial test result is output to the second output interface through the test access port, and the test input port of the test register can receive the serial test result through the second output interface, so that the practicability of the test access circuit is improved.

In this embodiment of the present application, in a case where the test access module is regarded as the target test access module, the first control signal may be a control signal sent by the second state machine of the test access port in the target test access module. For example, the TAP controller sends out control signals such as Update IR, update DR and the like. The second control signal may be a control signal of a bus protocol corresponding to the second bus interface. For example, control signals such as Pwrite, psel, penable of the APB bus, or control signals such as Htrans and Hprot of the AHB bus.

In this embodiment of the present application, the interface control submodule is configured to receive a first control signal sent by a test access port in the target test access module, convert the first control signal into a bus control signal corresponding to the second bus interface according to a bus protocol corresponding to the second bus interface, obtain the second control signal, and send the second control signal to the side submodule. The side sub-module sends a second control signal to the register to be tested through the first bus interface, and the register to be tested receives the second control signal through the second bus interface.

For example, the Update DR control signal sent by the TAP controller is used to load data onto a pin, the interface control submodule may generate a high-level Pwrite control signal of the APB bus according to the Update DR control signal, where the high-level Pwrite control signal indicates a write operation, and the bypass submodule may send the high-level Pwrite control signal to the register to be tested through the first bus interface, which indicates that test data is to be written into the register to be tested through the second bus interface, so as to control the register to be tested to receive the test data.

In the embodiment of the application, the interface control sub-module is used for converting the first control signal sent by the test access port in the target test access module, so that the second control signal obtained by conversion is matched with the second bus interface, the register to be tested can be controlled by the second control signal to receive the test data, and the test result is sent to the first bus interface, thereby realizing the access and test of the register to be tested, and improving the practicability of the test access circuit of the application.

Optionally, the main port module includes a first enabling interface, and the test access module includes a second enabling interface, where the second enabling interface is connected with the first enabling interface;

the main port module is further configured to generate an enable signal according to the configuration signal, and send the enable signal to a corresponding test access module through the first enable interface;

the test access module is used for receiving the enabling signal through the second enabling interface, and responding to the enabling signal to start the data conversion sub-module, the interface address sub-module and the interface control sub-module.

In this embodiment of the present application, the test access circuit may include a test clock interface, a test reset interface, and a test mode selection interface, where the main port module and the test access module are respectively connected to the test clock interface, the test reset interface, and the test mode selection interface, so as to share a test clock signal sent by the test register through the test clock interface, a test reset signal sent by the test reset interface, and a test mode selection signal sent by the test mode selection interface. For example, the test clock interface, the test reset interface, and the test mode selection interface in JTAG correspond to the interfaces of the TCK test clock signal, the TRST internal TAP controller reset signal, and the TMS test mode selection signal, respectively.

In this embodiment, the test access port may include a reset signal interface for receiving a test reset signal, and the data conversion sub-module, the interface address sub-module, and the interface control sub-module may be connected to include clock signal interfaces respectively for receiving a test clock signal.

In this embodiment of the present application, the test access module may further include a Clock Gating unit (CG), where an output interface of the Clock Gating unit is connected to the data conversion sub-module, the interface address sub-module, and the interface control sub-module, and the Clock Gating unit may be connected to the second enabling interface of the test access module and the test Clock interface. The main port module can generate an enabling signal corresponding to a certain test access module according to the configuration signal, and send the enabling signal to the corresponding test access module through the first enabling interface. The test access module receives the enabling signal through the second enabling interface, sends the enabling signal to the gating clock unit, and transmits the test clock signal to the data conversion sub-module, the interface address sub-module and the interface control sub-module under the condition that the enabling signal characterizes to start each module so as to respond to the enabling signal to start the data conversion sub-module, the interface address sub-module and the interface control sub-module.

For example, the main port module sends an enable signal tap_en=1 to the corresponding test access module through the first enable interface, and the test access module starts the data conversion sub-module, the interface address sub-module and the interface control sub-module. When tap_en=0, the data conversion sub-module, the interface address sub-module and the interface control sub-module, the signal of the first bus interface is in an invalid state, and only the second state machine of the test access port in the test access module works at the moment.

Therefore, the energy consumption and the hardware consumption of the test access module can be reduced, the energy consumption of the test access circuit is reduced, and the hardware life of the test access circuit is prolonged.

Fig. 2 is a schematic structural diagram of another test access circuit according to an embodiment of the present application, as shown in fig. 2, the test access circuit (Test Access Network, TAN) includes: a Main test access port (main_tap) of the Main port module, a first bypass (Byp _mtap), a jtag and apb converter (jtag 2 apb) of the test access module, a second bypass (Byp _j2a) and a first bus interface (aXb interface). The jtag and apb converters may be configured as jtag and ahb converters, that is, jtag2apb is replaced by jtag2ahb, and accordingly, the first bus interface corresponding to jtag2apb is apb interface, and the first bus interface corresponding to jtag2ahb is ahb interface. This is by way of example only, and the embodiments of the present application are not limited thereto. It should be noted that any one of the jtag2apb includes a Test Access Port (TAP) therein. Main_tap includes: a first input interface (tdi), a first output interface (tdo), a test clock interface (Tck), a test reset interface (trst), a test mode selection interface (tms) and a first enable interface (tap_en). Any of the jtag2 apbs (configurable as jtag2 ahb) includes: a second input interface (tdi), a second output interface (tdo), a test clock interface (Tck), a test reset interface (trst), a test mode selection interface (tms) and a second enable interface (tap_en). The TAN is based on a daisy chain structure, that is, main_tap and jtag2apb in fig. 2 are connected end to end, a front stage tdo is connected with a rear stage tdi, a byp_mtap is inserted between main_tap and s0_jtag2apb, a Byp _j2a is inserted between each test access module, and TCK, TRST, TMS signals sent by test registers are shared between main_tap and jtag2 apb.

Fig. 3 is a schematic structural diagram of a jtag2apb provided in an embodiment of the present application, as shown in fig. 3, where the jtag2apb includes: test access port (Tap), data conversion sub-module (data_converter), interface address sub-module (Apb _data_gen), interface control sub-module (Apb _ctrl_gen), multiple Multiplexers (MUX) in the side sub-modules, gating clock unit (cg), TRST interface, TDI interface, TCK interface, TDO interface, tap_en interface, I/O interfaces prdata_i, pwdata_i, pwdata_o, paddr_o, etc. of the APB bus. Wherein the test access port (tap) further comprises: reset1 interface, scu interface and pinstr interface, reset1 interface are used for outputting Reset signal, scu interface is used for outputting three JTAG control signals of shift dr, capture dr, update dr, pinstr interface is used for outputting JTAG other signals. The Data conversion submodule (data_converter) is connected to the Reset1 interface, the scu interface, the TDI interface and the gating clock unit (cg) and is connected in a bidirectional manner to the interface address submodule (Apb _data_gen). The interface address submodule (Apb _data_gen) is connected with a gating clock unit (cg), a scu interface, a pinstr interface, an I/O interface Prdata_i of an APB bus and interfaces with Pwdata_o and Paddr_o through MUXs in the bypass submodule. The interface control submodule (Apb _ctrl_gen) is connected with the gating clock unit (cg), scu interface and Pwrite_o, psel_o and Penable_o interfaces through MUXs in the side submodules. The bypass submodule comprises 5 MUXs, the bypass submodule further comprises a TESTMODE interface, and the TESTMODE interface is used for receiving TMS signals, bypassing I/O interfaces Pwdata_i, paddr_i, pwrite_i, psel_i and Penable_i of the APB bus and conducting connection between the Prdata_i interface and an interface address submodule (Apb _data_gen) under the condition that the TMS signals characterize a start test mode.

Referring to fig. 3, the jtag2apb circuit operates in the following manner, the test access port (tap) is reset in response to the TRST signal, and a state machine inside the tap is started under the driving of the TMS signal, and the state machine is compatible with the IEEE 1149.1 standard protocol. When the enable signal tap_en sent to the jtag2apb by the Main test access port (main_tap) of the Main port module is 1, the gating clock unit (cg) starts the Data conversion sub-module (data_converter), the interface address sub-module (Apb _data_gen) and the interface control sub-module (Apb _ctrl_gen) through the TCK signal.

When writing a first bus interface (APB interface), under the condition that a state machine (FSM) of a test register is in a shift IR stage, an operation address and a writing identification are serially driven, serial-parallel conversion is carried out in a data_converter, the operation address and the writing identification are sent to an apb_data_gen, APB bus protocol matching is carried out in the apb_data_gen, the operation address and the writing identification are then sent to Mux corresponding to a Paddr_o in a side sub-module, and finally the operation address and the writing identification are output to the APB interface through the Paddr_o interface. And under the condition that the FSM is in a shift DR stage, serially driving operands, performing serial-parallel conversion in a data_converter, performing APB bus protocol matching on the parallel operands in an apb_data_gen, performing Mux corresponding to Pwdata_o, and finally outputting the Mux to the APB interface through a Pwdata_o interface.

When a first bus interface (APB interface) is read, the test register is serially driven into an operation address and a read identifier under the condition that the FSM is in a shift IR stage, the operation address and the read identifier are serially and parallelly converted in a data_converter and then sent to an apb_data_gen, APB bus protocol matching is carried out in the apb_data_gen, then the operation address and the read identifier are sent to Mux corresponding to Paddr_o in a side sub-module, and finally the operation address and the read identifier are output to the APB interface through the Paddr_o interface. When FSM is in shift DR stage, apb_data_gen reads in parallel test result from prdata_i, and carries out parallel-to-serial conversion through data_converter, and finally sends the result to test access port (tap), and the result is output to second output interface (TDO) of test access module through own TDO interface.

In this embodiment of the present application, when the second state machine in the test access port (tap) of the P test access modules and the state machine inside the test register are in a synchronous state, the test register drives the operands in series under the condition that the state machine (FSM) of the test register is in the shift IR stage, and the second state machine in the test access port (tap) of the P test access modules is also in the shift IR stage, so that the test register can synchronously receive the operands sent by the test register, and thus the test register performs synchronous write operation on the P test access modules. This is by way of example only, and the embodiments of the present application are not limited thereto.

Fig. 4 is a flowchart illustrating steps of a test access method according to an embodiment of the present application, and as shown in fig. 4, the embodiment of the present application provides a test access method applied to a test access circuit according to the foregoing embodiment, where the circuit includes: the device comprises a main port module and N cascaded test access modules, wherein the N test access modules are connected with the main port module, N is a positive integer, the test access modules comprise test access ports, and the method comprises the following steps:

step 201, receiving a configuration signal sent by a test register through the main port module, configuring the N test access modules according to the configuration signal, and determining a target test access module corresponding to a register to be tested of a chip from the plurality of test access modules according to a configuration result;

step 202, receiving test data sent by the test register through the target test access module, sending the test data to the register to be tested through a test access port in the target test access module, and sending a test result of the register to be tested to the test register.

In this embodiment of the present application, according to a configuration result, a currently available enabled test access module of the N test access modules may be determined as a target test access module corresponding to a register to be tested of the chip. Specifically, the main port module may configure an available test access module closest to the register to be tested from the N test access modules to be in an enabled state, or may configure an available test access module with a shortest access path to the register to be tested from the N test access modules to be in an enabled state, which is only illustrated herein, and the embodiment of the present application does not limit the present application.

In this embodiment, the test data may be an operand sent by the test register to the register to be tested, where the operand specifies an amount of digital operation performed by the register to be tested. The target test access module receives the operand sent by the test register, accesses the register to be tested through the test access port in the target test access module, and sends the operand to the register to be tested. Specifically, the target test access module may receive an operation address sent by the test register, where the operation address may be a memory address of the register to be tested, and the test access port in the target test access module may send an operand to the register to be tested according to the operation address through a bus interface mounted on the target test access module and a bus connected to the register to be tested. The bus to which the register to be tested is connected may be an advanced peripheral interface bus (Advanced Peripheral Bus, APB), an advanced high-performance bus (Advanced High Performance Bus, AHB), etc., and the bus interface on which the target test access module is mounted may be an APB bus or a bus interface corresponding to the AHB bus, which is only illustrated herein, and the embodiment of the present application does not limit the present application.

In this embodiment of the present application, the test result may be a result obtained by performing digital operation on a register value stored in the register to be tested according to an operand, where the register to be tested receives the operand sent by the target test access module through the test access port in the target test access module, and the result is used as a test result, and the test result is returned to the target test access module. The target test access module receives a test result returned by the register to be tested, and can send the test result of the register to be tested to the test register through the TDO of the target test access module so that the test result can be designated by the test register, for example, the test result is sent to a JTAG test tool and the like. This is by way of example only, and the embodiments of the present application are not limited thereto.

The test access method in the embodiment of the present application has the same advantages as those of the test access circuit compared with the prior art, and is not described herein.

Optionally, the test access module further includes a second bypass;

In the embodiment of the present application, the specific implementation manner of the steps may refer to the relevant functional descriptions of each component in the circuit embodiment, which are not repeated herein.

An embodiment of the present application provides a chip, including the test access circuit described in the foregoing embodiment, for performing the test access method described in the foregoing embodiment.

It should be understood that the chips referred to in the embodiments of the present application may also be referred to as system-on-chip chips, chip systems, or system-on-chip chips, etc.

The present embodiment provides a readable storage medium having stored thereon a program or instructions which, when executed by a processor, implement the steps of the test access method described in the previous embodiment.

An embodiment of the present application provides an electronic device 30, see fig. 5, the electronic device 30 comprising a test access circuit 10 as described above.

The electronic device 30 of the embodiment of the present application has the same advantages as those of the circuit embodiments in the prior art, and is not described herein.

Based on the same technical concept as the previous embodiments, another electronic device 40 is provided in the embodiments of the present application, and referring to fig. 6, the electronic device 40 includes a processor 401 and a memory 402; wherein the memory 402 is used to store computer programs and data; a processor 401 for executing a computer program stored in said memory 402 for implementing the method of any of the previous embodiments.

In practice, the memory 402 may provide instructions and data to the processor 401. The processor 401 may be at least one of an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), a digital signal processing technology chip (Digital Signal Processing, DSP), a programmable logic device (Programmable Logic Device, PLD), a field programmable gate array (Field Programmable Gate Array, FPGA), a CPU, a processor, a microcontroller, and a microprocessor.

Fig. 7 is a schematic structural diagram of still another electronic device 50 implementing an embodiment of the present application, as shown in fig. 7, where the electronic device 50 includes, but is not limited to: radio frequency unit 501, network module 502, audio output unit 503, input unit 504, test access circuit 505, display unit 506, user input unit 507, interface unit 508, memory 509, and processor 510.

Those skilled in the art will appreciate that the electronic device 50 may also include a power source, such as a battery, for powering the various components, which may be logically connected to the processor 510 via a power management system so as to perform functions such as managing charge, discharge, and power consumption via the power management system. The electronic device structure shown in fig. 7 does not constitute a limitation of the electronic device, and the electronic device may include more or less components than shown, or may combine certain components, or may be arranged in different components, which are not described in detail herein.

It should be appreciated that in embodiments of the present application, the input unit 504 may include a graphics processor (Graphics Processing Unit, GPU) 504 'and a microphone 504", with the graphics processor 504' processing image data of still pictures or video obtained by an image capturing device, such as a camera, in a video capturing mode or an image capturing mode. The display unit 506 may include a display panel 506', and the display panel 506' may be configured in the form of a liquid crystal display, an organic light emitting diode, or the like. The user input unit 507 includes at least one of a touch panel 507' and other input devices 507 ". The touch panel 507', also referred to as a touch screen. The touch panel 507' may include two parts, a touch detection device and a touch controller. Other input devices 507 "may include, but are not limited to, a physical keyboard, function keys, a trackball, a mouse, a joystick. The function keys, such as volume control keys, switch keys, etc., are not described herein.

The memory 509 may be used to store software programs as well as various data. Further, the memory 509 may include volatile memory or nonvolatile memory, or the memory 509 may include both volatile and nonvolatile memory. The nonvolatile Memory may be a Read-Only Memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an Electrically Erasable EPROM (EEPROM), or a flash Memory. The volatile memory may be random access memory (Random Access Memory, RAM), static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (ddr SDRAM), enhanced SDRAM (Enhanced SDRAM), synchronous DRAM (SLDRAM), and Direct RAM (DRRAM). Memory 509 in embodiments of the present application includes, but is not limited to, these and any other suitable types of memory.

Processor 510 may include one or at least two processing units. Optionally, the processor 510 integrates an application processor that primarily processes operations involving an operating system, user interface, application programs, etc., and a modem processor that primarily processes wireless communication signals, such as a baseband processor. It will be appreciated that the modem processor described above may not be integrated into the processor 510.

The present embodiments provide a computer program product stored in a storage medium for execution by at least one processor to implement the test access method described in the previous embodiments.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. Furthermore, it should be noted that the scope of the methods and apparatus in the embodiments of the present application is not limited to performing the functions in the order shown or discussed, but may also include performing the functions in a substantially simultaneous manner or in an opposite order depending on the functions involved, e.g., the described methods may be performed in an order different from that described, and various steps may also be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

From the above description of the embodiments, it will be clear to those skilled in the art that the above-described embodiment method may be implemented by means of software plus a necessary general hardware platform, but of course may also be implemented by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solutions of the present application may be embodied essentially or in a part contributing to the prior art in the form of a computer software product stored in a storage medium, such as a ROM/RAM, a magnetic disk, an optical disk, comprising instructions for causing a terminal, which may be a mobile phone, a computer, a server, a network device, or the like, to perform the methods described in the embodiments of the present application.

The embodiments of the present application have been described above with reference to the accompanying drawings, but the present application is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those of ordinary skill in the art without departing from the spirit of the present application and the scope of the claims, which are also within the protection of the present application.

Claims

1. A test access circuit, the circuit comprising: the device comprises a main port module and N cascaded test access modules, wherein the N test access modules are connected with the main port module, N is a positive integer, and the test access modules comprise test access ports;

2. The circuit of claim 1, wherein the main port module comprises a first input interface and a first output interface, the first input interface being connected with a test output interface of the test register; the test access module comprises a second input interface and a second output interface; the N test access modules comprise a multi-level test access module;

3. The circuit of claim 2, wherein the primary port module further comprises a first bypass connected to the test output interface, a first output interface, and a second input interface of the first stage test access module;

4. The circuit of claim 2, wherein the test access module further comprises a second bypass;

5. The circuit of claim 2, wherein the test access module further comprises a first bus interface;

6. The circuit of claim 5, wherein the test access module further comprises a data conversion sub-module, an interface address sub-module, and a bypass sub-module; the bypass submodule is connected with the first bus interface;

7. The circuit of claim 6, wherein the data conversion sub-module is further configured to receive the test data via the second input interface, perform serial-to-parallel conversion on the test data, and send the converted test data to the interface address sub-module;

8. The circuit of claim 6, wherein the bypass submodule is further configured to conduct connection of the first bus interface to the interface address submodule if the bus signal received by the first bus interface characterizes the register under test to send the test result;

9. The circuit of claim 6, wherein the test access module further comprises an interface control sub-module, the interface control sub-module being coupled to the test access port;

10. A test access method, applied to a test access circuit as claimed in any one of claims 1 to 9, the circuit comprising: the device comprises a main port module and N cascaded test access modules, wherein the N test access modules are connected with the main port module, N is a positive integer, the test access modules comprise test access ports, and the method comprises the following steps:

11. A chip comprising a test access circuit according to any of claims 1-9 for performing the test access method according to claim 10.

12. A readable storage medium, wherein a program or instructions is stored on the readable storage medium, which when executed by a processor, implement the steps of the test access method of claim 10.