CN116418994A

CN116418994A - Image coding method and device

Info

Publication number: CN116418994A
Application number: CN202111640001.9A
Authority: CN
Inventors: 李国怀
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-12-29
Filing date: 2021-12-29
Publication date: 2023-07-11
Also published as: WO2023125518A1

Abstract

The application relates to an image coding method and device, which are used for coding stored images in a memory mapping mode, so that memory copying is reduced, and coding efficiency is improved. The method comprises the following steps: firstly, distributing a storage memory for an input image; dividing a storage memory into a plurality of memory slices; and then reading data from the address of at least one memory slice in the plurality of memory slices through an encoder and encoding to obtain encoded data.

Description

Image coding method and device

Technical Field

The present application relates to the field of artificial intelligence, and in particular, to an image encoding method and apparatus.

Background

In some scenes associated with images, such as photographs, inter-image scenes, etc., it is often necessary to encode the image for storage. In general, in the encoding process, an image is divided into a plurality of slices (Grid), and then each slice is encoded, so that the compression efficiency of the image can be improved, the encoding performance can be improved, and thus the image slicing process is particularly important

However, when the image is sliced, there are a large number of copies of the memory, which would bring additional overhead, and additional memory would be consumed to carry the slice data, and the slicing process would be costly. Therefore, how to reduce the cost of slicing process is a urgent problem to be solved.

Disclosure of Invention

The application provides an image coding method and device, which are used for coding stored images in a memory mapping mode, so that memory copying is reduced, and coding efficiency is improved.

In view of this, in a first aspect, the present application provides an image encoding method, including: firstly, distributing a storage memory for an input image; dividing a storage memory into a plurality of memory slices; and then reading data from the address of at least one memory slice in the plurality of memory slices through an encoder and encoding to obtain encoded data.

Therefore, in the embodiment of the application, the address of the data to be encoded can be directly mapped to the encoder, so that the encoder can directly extract the data to be encoded based on the address, memory copying is not needed, memory overhead for memory copying can be reduced, and encoding efficiency can be improved.

In one possible embodiment, the dividing the storage memory into the plurality of memory slices may include: dividing the storage memory into a plurality of memory slices according to a preset slice size, wherein the preset slice size comprises a preset height and a preset width.

Therefore, in the embodiment of the present application, when the storage memory is divided, the division may be performed according to a preset slice size, so that the subsequent encoder may perform encoding in units of the preset slice size.

In one possible implementation manner, the foregoing allocating storage memory for the input image may include: and allocating storage memory for the input image based on a preset slice size.

In one possible implementation, the storage memory may include a first memory in which information of each pixel point in the input image is stored, and a second memory for aligning the size of the storage memory according to a preset slice size, so that the encoder reads data from the input address in units of the preset slice size.

Therefore, in the embodiment of the application, when the memory of the input image is not divided by the preset slice size, the address of the obtained memory slice can be mapped to the encoder for encoding, so that final encoded data is obtained, the memory copy amount is reduced, the memory overhead for performing memory copy can be reduced, and the encoding efficiency can be improved.

In one possible implementation, the storage memories are arranged in an array, and the width of the storage memories is divided by a preset width, and the height of the storage memories is divided by a preset height.

Therefore, in the embodiment of the application, when the memory is allocated to the input image, the alignment can be performed according to the preset width and the preset height, so that when the memory slices are divided, the size of each memory slice is the preset slice size, out-of-range when the encoder reads the address is avoided, only a small amount of memory is allocated, the memory copy amount is reduced, the memory cost for copying the memory can be reduced, and the encoding efficiency can be improved.

In one possible implementation, the second memory includes a third memory and a fourth memory, where the first memory and the third memory are arranged in an array after being combined, the height of the array is divided by a preset height, and the remainder of dividing the last row of the array by a preset width is not less than the preset width after being combined with the fourth memory.

Therefore, in the embodiment of the application, when the memory is allocated for the input image, the height of the allocated memory can be aligned with the preset height, in order to avoid out-of-range when the encoder reads, additional memory can be allocated for the last row, so that the remainder of the last row of the array divided by the preset width is not less than the preset width after being combined with the fourth memory, out-of-range when the encoder reads the address is avoided, only a small amount of memory is allocated, the memory copy quantity is reduced, the memory overhead for copying the memory can be reduced, and the encoding efficiency can be improved.

In one possible implementation manner, the plurality of memory slices are divided into a first memory slice and a second memory slice, the first memory slice has a preset height, the second memory slice has a height smaller than the preset height or the second memory slice is the last slice of the last row in the array formed by the plurality of memory slices, and the first memory slice and the second memory slice are different memory slices; the method may further include: a fifth memory is allocated for a second memory slice in the memory slices, data in the second memory is copied into the fifth memory, the width of the fifth memory is divided by a preset width, and the height of the fifth memory is divided by a preset height; the inputting the address of at least one memory slice of the plurality of memory slices to the encoder may include: an address of a first memory slice and an address of a fifth memory of the plurality of memory slices are input to the encoder.

Therefore, in the embodiment of the application, the occupied memory can be allocated for the input image based on the size of the input image, then the memory is divided, when the memory of the input image is not divided by the preset slice size, the obtained address of the memory matched with the preset slice size can be mapped to the encoder for encoding, and the data is copied from the divided part and used as the input of the encoder, so that the final encoded data is obtained, all the memories in the memory are not required to be copied, the memory copying amount is reduced, the memory cost for copying the memory can be reduced, and the encoding efficiency can be improved.

In one possible implementation, the height of the storage memory is divided by a preset height.

Therefore, in the embodiment of the application, when the memory of the input image is not divided by the preset slice size, in the process of allocating the memory for the input image, the heights of the allocated memories can be aligned according to the preset heights, so that the number of the sizes of the slices which are different from the preset slice size can be reduced. And then mapping the obtained address of the memory matched with the preset slice size to an encoder for encoding, copying data from the whole divided part and taking the copied data as the input of the encoder to obtain final encoded data, and the final encoded data does not need to copy all memories in the storage memory, so that the memory copy quantity is reduced, the memory cost for performing memory copy can be reduced, and the encoding efficiency can be improved.

In a second aspect, the present application provides an image encoding apparatus, comprising:

the distribution module is used for distributing a storage memory for the input image;

the dividing module is used for dividing the storage memory into a plurality of memory slices;

the encoding module is used for inputting the address of at least one memory slice in the memory slices to the encoder, and the encoder is used for reading data based on the input address and encoding the data to obtain encoded data.

In one possible implementation, the dividing module is specifically configured to divide the storage memory into a plurality of memory slices according to a preset slice size, where the preset slice size includes a preset height and a preset width.

In one possible embodiment, it is specifically used for: and allocating storage memory for the input image based on a preset slice size.

In one possible implementation, the storage memory includes a first memory and a second memory, where the first memory stores information of each pixel point in the input image, and the second memory is used to align the size of the storage memory according to a preset slice size, so that the encoder reads data from the input address in units of the preset slice size.

In one possible implementation manner, the plurality of memory slices are divided into a first memory slice and a second memory slice, the first memory slice has a preset height, the second memory slice has a height smaller than the preset height or the second memory slice is the last slice of the last row in the array formed by the plurality of memory slices, and the first memory slice and the second memory slice are different memory slices;

the allocation module is further used for allocating a fifth memory for a second memory slice in the plurality of memory slices, copying data in the second memory to the fifth memory, dividing the width of the fifth memory by a preset width, and dividing the height of the fifth memory by a preset height;

the encoding module is specifically configured to input an address of a first memory slice and an address of a fifth memory of the plurality of memory slices to the encoder.

In a third aspect, an embodiment of the present application provides an electronic device, including: the processor and the memory are interconnected by a line, and the processor invokes the program code in the memory to perform the processing-related functions in the image encoding method according to any one of the first aspect. Alternatively, the electronic device may be a chip.

In a fourth aspect, embodiments of the present application provide an electronic device, which may also be referred to as a digital processing chip or chip, the chip including a processing unit and a communication interface, the processing unit obtaining program instructions through the communication interface, the program instructions being executed by the processing unit, the processing unit being configured to perform a processing-related function as in the first aspect or any of the alternative embodiments of the first aspect.

In a fifth aspect, embodiments of the present application provide a computer-readable storage medium comprising instructions that, when run on a computer, cause the computer to perform the method of the first aspect or any of the alternative embodiments of the first aspect.

In a sixth aspect, embodiments of the present application provide a computer program product comprising instructions which, when run on a computer, cause the computer to perform the method of the first aspect or any of the alternative embodiments of the first aspect.

Drawings

Fig. 1 is a schematic structural diagram of an electronic device provided in the present application;

fig. 2 is a schematic structural diagram of another electronic device provided in the present application;

FIG. 3 is a schematic flow chart of an image encoding method provided in the present application;

FIG. 4 is a schematic diagram of a structure of a memory according to the present disclosure;

fig. 5 is a schematic structural diagram of another electronic device provided in the present application;

FIG. 6 is a flowchart of another image encoding method provided in the present application;

FIG. 7 is a schematic diagram of another embodiment of a memory according to the present disclosure;

FIG. 8 is a schematic diagram of another embodiment of a memory according to the present disclosure;

FIG. 9 is a schematic diagram of another embodiment of a memory according to the present disclosure;

FIG. 10 is a schematic diagram of another embodiment of a memory according to the present disclosure;

FIG. 11 is a schematic diagram of another embodiment of a memory according to the present disclosure;

FIG. 12 is a schematic diagram of another embodiment of a memory according to the present disclosure;

fig. 13 is a schematic structural diagram of an image encoding device provided in the present application;

fig. 14 is a schematic structural diagram of another electronic device provided in the present application.

Detailed Description

The following description of the technical solutions in the embodiments of the present application will be made with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.

First, the method provided in the present application may be deployed in various electronic devices, such as various terminals or servers, where the servers may be various independent servers, distributed servers, or centralized servers, and the terminals may include, but are not limited to: smart mobile phones, televisions, tablet computers, bracelets, head mounted display devices (Head Mount Display, HMD), augmented reality (augmented reality, AR) devices, mixed Reality (MR) devices, cellular phones (cellular phones), smart phones (smart phones), personal digital assistants (personal digital assistant, PDA), tablet computers, car terminals, laptop computers (or so-called notebook or laptop computers), personal computers (personal computer, PC), and the like.

By way of example, referring to fig. 1, a specific structure of the electronic device provided in the present application will be described below by taking a specific structure as an example.

The electronic device 100 may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (universal serial bus, USB) interface 130, a charge management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, an earphone interface 170D, a sensor module 180, keys 190, a motor 191, an indicator 192, a camera 193, a display 194, and a subscriber identity module (subscriber identification module, SIM) card interface 195, etc. The sensor module 180 may include a pressure sensor 180A, a gyroscope sensor 180B, an air pressure sensor 180C, a magnetic sensor 180D, an acceleration sensor 180E, a distance sensor 180F, a proximity sensor 180G, a fingerprint sensor 180H, a temperature sensor 180J, a touch sensor 180K, an ambient light sensor 180L, a bone conduction sensor 180M, a motion sensor 180N, and the like.

It should be understood that the illustrated structure of the embodiment of the present invention does not constitute a specific limitation on the electronic device 100. In other embodiments of the present application, electronic device 100 may include more or fewer components than shown, or certain components may be combined, or certain components may be split, or different arrangements of components. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

The processor 110 may include one or more processing units, such as: the processor 110 may include an application processor (application processor, AP), a modem processor, a graphics processor (graphics processing unit, GPU), an image signal processor (image signal processor, ISP), a controller, a video codec, a digital signal processor (digital signal processor, DSP), a baseband processor, and/or a neural network processor (neural-network processing unit, NPU), etc. Wherein the different processing units may be separate devices or may be integrated in one or more processors.

The controller can generate operation control signals according to the instruction operation codes and the time sequence signals to finish the control of instruction fetching and instruction execution.

A memory may also be provided in the processor 110 for storing instructions and data. In some embodiments, the memory in the processor 110 is a cache memory. The memory may hold instructions or data that the processor 110 has just used or recycled. If the processor 110 needs to reuse the instruction or data, it can be called directly from the memory. Repeated accesses are avoided and the latency of the processor 110 is reduced, thereby improving the efficiency of the system.

In some embodiments, the processor 110 may include one or more interfaces. The interfaces may include an integrated circuit (inter-integrated circuit, I2C) interface, an integrated circuit built-in audio (inter-integrated circuit sound, I2S) interface, a pulse code modulation (pulse code modulation, PCM) interface, a universal asynchronous receiver transmitter (universal asynchronous receiver/transmitter, UART) interface, a mobile industry processor interface (mobile industry processor interface, MIPI), a general-purpose input/output (GPIO) interface, a subscriber identity module (subscriber identity module, SIM) interface, and/or a universal serial bus (universal serial bus, USB) interface, among others.

The I2C interface is a bi-directional synchronous serial bus comprising a serial data line (SDA) and a serial clock line (derail clock line, SCL). In some embodiments, the processor 110 may contain multiple sets of I2C buses. The processor 110 may be coupled to the touch sensor 180K, charger, flash, camera 193, etc., respectively, through different I2C bus interfaces. For example: the processor 110 may be coupled to the touch sensor 180K through an I2C interface, such that the processor 110 communicates with the touch sensor 180K through an I2C bus interface to implement a touch function of the electronic device 100.

The I2S interface may be used for audio communication. In some embodiments, the processor 110 may contain multiple sets of I2S buses. The processor 110 may be coupled to the audio module 170 via an I2S bus to enable communication between the processor 110 and the audio module 170. In some embodiments, the audio module 170 may transmit an audio signal to the wireless communication module 160 through the I2S interface, to implement a function of answering a call through the bluetooth headset.

PCM interfaces may also be used for audio communication to sample, quantize and encode analog signals. In some embodiments, the audio module 170 and the wireless communication module 160 may be coupled through a PCM bus interface. In some embodiments, the audio module 170 may also transmit audio signals to the wireless communication module 160 through the PCM interface to implement a function of answering a call through the bluetooth headset. Both the I2S interface and the PCM interface may be used for audio communication.

The UART interface is a universal serial data bus for asynchronous communications. The bus may be a bi-directional communication bus. It converts the data to be transmitted between serial communication and parallel communication. In some embodiments, a UART interface is typically used to connect the processor 110 with the wireless communication module 160. For example: the processor 110 communicates with a bluetooth module in the wireless communication module 160 through a UART interface to implement a bluetooth function. In some embodiments, the audio module 170 may transmit an audio signal to the wireless communication module 160 through a UART interface, to implement a function of playing music through a bluetooth headset.

The MIPI interface may be used to connect the processor 110 to peripheral devices such as a display 194, a camera 193, and the like. The MIPI interfaces include camera serial interfaces (camera serial interface, CSI), display serial interfaces (display serial interface, DSI), and the like. In some embodiments, processor 110 and camera 193 communicate through a CSI interface to implement the photographing functions of electronic device 100. The processor 110 and the display 194 communicate via a DSI interface to implement the display functionality of the electronic device 100.

The GPIO interface may be configured by software. The GPIO interface may be configured as a control signal or as a data signal. In some embodiments, a GPIO interface may be used to connect the processor 110 with the camera 193, the display 194, the wireless communication module 160, the audio module 170, the sensor module 180, and the like. The GPIO interface may also be configured as an I2C interface, an I2S interface, a UART interface, an MIPI interface, etc.

The USB interface 130 is an interface conforming to the USB standard specification, and may specifically be a Mini USB interface, a Micro USB interface, a USB Type C interface, or the like. The USB interface 130 may be used to connect a charger to charge the electronic device 100, and may also be used to transfer data between the electronic device 100 and a peripheral device. And can also be used for connecting with a headset, and playing audio through the headset. The interface may also be used to connect other electronic devices, such as AR devices, etc. It should be understood that the USB interface 130 may be replaced by other interfaces, such as Type-c or Lighting, which may implement charging or data transmission, and the USB interface 130 is merely illustrated herein as an example.

It should be understood that the interfacing relationship between the modules illustrated in the embodiments of the present invention is only illustrative, and is not meant to limit the structure of the electronic device 100. In other embodiments of the present application, the electronic device 100 may also use different interfacing manners, or a combination of multiple interfacing manners in the foregoing embodiments.

The charge management module 140 is configured to receive a charge input from a charger. The charger can be a wireless charger or a wired charger. In some wired charging embodiments, the charge management module 140 may receive a charging input of a wired charger through the USB interface 130. In some wireless charging embodiments, the charge management module 140 may receive wireless charging input through a wireless charging coil of the electronic device 100. The charging management module 140 may also supply power to the electronic device through the power management module 141 while charging the battery 142.

The power management module 141 is used for connecting the battery 142, and the charge management module 140 and the processor 110. The power management module 141 receives input from the battery 142 and/or the charge management module 140 to power the processor 110, the internal memory 121, the display 194, the camera 193, the wireless communication module 160, and the like. The power management module 141 may also be configured to monitor battery capacity, battery cycle number, battery health (leakage, impedance) and other parameters. In other embodiments, the power management module 141 may also be provided in the processor 110. In other embodiments, the power management module 141 and the charge management module 140 may be disposed in the same device.

The wireless communication function of the electronic device 100 may be implemented by the antenna 1, the antenna 2, the mobile communication module 150, the wireless communication module 160, a modem processor, a baseband processor, and the like.

The antennas 1 and 2 are used for transmitting and receiving electromagnetic wave signals. Each antenna in the electronic device 100 may be used to cover a single or multiple communication bands. Different antennas may also be multiplexed to improve the utilization of the antennas. For example: the antenna 1 may be multiplexed into a diversity antenna of a wireless local area network. In other embodiments, the antenna may be used in conjunction with a tuning switch.

The mobile communication module 150 may provide a solution for wireless communication including 2G/3G/4G/5G, etc., applied to the electronic device 100. The mobile communication module 150 may include at least one filter, switch, power amplifier, low noise amplifier (low noise amplifier, LNA), etc. The mobile communication module 150 may receive electromagnetic waves from the antenna 1, perform processes such as filtering, amplifying, and the like on the received electromagnetic waves, and transmit the processed electromagnetic waves to the modem processor for demodulation. The mobile communication module 150 can amplify the signal modulated by the modem processor, and convert the signal into electromagnetic waves through the antenna 1 to radiate. In some embodiments, at least some of the functional modules of the mobile communication module 150 may be disposed in the processor 110. In some embodiments, at least some of the functional modules of the mobile communication module 150 may be provided in the same device as at least some of the modules of the processor 110.

The modem processor may include a modulator and a demodulator. The modulator is used for modulating the low-frequency baseband signal to be transmitted into a medium-high frequency signal. The demodulator is used for demodulating the received electromagnetic wave signal into a low-frequency baseband signal. The demodulator then transmits the demodulated low frequency baseband signal to the baseband processor for processing. The low frequency baseband signal is processed by the baseband processor and then transferred to the application processor. The application processor outputs sound signals through an audio device (not limited to the speaker 170A, the receiver 170B, etc.), or displays images or video through the display screen 194. In some embodiments, the modem processor may be a stand-alone device. In other embodiments, the modem processor may be provided in the same device as the mobile communication module 150 or other functional module, independent of the processor 110.

The wireless communication module 160 may provide solutions for wireless communication including wireless local area network (wireless local area networks, WLAN) (e.g., wireless fidelity (wireless fidelity, wi-Fi) network), bluetooth (BT), global navigation satellite system (global navigation satellite system, GNSS), frequency modulation (frequency modulation, FM), near field wireless communication technology (near field communication, NFC), ultra Wide Band (UWB), infrared technology (IR), etc., applied to the electronic device 100. The wireless communication module 160 may be one or more devices that integrate at least one communication processing module. The wireless communication module 160 receives electromagnetic waves via the antenna 2, modulates the electromagnetic wave signals, filters the electromagnetic wave signals, and transmits the processed signals to the processor 110. The wireless communication module 160 may also receive a signal to be transmitted from the processor 110, frequency modulate it, amplify it, and convert it to electromagnetic waves for radiation via the antenna 2.

In some embodiments, antenna 1 and mobile communication module 150 of electronic device 100 are coupled, and antenna 2 and wireless communication module 160 are coupled, such that electronic device 100 may communicate with a network and other devices through wireless communication techniques. The wireless communication techniques may include, but are not limited to: fifth Generation mobile communication technology (5 th-Generation, 5G) systems, global system for mobile communications (global system for mobile communications, GSM), general packet radio service (general packet radio service, GPRS), code division multiple access (code division multiple access, CDMA), wideband code division multiple access (wideband code division multiple access, WCDMA), time division code division multiple access (time-division code division multiple access, TD-SCDMA), long term evolution (long term evolution, LTE), bluetooth (blue), global navigation satellite system (the global navigation satellite system, GNSS), wireless fidelity (wireless fidelity, wiFi), near field wireless communication (near field communication, NFC), FM (which may also be referred to as frequency modulation broadcast), zigbee, radio frequency identification technology (radio frequency identification, RFID) and/or Infrared (IR) technology, and the like. The GNSS may include a global satellite positioning system (global positioning system, GPS), a global navigation satellite system (global navigation satellite system, GLONASS), a beidou satellite navigation system (beidou navigation satellite system, BDS), a quasi zenith satellite system (quasi-zenith satellite system, QZSS) and/or a satellite based augmentation system (satellite based augmentation systems, SBAS), etc.

In some embodiments, the electronic device 100 may also include a wired communication module (not shown in fig. 1), or the mobile communication module 150 or the wireless communication module 160 may be replaced with a wired communication module (not shown in fig. 1) herein, which may enable the electronic device to communicate with other devices through a wired network. The wired network may include, but is not limited to, one or more of the following: optical transport network (optical transport network, OTN), synchronous digital hierarchy (synchronous digital hierarchy, SDH), passive optical network (passive optical network, PON), ethernet (Ethernet), or flexible Ethernet (FlexE), etc.

The electronic device 100 implements display functions through a GPU, a display screen 194, an application processor, and the like. The GPU is a microprocessor that displays an interface, and is connected to the display screen 194 and the application processor. The GPU is used to perform mathematical and geometric calculations for graphics rendering. Processor 110 may include one or more GPUs that execute program instructions to generate or change display information.

The display screen 194 is used to display images, videos, and the like. The display 194 includes a display panel. The display panel may employ a liquid crystal display (liquid crystal display, LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode (AMOLED) or an active-matrix organic light-emitting diode (matrix organic light emitting diode), a flexible light-emitting diode (flex), a mini, a Micro led, a Micro-OLED, a quantum dot light-emitting diode (quantum dot light emitting diodes, QLED), or the like. In some embodiments, the electronic device 100 may include 1 or N display screens 194, N being a positive integer greater than 1.

The electronic device 100 may implement photographing functions through an ISP, a camera 193, a video codec, a GPU, a display screen 194, an application processor, and the like.

The ISP is used to process data fed back by the camera 193. For example, when photographing, the shutter is opened, light is transmitted to the camera photosensitive element through the lens, the optical signal is converted into an electric signal, and the camera photosensitive element transmits the electric signal to the ISP for processing and is converted into an image visible to naked eyes. ISP can also optimize the noise, brightness and skin color of the image. The ISP can also optimize parameters such as exposure, color temperature and the like of a shooting scene. In some embodiments, the ISP may be provided in the camera 193.

The camera 193 is used to capture still images or video. The object generates an optical image through the lens and projects the optical image onto the photosensitive element. The photosensitive element may be a charge coupled device (charge coupled device, CCD) or a Complementary Metal Oxide Semiconductor (CMOS) phototransistor. The photosensitive element converts the optical signal into an electrical signal, which is then transferred to the ISP to be converted into a digital image signal. The ISP outputs the digital image signal to the DSP for processing. The DSP converts the digital image signal into an image signal in a format of a standard RGB camera, YUV, or the like. In some embodiments, electronic device 100 may include 1 or N cameras 193, N being a positive integer greater than 1.

The digital signal processor is used for processing digital signals, and can process other digital signals besides digital image signals. For example, when the electronic device 100 selects a frequency bin, the digital signal processor is used to fourier transform the frequency bin energy, or the like.

Video codecs are used to compress or decompress digital video. The electronic device 100 may support one or more video codecs. In this way, the electronic device 100 may play or record video in a variety of encoding formats, such as: dynamic picture experts group (moving picture experts group, MPEG) 1, MPEG2, MPEG3, MPEG4, etc.

The NPU is a neural-network (NN) computing processor, and can rapidly process input information by referencing a biological neural network structure, for example, referencing a transmission mode between human brain neurons, and can also continuously perform self-learning. Applications such as intelligent awareness of the electronic device 100 may be implemented through the NPU, for example: image recognition, face recognition, speech recognition, text understanding, etc.

The external memory interface 120 may be used to connect an external memory card, such as a Micro SD card, to enable expansion of the memory capabilities of the electronic device 100. The external memory card communicates with the processor 110 through an external memory interface 120 to implement data storage functions. For example, files such as music, video, etc. are stored in an external memory card.

The internal memory 121 may be used to store computer executable program code including instructions. The internal memory 121 may include a storage program area and a storage data area. The storage program area may store an application program (such as a sound playing function, an image playing function, etc.) required for at least one function of the operating system, etc. The storage data area may store data created during use of the electronic device 100 (e.g., audio data, phonebook, etc.), and so on. In addition, the internal memory 121 may include a high-speed random access memory, and may further include a nonvolatile memory such as at least one magnetic disk storage device, a flash memory device, a universal flash memory (universal flash storage, UFS), and the like. The processor 110 performs various functional applications of the electronic device 100 and data processing by executing instructions stored in the internal memory 121 and/or instructions stored in a memory provided in the processor.

The electronic device 100 may implement audio functions through an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, an earphone interface 170D, an application processor, and the like. Such as music playing, recording, etc.

The audio module 170 is used to convert digital audio information into an analog audio signal output and also to convert an analog audio input into a digital audio signal. The audio module 170 may also be used to encode and decode audio signals. In some embodiments, the audio module 170 may be disposed in the processor 110, or a portion of the functional modules of the audio module 170 may be disposed in the processor 110.

The speaker 170A, also referred to as a "horn," is used to convert audio electrical signals into sound signals. The electronic device 100 may listen to music, or to hands-free conversations, through the speaker 170A.

A receiver 170B, also referred to as a "earpiece", is used to convert the audio electrical signal into a sound signal. When electronic device 100 is answering a telephone call or voice message, voice may be received by placing receiver 170B in close proximity to the human ear.

Microphone 170C, also referred to as a "microphone" or "microphone", is used to convert sound signals into electrical signals. When making a call or transmitting voice information, the user can sound near the microphone 170C through the mouth, inputting a sound signal to the microphone 170C. The electronic device 100 may be provided with at least one microphone 170C. In other embodiments, the electronic device 100 may be provided with two microphones 170C, and may implement a noise reduction function in addition to collecting sound signals. In other embodiments, the electronic device 100 may also be provided with three, four, or more microphones 170C to enable collection of sound signals, noise reduction, identification of sound sources, directional recording functions, etc.

The earphone interface 170D is used to connect a wired earphone. The headset interface 170D may be a USB interface 130 or a 3.5mm open mobile electronic device platform (open mobile terminal platform, OMTP) standard interface, a american cellular telecommunications industry association (cellular telecommunications industry association of the USA, CTIA) standard interface.

The pressure sensor 180A is used to sense a pressure signal, and may convert the pressure signal into an electrical signal. In some embodiments, the pressure sensor 180A may be disposed on the display screen 194. The pressure sensor 180A is of various types, such as a resistive pressure sensor, an inductive pressure sensor, a capacitive pressure sensor, and the like. The capacitive pressure sensor may be a capacitive pressure sensor comprising at least two parallel plates with conductive material. The capacitance between the electrodes changes when a force is applied to the pressure sensor 180A. The electronic device 100 determines the strength of the pressure from the change in capacitance. When a touch operation is applied to the display screen 194, the electronic apparatus 100 detects the touch operation intensity according to the pressure sensor 180A. The electronic device 100 may also calculate the location of the touch based on the detection signal of the pressure sensor 180A. In some embodiments, touch operations that act on the same touch location, but at different touch operation strengths, may correspond to different operation instructions. For example: and executing an instruction for checking the short message when the touch operation with the touch operation intensity smaller than the first pressure threshold acts on the short message application icon. And executing an instruction for newly creating the short message when the touch operation with the touch operation intensity being greater than or equal to the first pressure threshold acts on the short message application icon.

The gyro sensor 180B may be used to determine a motion gesture of the electronic device 100. In some embodiments, the angular velocity of electronic device 100 about three axes (i.e., x, y, and z axes) may be determined by gyro sensor 180B. The gyro sensor 180B may be used for photographing anti-shake. For example, when the shutter is pressed, the gyro sensor 180B detects the shake angle of the electronic device 100, calculates the distance to be compensated by the lens module according to the angle, and makes the lens counteract the shake of the electronic device 100 through the reverse motion, so as to realize anti-shake. The gyro sensor 180B may also be used for navigating, somatosensory game scenes.

The air pressure sensor 180C is used to measure air pressure. In some embodiments, electronic device 100 calculates altitude from barometric pressure values measured by barometric pressure sensor 180C, aiding in positioning and navigation.

The magnetic sensor 180D includes a hall sensor. The electronic device 100 may detect the opening and closing of the flip cover using the magnetic sensor 180D. In some embodiments, when the electronic device 100 is a flip machine, the electronic device 100 may detect the opening and closing of the flip according to the magnetic sensor 180D. And then according to the detected opening and closing state of the leather sheath or the opening and closing state of the flip, the characteristics of automatic unlocking of the flip and the like are set.

The acceleration sensor 180E may detect the magnitude of acceleration of the electronic device 100 in various directions (typically three axes). The magnitude and direction of gravity may be detected when the electronic device 100 is stationary. The electronic equipment gesture recognition method can also be used for recognizing the gesture of the electronic equipment, and is applied to horizontal and vertical screen switching, pedometers and other applications.

A distance sensor 180F for measuring a distance. The electronic device 100 may measure the distance by infrared or laser. In some embodiments, the electronic device 100 may range using the distance sensor 180F to achieve quick focus.

The proximity light sensor 180G may include, for example, a Light Emitting Diode (LED) and a light detector, such as a photodiode. The light emitting diode may be an infrared light emitting diode. The electronic device 100 emits infrared light outward through the light emitting diode. The electronic device 100 detects infrared reflected light from nearby objects using a photodiode. When sufficient reflected light is detected, it may be determined that there is an object in the vicinity of the electronic device 100. When insufficient reflected light is detected, the electronic device 100 may determine that there is no object in the vicinity of the electronic device 100. The electronic device 100 can detect that the user holds the electronic device 100 close to the ear by using the proximity light sensor 180G, so as to automatically extinguish the screen for the purpose of saving power. The proximity light sensor 180G may also be used in holster mode, pocket mode to automatically unlock and lock the screen.

The ambient light sensor 180L is used to sense ambient light level. The electronic device 100 may adaptively adjust the brightness of the display 194 based on the perceived ambient light level. The ambient light sensor 180L may also be used to automatically adjust white balance when taking a photograph. Ambient light sensor 180L may also cooperate with proximity light sensor 180G to detect whether electronic device 100 is in a pocket to prevent false touches.

The fingerprint sensor 180H is used to collect a fingerprint. The electronic device 100 may utilize the collected fingerprint feature to unlock the fingerprint, access the application lock, photograph the fingerprint, answer the incoming call, etc.

The temperature sensor 180J is for detecting temperature. In some embodiments, the electronic device 100 performs a temperature processing strategy using the temperature detected by the temperature sensor 180J. For example, when the temperature reported by temperature sensor 180J exceeds a threshold, electronic device 100 performs a reduction in the performance of a processor located in the vicinity of temperature sensor 180J in order to reduce power consumption to implement thermal protection. In other embodiments, when the temperature is below another threshold, the electronic device 100 heats the battery 142 to avoid the low temperature causing the electronic device 100 to be abnormally shut down. In other embodiments, when the temperature is below a further threshold, the electronic device 100 performs boosting of the output voltage of the battery 142 to avoid abnormal shutdown caused by low temperatures.

The touch sensor 180K, also referred to as a "touch device". The touch sensor 180K may be disposed on the display screen 194, and the touch sensor 180K and the display screen 194 form a touch screen, which is also called a "touch screen". The touch sensor 180K is for detecting a touch operation acting thereon or thereabout. The touch sensor may communicate the detected touch operation to the application processor to determine the touch event type. Visual output related to touch operations may be provided through the display 194. In other embodiments, the touch sensor 180K may also be disposed on the surface of the electronic device 100 at a different location than the display 194.

The bone conduction sensor 180M may acquire a vibration signal. In some embodiments, bone conduction sensor 180M may acquire a vibration signal of a human vocal tract vibrating bone pieces. The bone conduction sensor 180M may also contact the pulse of the human body to receive the blood pressure pulsation signal. In some embodiments, bone conduction sensor 180M may also be provided in a headset, in combination with an osteoinductive headset. The audio module 170 may analyze the voice signal based on the vibration signal of the sound portion vibration bone block obtained by the bone conduction sensor 180M, so as to implement a voice function. The application processor may analyze the heart rate information based on the blood pressure beat signal acquired by the bone conduction sensor 180M, so as to implement a heart rate detection function.

The motion sensor 180N may be used to detect a moving object within a range shot by the camera, and collect a motion profile or a motion track of the moving object. For example, the motion sensor 180N may be an infrared sensor, a laser sensor, a dynamic vision sensor (dynamic vision sensor, DVS), etc., which may include, in particular, a DAVIS (Dynamic and Active-pixel Vision Sensor), ATIS (Asynchronous Time-based Image Sensor), or CeleX sensor, etc. DVS uses the biological vision characteristics to simulate a neuron per pixel, and responds independently to the relative change in illumination intensity (hereinafter referred to as "light intensity"). When the relative change in light intensity exceeds a threshold, the pixel outputs an event signal including the position of the pixel, a time stamp, and characteristic information of the light intensity.

The keys 190 include a power-on key, a volume key, etc. The keys 190 may be mechanical keys. Or may be a touch key. The electronic device 100 may receive key inputs, generating key signal inputs related to user settings and function controls of the electronic device 100.

The motor 191 may generate a vibration cue. The motor 191 may be used for incoming call vibration alerting as well as for touch vibration feedback. For example, touch operations acting on different applications (e.g., photographing, audio playing, etc.) may correspond to different vibration feedback effects. The motor 191 may also correspond to different vibration feedback effects by touching different areas of the display screen 194. Different application scenarios (such as time reminding, receiving information, alarm clock, game, etc.) can also correspond to different vibration feedback effects. The touch vibration feedback effect may also support customization.

The indicator 192 may be an indicator light, may be used to indicate a state of charge, a change in charge, a message indicating a missed call, a notification, etc.

The SIM card interface 195 is used to connect a SIM card. The SIM card may be inserted into the SIM card interface 195, or removed from the SIM card interface 195 to enable contact and separation with the electronic device 100. The electronic device 100 may support 1 or N SIM card interfaces, N being a positive integer greater than 1. The SIM card interface 195 may support Nano SIM cards, micro SIM cards, and the like. The same SIM card interface 195 may be used to insert multiple cards simultaneously. The types of the plurality of cards may be the same or different. The SIM card interface 195 may also be compatible with different types of SIM cards. The SIM card interface 195 may also be compatible with external memory cards. The electronic device 100 interacts with the network through the SIM card to realize functions such as communication and data communication. In some embodiments, the electronic device 100 employs esims, i.e.: an embedded SIM card. The eSIM card can be embedded in the electronic device 100 and cannot be separated from the electronic device 100.

It should be noted that, in some practical application scenarios, the electronic device may include more or fewer components than those shown in fig. 1, and may be specifically adjusted according to the practical application scenario, which is not limited in this application.

The foregoing describes exemplary hardware structures of an electronic device provided in the present application, where the system on which the electronic device may be mounted may include

Hong Monte or other operating systems, etc., which are not to be construed as limiting in any way.

To be carried on

For example, as shown in fig. 2, the electronic device 100 of the operating system is logically divided into a hardware layer 21, an operating system 261, and an application layer 31. The hardware layer 21 includes hardware resources such as an application processor 201, a microcontroller unit 203, a modem 207, a Wi-Fi module 211, a sensor 214, a positioning module 150, and the like. The application layer 31 includes one or more Applications (APP), such as application 263, and the application 263 may be any type of application, such as a social application, an e-commerce application, a browser, and the like. The operating system 261, which is a software middleware between the hardware layer 21 and the application layer 31, is a computer program that manages and controls hardware and software resources.

In one embodiment, operating system 261 includes kernel 23, hardware abstraction layer (hardware abstraction layer, HAL) 25, library and runtime (libraries and runtime) 27, and framework (frame) 29. Wherein the kernel 23 is used to provide underlying system components and services, such as: power management, memory management, thread management, hardware drivers, etc.; the hardware drivers include Wi-Fi drivers, sensor drivers, positioning module drivers, and the like. The hardware abstraction layer 25 is a package for kernel drivers that provides an interface to the framework 29, masking the implementation details of the lower layers. The hardware abstraction layer 25 runs in user space, while the kernel driver runs in kernel space.

The library and runtime 27, also called a runtime library, provides the executable with the required library files and execution environment at runtime. Library and Runtime 27 includes Android Runtime (ART) 271, library 273, and the like. ART 271 is a virtual machine or virtual machine instance capable of converting the bytecode of an application into machine code. Library 273 is a library that provides support for executable programs at runtime, including browser engines (such as webkit), script execution engines (such as JavaScript engines), graphics processing engines, and the like.

Framework 27 is used to provide various underlying common components and services for applications in application layer 31, such as window management, location management, and the like. The framework 27 may include a phone manager 291, a resource manager 293, a location manager 295, and the like.

The functions of the various components of the operating system 261 described above may be implemented by the application processor 201 executing programs stored in the memory 205.

Those skilled in the art will appreciate that electronic device 100 may include fewer or more components than those shown in fig. 2, and that the electronic device shown in fig. 2 includes only components that are more relevant to the various implementations disclosed in embodiments of the present application.

The electronic device has the capabilities of storing images, encoding image data and the like, and can divide the images into a plurality of slices (Grid) and encode each slice in the process of storing or encoding the images, so that the compression efficiency of the images can be improved, and the encoding performance can be improved.

The common slicing mode can be divided into a frame work layer slicing mode and a slice sinking mode. For example, the original image is a 4032×3024 size high efficiency image file format (high efficiency image file format, HEIF) encoded picture (commonly referred to as Grid): 512×512; in order to avoid the encoder from reading illegal memory, the encoder actually transmits the data to the memory 4032×3024 of the encoder and divides the data into 512×512 Grid, i.e. the memory is allocated to the image, the image data is copied to the memory 4032×3024, and then the encoder reads the data from the memory to perform encoding, which needs a large amount of memory copies to affect the performance and power consumption. The common scheme is to use specific instructions (such as NEON instructions) for data parallel processing, so as to accelerate the copying process. Or a line-by-line and multi-line copying mode is used to replace a pixel-by-pixel copying mode, so that the copying process is accelerated. A parallel mode of slice copying and high efficiency video coding (high efficiency video coding, HEVC) is used, thereby speeding up the end-to-end coding process. However, there are a large number of copies of memory during slicing and encoding, which would introduce additional overhead and would consume additional memory to carry the sliced data, the slicing process overhead being large.

Therefore, the image coding method is provided, when coding is carried out, the address of the storage memory of the input image is directly mapped to the encoder, so that the encoder can directly read data and code based on the mapped address, memory copying is not needed, extra memory bearing slice data is not needed to be allocated, performance and power consumption cost caused by memory copying are reduced, and coding efficiency is improved.

Referring to fig. 3, a flowchart of an image encoding method provided in the present application is as follows.

301. Memory is allocated for the input image.

The input image may be a received image or an image obtained by imaging after being captured by a local camera, and the input image may be stored in a memory for subsequent encoding. The information of the storage memory of the input image may include information such as an address or a length of the storage memory.

Generally, when an electronic device obtains an input image, for example, when the input image is generated or received, a continuous memory may be allocated to the input image, and information of each pixel point in the input image may be stored in the memory. It will be appreciated that the input image may be stored in the memory in an array, for example, when the input image is obtained, a continuous memory is allocated to the input image, and information of the input image is stored in the allocated memory according to the arrangement of pixels. For example, as shown in fig. 4, the input image may be stored in the memory in the form of an array, and information such as the size and address of the memory may be recorded.

Typically, the allocated memory may be used to store information about each pixel of the input image, such as chrominance values, luminance values, and the like. In some scenarios, to avoid the encoder from reading data out of bounds, additional memory may be allocated for the input image.

In particular, the manner in which memory is allocated for the input image may include a variety of ways, and is exemplified below in several possible embodiments.

In one possible implementation, a continuous storage memory may be allocated for the input image based on a preset slice size, and the storage memory may be divided into two parts, for convenience of distinguishing between a first memory for storing information of each pixel point in the input image and a second memory for aligning the storage memory according to the preset slice size, so that the subsequent encoder may read data from the input address in units of the preset slice size.

Optionally, when memory is allocated for an input image, memory may be allocated for the input image based on a preset slice size, where the memory may be understood as two parts, for convenience of distinguishing between a first memory for storing data of the input image, such as a brightness value, a gray value, or a chromaticity value of each pixel in the input image, and a second memory for aligning a size of the memory allocated for the input image according to the preset slice size, so that the memory address of each memory slice may be completely read by the encoder when the memory is sliced according to the preset slice size, and encoding is performed in units of each memory slice.

Optionally, when memory is allocated for the input image, the memory may be allocated according to a preset slice size, where the preset slice size includes a preset height and a preset width, the height of the memory allocated for the input image is aligned according to the preset height, and the width of the memory allocated for the input image is aligned according to the preset width, so that when the memory slice is performed subsequently, the memory slice with a size equal to the preset slice size may be directly obtained by slicing, and therefore, when the subsequent encoder reads the memory address, the boundary crossing is avoided.

Optionally, when allocating memory for the input image, the allocated memory is aligned according to a preset height, and the allocated memory is allocated according to an actually required memory of the input image, that is, the second memory may be divided into a plurality of parts, so as to be convenient for distinguishing a third memory and a fourth memory, where the third memory is combined with the first memory and then arranged according to an array, that is, the height of the memory is aligned with the preset height through the third memory, and a remainder of a last row of the array divided by the preset width is not less than the preset width after being combined with the fourth memory. That is, to reduce the amount of memory allocated, the width of the array may not be aligned according to a preset width, and a section of memory may be allocated more in the last row of the array, so as to avoid subsequent encoder reading out of bounds.

In addition, in the process of distributing the memory for the input image, only the height can be aligned, so that the height of the storage memory is divided by the preset height, and of course, the occupied memory can also be distributed directly according to the data included in the input image, and particularly, the occupied memory can be adjusted according to the actual application scene. In addition, one of the foregoing slicing modes may be pre-deployed in the electronic device, or multiple slicing modes may be pre-deployed. When a plurality of slicing modes are deployed in the electronic equipment, after an input image to be encoded is obtained, one of the plurality of slicing modes can be selected for slicing according to a preset mode, and particularly, the slicing mode can be adjusted according to an actual application scene.

For example, when the available memory of the electronic device is lower than the first threshold, in order to reduce the memory copy amount, when memory is allocated for the input image, the height of the storage memory may be aligned only according to the preset height and the memory is allocated, so as to form an array, and a plurality of bytes are additionally allocated for the last row of the array, so that the remainder of the last row of the array divided by the preset width is not smaller than the preset width after being combined with the additionally allocated plurality of bytes, so as to avoid out-of-bounds of encoder reading; when the available memory of the electronic device is greater than the second threshold but not greater than the third threshold, the electronic device can be aligned according to the preset slice size, namely the height of the storage memory is divided by the preset height, and the width of the storage memory is divided by the preset width, so that the subsequent slice can be performed according to the preset slice size, and the encoder can perform encoding by taking the memory slice as a unit without performing memory copying; when the available memory of the electronic device is greater than the third threshold, the available memory of the electronic device is sufficient, at this time, the array can be selected to be directly segmented, the divided part is divided into a plurality of slices, and the rest part can be encoded by using memory copies during encoding. Therefore, the matched slicing mode can be selected according to the actual application scene, so that the coding mode of the image is matched with the available memory condition of the electronic equipment or the user requirement, the coding efficiency is improved, and the user experience is improved.

302. The storage memory is divided into a plurality of memory slices.

After determining the memory of the input image to be encoded, the input image may be segmented to obtain a plurality of memory slices. The method is equivalent to slicing the storage memory of the input image, so that the storage memory is divided into a plurality of grids, namely memory slices.

Specifically, the storage memory may be segmented according to a preset size, that is, a preset slice size, to obtain a plurality of memory slices (Grid). I.e. it corresponds to slicing the input image, dividing the input image into a plurality of parts so that the subsequent encoder can encode the input image.

The preset slice size may include a size preset by a user, a size negotiated by an upper layer and a lower layer of the electronic device, a size set according to a coding length of the encoder, or a random size, and may be specifically determined according to an actual application scenario.

303. And inputting addresses of the memory slices to an encoder for encoding to obtain encoded data.

After the memory slices are performed, the address of each memory slice is input to an encoder for encoding, thereby obtaining encoded data. When the encoding is performed, the data to be encoded can be extracted from each memory slice based on the input address, so that the data in each memory slice is encoded, and the encoded data is obtained.

The encoder may be a pre-deployed encoder in the electronic device, and may encode according to a pre-set encoding rule. For example, a code may be deployed and run in an electronic device, and used to read data from an address input to an encoder, and encode an image according to a preset encoding mode, where the encoding mode may be an encoding mode such as HEVC encoding or advanced video coding (advanced video coding, AVC), and the like, and specifically may be adjusted according to an actual application scenario.

It can be understood that Grid is a coding unit of an encoder, the encoder encodes data stored in a memory of one Grid, and a memory address corresponding to each Grid can be mapped to the encoder, so that the encoder can obtain memory information of the Grid, including width, height, stride, and the like.

Therefore, in the embodiment of the application, the address of the data to be encoded can be directly input to the encoder, so that the encoder can directly extract the data to be encoded based on the address, the memory overhead for copying the memory can be reduced, and the encoding efficiency can be improved.

In one possible implementation, if the storage memory is not divided by the preset slice size, the storage memory is sliced to obtain a plurality of memory slices and a first slice, where the first slice is a portion of the storage memory that is remained after slicing according to the preset slice size. The addresses of the plurality of memory slices may then be mapped to an encoder for encoding, and the first data may be copied from the addresses corresponding to the first slice and used as input to the encoder to obtain encoded data.

Therefore, in the embodiment of the application, when the memory of the input image is not divided by the preset slice size, the obtained address of the memory matched with the preset slice size can be mapped to the encoder for encoding, and the data is copied from the divided part and used as the input of the encoder, so that the final encoded data is obtained, all memories in the memory are not required to be copied, the memory copy amount is reduced, the memory cost for performing memory copy can be reduced, and the encoding efficiency can be improved.

In a possible implementation manner, if the memory is not aligned completely according to the preset slice size when the memory is allocated for the input image, for example, only the height is aligned and the width is not aligned, or both the height and the width are not aligned, the memory may be sliced according to the preset slice size when the memory is sliced. The obtained memory slices can then be divided into two types, which are convenient for distinguishing between a first memory slice and a second memory slice, wherein the first memory slice has a preset height, the second memory slice has a height smaller than the preset height, or the second memory slice is the last slice of the last line, and the first memory slice and the second memory slice are different memory slices, i.e. the same memory type is one of the first memory slice or the second memory slice.

And a fifth memory can be allocated for the second memory slice, the data in the second memory is copied into the fifth memory, the width of the fifth memory is divided by the preset width, the height of the fifth memory is divided by the preset height, and the data stored in the second memory slice is copied into the fifth memory. When encoding is performed, the addresses of the first memory slice and the fifth memory slice can be input to the encoder, so that the encoder can read data from the input addresses and encode the data, final encoded data is obtained, and the condition that the encoder reads out of range is avoided.

For example, if the height of the storage memory is divided by the preset height and the width of the storage memory is not divided by the preset width, the memory slice of the last column and the last column may be used as the second memory slice, and the rest of the memory slices are divided into the first memory slices. And allocating a fifth memory for the second memory slice, wherein the size of the fifth memory can be a preset slice size, and copying the data stored in the second memory slice into the fifth memory. And then inputting the addresses of the first memory slice and the fifth memory slice to the encoder so that the encoder reads the data from the input addresses and encodes the data to obtain final encoded data.

For another example, if the height of the storage memory is not divided by the preset height and the width of the storage memory is not divided by the preset width, the portion of the storage memory whose height is not divided by the preset height, that is, the memory slice corresponding to the last column in the storage memory may be used as the second memory slice. And allocating a fifth memory for the second memory slice, and copying the data stored in the second memory slice into the fifth memory. And then inputting the addresses of the first memory slice and the fifth memory to the encoder so that the encoder reads the data from the input addresses and encodes the data to obtain final encoded data, thereby avoiding the condition of out-of-limit reading of the encoder.

The foregoing describes a method flow provided by the present application, and for ease of understanding, the following exemplary description is provided in connection with a specific application scenario.

First, taking a specific application scenario as an example, a partial system architecture of an electronic device adapted to the specific application scenario may be shown in fig. 5. The system architecture can be based on a MediaCodec/OMX FrameWork and an HEVC encoder, and can comprise multiple layers, such as an application layer, a frame work layer, a HAL/vendor layer and the like, wherein an APP can be installed in the application layer, and the APP can trigger the encoder to encode.

Some APP capable of obtaining an input image, such as a camera or communication software, may be installed in the electronic device, where the APP capable of generating or receiving an image, specifically, for example, the camera may be used to capture an image, and trigger a step of saving the image; the communication software may receive images sent by other electronic devices, trigger steps to save the images, and so on.

HEIF coding: in Android FrameWork, heifwriters and HEIFEncoder, HEIFWriter have been implemented to provide an interface for an application layer (APK) for the application layer to input raw picture data, the heifwriters may call the interface of the HEIFEncoder, and the heifwriters are used to complete the encapsulation of the file, generating the HEIC file; the heitencoder may invoke a MediaCodec interface for creating the HEIC encoder, enabling HEIF encoding.

MediaCodec is a class used for encoding and decoding audio and video, and functions of encoding and decoding are realized by accessing the codec of the bottom layer. Is part of the media (media) infrastructure of the electronic device.

OMX, alternatively referred to as OpenMAX (Open Media Acceleration), is an open cross-platform media framework that can be used to deliver Usage (i.e., identification) of Input buffers (i.e., incoming memory information).

The HEIC encoder, as an OMX IL (OpenMAX Integration Layer, interface between OMX framework layer and component layer) layer, performs interfacing with the OMX framework, and in this embodiment, performs the core function of HEIF slicing.

Gralloc (Graphic Buffer Allocator) is a HAL layer module responsible for applying and releasing Graphic Buffer in Android, and is used for performing memory allocation of the Graphic Buffer, wherein the optimized function points are as follows: after identifying the specific Usage attribute of the HEIC code, the memory size is aligned based on the Grid size.

HEVC encoder: the input is the memory information of each Grid obtained after the HEIC encoder is sliced, such as the information of the width of the picture corresponding to the Grid, the height of the picture corresponding to the Grid, the stride and the like, and is used for reading data from the input Grid memory information and carrying out HEVC encoding on the data in each Grid respectively.

Specifically, the process of encoding an image may be as shown in fig. 6.

601. HEIC encoder set identification (use)

First, a user, which is an identification for identifying whether the coding type of the inputted image is the HEIC code, is set by the HEIC encoder.

Such as the HEIC encoder setting a specific attribute to the Input Buffer, such as identifying by graphic Buffer usage whether to slice and encode in the manner provided herein. It will be appreciated that in the process where the HEIC encoder module can negotiate the Buffer attribute with OMX, a specific graphic Buffer usage is added to identify the slice pre-alignment attribute of the HEIC encoded slice scene, i.e., the slice is aligned and sliced in that manner. Such as which mode is selected from the following slicing modes of step 603 to slice.

602. OMX delivers usage to Gralloc

And then, before the OMX module initiates the application of the graphic buffer memory, the OMX can read graphic buffer usage, and after identifying which type of use is identified, the current HEIC coding scene can be obtained. At this time, a new user may be set, which needs to be globally unique to identify the HEIC encoding scene, as an attribute of the Input Buffer, and may be identified by the Gralloc, or directly transferred graphic Buffer usage to the Gralloc, so that the Gralloc identifies that the HEIC encoding scene is currently identified.

603. Gralloc allocates memory based on usage

One or more slicing modes can be deployed in advance, and after the Gralloc obtains the usage, the current HEIC encoding scene can be identified, and corresponding memory is allocated.

When only one slicing mode is deployed, after the Gralloc obtains the usage, the current HEIC coding scene can be identified, and then memory allocation is performed.

When multiple slicing modes are deployed, after the Gralloc obtains the usages, it can identify which mode to use for slicing based on the usages, and then allocate the corresponding memories.

Generally, when there are multiple slicing modes, the memories required to be allocated by each slicing mode may be the same or different, and the matched slicing mode may be selected according to the actual application scenario, for example, when the available memory of the electronic device is sufficient, one of the slicing modes may be selected randomly, when the available memory of the electronic device is insufficient, the slicing mode consuming the least memory may be selected, or when the requirement on the coding efficiency is higher, the slicing mode consuming less memory may be selected, and the adjustment may be specifically performed according to the actual application scenario.

604. HEIC encoder slicing

After the Gralloc allocates the memory based on the usage, the information of the allocated memory can be transmitted to the HEIC encoder, the HEIC encoder performs slicing, and the information of each slice obtained after slicing is transmitted to the HEVC encoder, so that the HEVC encoder reads data from the slices and encodes the data.

In slicing, taking the Android system as an example, slices may be sliced by the frame work layer (or application layer slice) or by the encoder (commonly referred to as slice sinking).

If sliced by the frame work layer, the HEVC encoder is created by the upper layers: the upper layer may negotiate a slice size through the Mediacodec/OMX and the lower layer, or set a slice size in advance, and then slice the data based on the slice size by the upper layer, the address of each slice is transferred to the encoder through the Mediacodec/OMX, and the encoder extracts the data to be encoded based on the incoming address and encodes the data. The encoded data can be carried by the Output Buffer and delivered to the upper layer. The upper layer generates and feeds back end of stream (EOS) to indicate that encoding is completed, and after receiving encoded data of all slices of the image, the upper layer can package the encoded data into an HEIC file.

If the encoder is used for slicing, the HEIC encoder is created by the upper layer, the upper layer can negotiate the slice size through the Medicacodec/OMX and the lower layer, or preset the slice size, then the upper layer transmits the image to the lower layer, the encoder is used for slicing the image and finishing encoding, after the last slice is finished encoding, the EOS is reported, and after the upper layer receives the encoded data of all slices of the image, the HEIC file can be packaged.

The upper layer and the lower layer are relative concepts, for example, a frame work layer or a layer above the frame work layer may be understood as an upper layer, and a layer below the frame work layer may be referred to as a lower layer, which may be specifically divided according to an actual application scenario, which is only illustrative and not limiting.

For example, the input image may be split into multiple parts with the same size, that is, the storage memory corresponding to the input image is split into multiple Grid with the same size, and then the relevant parameters are configured as the input of the HEVC encoder. Illustratively, when slicing is performed, as shown in fig. 7, the width of the allocated memory is called stride, and the Height of the allocated memory is called Height; the width of each Grid is called Grid width, and the height of each Grid is called Grid height, and the Grid width is understood as the preset slice size.

In combination with the foregoing step 603 and step 604, in the method provided in the present application, memory may be allocated for the input image and sliced in a variety of ways, which are described below by way of example.

Mode one, allocating stride according to Grid width

When the memory is allocated, the stride of the memory may be aligned according to the Grid width, which may be understood that the stride of the memory may be divided by the Grid width, and the Height of the memory may be aligned according to the Grid Height.

In general, the memory size occupied by data in an input image may not be divided by the preset slice size, and the size of each Grid generally needs to be kept uniform.

As shown in fig. 8, the size of the memory occupied by the data in the Input image is not divided by the size of the Grid, when the memory is allocated to the Input Buffer, the strips allocated to the memory are aligned according to the Grid width, that is, the memory can be allocated to the last column of Grid and the last row of Grid, and the memory information (including the memory address allocated to the data included in the Input image and the address of the memory allocated additionally) of each Grid is transferred to the encoder, so that when the encoder reads the memory, the encoder can read the data from the memory information corresponding to each Grid, and avoid program crash or the encoder cannot work normally due to illegal memory reading. And the encoder can directly read the input image from the input address without performing memory copying, thereby reducing the memory copying process, reducing the memory overhead and improving the coding efficiency.

Taking an input image with a resolution of 4032×3024 as an example, if slicing is performed in some common slicing manners, for example, slicing is performed by using a Grid with a resolution of 512×512, a large amount of memory copies are required during slicing, which affects performance and power consumption, and additional memory needs to be allocated to carry Grid data. If 48 Grid copies are needed, each Grid memory is 512×512×4=1m Bytes (512 copies are needed for each Grid 512×4 Bytes). By the memory allocation and slicing method provided by the application, extra memory copying is not needed, extra performance and power consumption expenditure are eliminated, and extra memory is not needed to be allocated to bear Grid data.

Mode two, multiple allocation of N bytes

In general, the encoder may encode the Grid, and the memory of the input image is usually a continuous memory, so the encoder may read the data of each Grid according to the start address of each Grid, in the case of encoding based on the memory map, when the last Grid of the last row is read, the portion exceeding the size of the Grid may be read from the address of the next row, so as to read the content of the complete one Grid, and then, when the image is restored, the redundant portion in the last row of Grid may be removed. When the address of the last Grid of the last row is read, if the read address exceeds the Grid range, illegal memory may be read, so that the encoder cannot work normally or the encoding process of the encoder is affected.

Therefore, N bytes can be allocated more for the last Grid, that is, the width of the last row of the last Grid is Grid width, so that the encoder can read the data of a complete Grid, and illegal memory can be avoided, and the encoder can generate encoding errors or influence the encoding process of the encoder.

For example, as shown in fig. 9, when the Input Buffer is used to allocate memory, the heights of the allocated memory are aligned according to the Grid Height, and the Stride does not perform Grid width alignment processing; on this basis, N bytes of memory are allocated. Taking an image in an RGBA format as an example, N is not less than ((Grid width) - (picture width%) 4. The obtained N value is the minimum value which ensures that the encoder does not cross the boundary when reading the memory, thereby avoiding reading the illegal memory, and further enabling the encoder to generate encoding errors or influencing the encoding process of the encoder, and the like.

It can be understood that when the Input Buffer allocates the memory, the Height is aligned according to the size of the Grid, the Stride is valued according to the width of the storage memory (or conventionally, the size is aligned according to 16 bytes, 32 bytes or 64 bytes, the specific number is determined by the system), so that the problem of insufficient memory exists when the Grid in the lower right corner of fig. 9 is mapped to the encoder, therefore, N bytes of memory can be allocated more, so as to avoid reading illegal memory, and thus the encoder generates encoding errors or affects the encoding process of the encoder.

Taking an input image with 4032×3024 resolution as an example, the input image may be split into Grid with 512×512, and when splitting, a large amount of memory copies are needed, which affects performance and power consumption, and additional memory needs to be allocated to carry Grid data. If 48 Grid copies are needed, each Grid memory is 512×512×4=1m Bytes (512 copies are needed for each Grid 512×4 Bytes). By means of the slicing mode provided by the method, extra memory copying is not needed, extra performance and power consumption expenditure are eliminated, and extra memory is not needed to be allocated to bear Grid data. When HEIF is sliced, the last row of Grid does not need additional memory copy, so all Grid do not need memory copy. Performance and power consumption are optimized, and no additional memory is required to be allocated to carry Grid data.

Mode three, part adopts memory address mapping, and the rest adopts memory copy

The addresses of the portions of the input image that are divisible by the size of Grid may be mapped into the encoder, while the remaining portions may be input into the encoder by way of a memory copy.

The memory occupied by the data of the input image may be divided into various cases, such as height divided by Grid height, or height not divided by Grid height.

For example, as shown in fig. 10, if the memory height occupied by the data of the input image is divided by the Grid height, the storage memory may be allocated according to the actually required memory of the input image, and the storage memory may be divided into a first memory slice and a second memory slice, where the second memory slice is the last memory slice of the last line, and the width is not divided by the Grid width, and the rest is the first memory slice as shown in fig. 10. In order to avoid the encoder from crossing the boundary when reading the last memory slice of the last line (i.e., the second memory slice), the last slice of the last line may be memory copied, i.e., an additional memory (i.e., a fifth memory) is allocated for the last memory slice, and then the data in the last slice is copied to the additional allocated memory. And then taking the address of the first memory slice and the address of the fifth memory slice as the input of the encoder.

The memory of the input image can be segmented according to the preset Grid size, the memory of the divided part is transmitted to the encoder in a memory address mapping mode, the rest of the non-divided part can be allocated with additional memory, and the data in the non-divided part of the memory is transmitted to the encoder in a memory copying mode.

It will be understood that when mapping each Grid address to the encoder, the lower right corner Grid as shown in fig. 10 has a problem of insufficient memory, so when slicing the lower right corner Grid, memory copying may be performed, that is, memory is additionally allocated to carry data in the one Grid, so as to avoid reading illegal memory, thereby causing the encoder to generate encoding errors or affecting the encoding process of the encoder. For another example, as shown in fig. 11, if the memory occupied by the data of the input image is not divided by the Grid height, when allocating the memory for the input image, the allocated memory height may be aligned with the Grid height, that is, the allocated memory height is divided by the Grid height. The method for dividing the allocated storage memory may refer to fig. 10, and will not be described herein.

For example, as shown in fig. 12, if the memory height occupied by the data of the input image is not exactly divided by the Grid height, no additional memory may be allocated to the input image, and the storage memory may be allocated according to the actual size of the input image. Then, the storage memory is directly divided according to the Grid size, the obtained memory slice can be divided into a first memory slice and a second memory slice, wherein the first memory slice is a slice with the height of Grid, and the second memory slice is a slice with the height smaller than the height of Grid. Then, additional memory (i.e., a fifth memory) is allocated for the second memory slice, and then the data in the second memory slice is copied to the additional allocated memory. And then taking the address of the first memory slice and the address of the fifth memory slice as the input of the encoder.

Therefore, in the embodiment of the application, the divided part in the storage memory can be transmitted into the encoder in an address mapping mode, and only the memory is required to be allocated for the part which is not divided, so that the memory copy quantity is reduced, the memory overhead is reduced, and the coding efficiency is improved.

605. HEVC encoder coding

After the HEVC encoder receives the configuration information of each Grid, such as the information of the start address, the length, etc. of each Grid, HEVC encoding can be performed. The configuration information may include information such as a start address, a width, or a length of each Grid, so that an encoder may read and encode data in each Grid.

For example, as for each Grid, the received configuration information is as follows:

start = Grid memory Start address;

stride = Input Buffer Stride;

Width＝Grid width；

Height＝Grid height

wherein, the Stride represents the Width of the memory, the Width represents the Width of each Grid, and the Height represents the Height of each Grid.

For example, taking an image with a frame resolution of 4032×3024 as an example, encoding is performed by means of memory copy and the memory address mapping provided in the present application, and comparing by calculating encoding time consumption. The time spent for the HEIC encoding = the time when the HEIC completes encoding (all Grid completed HEVC encoding, reported EOS) -the time when the HEIC starts encoding (the time when the HEIC encoder received the original image). The time consumption is more than 80ms in a memory copying mode, and the minimum time is only 45ms in the coding mode provided by the method, so that the coding efficiency is greatly improved. Of course, the above is based on a certain chip test, and different hardware time-consuming data may be different.

Therefore, in the embodiment of the application, the memory of the image can be segmented, and the Grid address obtained by segmentation is mapped into the encoder, so that the memory additionally allocated can be reduced, the memory overhead is reduced, and the encoding efficiency is improved. Further, in order to avoid the encoder from reading the illegal memory address during encoding, a certain memory may be allocated in various manners, so that the encoder may be prevented from reading the illegal memory, thereby causing an encoding error to occur or affecting the encoding process of the encoder.

The foregoing describes the flow of the method provided by the present application, and the following describes the apparatus provided by the present application.

Referring to fig. 13, a schematic structural diagram of an image encoding device is provided, and the image encoding device is used for executing the method steps corresponding to fig. 3-12. The image encoding device includes:

an allocation module 1301, configured to allocate a storage memory for an input image;

a dividing module 1302 for dividing the storage memory into a plurality of memory slices;

the encoding module 1303 is configured to input an address of at least one memory slice of the plurality of memory slices to an encoder, where the encoder is configured to read data based on the input address and encode the data to obtain encoded data.

In one possible implementation, the dividing module 1302 is specifically configured to divide the storage memory into a plurality of memory slices according to a preset slice size, where the preset slice size includes a preset height and a preset width.

In one possible implementation, the partitioning module 1302 is specifically configured to: and allocating storage memory for the input image based on a preset slice size.

the allocation module 1301 is further configured to allocate a fifth memory for a second memory slice in the plurality of memory slices, copy data in the second memory to the fifth memory, divide a width of the fifth memory by a preset width, and divide a height of the fifth memory by a preset height;

the encoding module 1303 is specifically configured to input an address of a first memory slice and an address of a fifth memory slice of the plurality of memory slices to the encoder.

Referring to fig. 14, another schematic structural diagram of an electronic device provided in the present application is described below.

The electronic device may include the aforementioned wearable device, terminal, vehicle, or the like, and may include a processor 1401, a memory 1402, and a transceiver 1403. The processor 1401 and memory 1402 are interconnected by wires. Wherein program instructions and data are stored in memory 1402.

The memory 1402 stores program instructions and data corresponding to the steps of fig. 3 to 12.

The processor 1401 is configured to perform the method steps performed by the first device or the electronic device as described in any of the embodiments of fig. 3-12.

A transceiver 1403 for performing the steps of receiving or transmitting data performed by the first device or the electronic device as described in any of the embodiments of fig. 3-12.

There is also provided in an embodiment of the present application a computer-readable storage medium having stored therein a program for generating a vehicle running speed, which when run on a computer, causes the computer to perform the steps in the method described in the embodiments shown in the foregoing fig. 3-12.

Alternatively, the aforementioned electronic device shown in fig. 14 is a chip.

The embodiment of the application also provides an electronic device, which may also be called a digital processing chip or a chip, where the chip includes a processing unit and a communication interface, where the processing unit obtains program instructions through the communication interface, where the program instructions are executed by the processing unit, and where the processing unit is configured to execute the method steps executed by the electronic device shown in any of the foregoing embodiments of fig. 3-12.

The embodiment of the application also provides a digital processing chip. The digital processing chip has integrated therein circuitry and one or more interfaces for implementing the above-described processor 1401, or the functions of the processor 1401. When the memory is integrated into the digital processing chip, the digital processing chip may perform the method steps of any one or more of the preceding embodiments. When the digital processing chip is not integrated with the memory, the digital processing chip can be connected with the external memory through the communication interface. The digital processing chip implements the actions executed by the electronic device in the above embodiment according to the program codes stored in the external memory.

Embodiments of the present application also provide a computer program product which, when run on a computer, causes the computer to perform the steps performed by an electronic device in a method as described in the embodiments of fig. 3-12 above.

The electronic device provided in this embodiment of the present application may be a chip, where the chip includes: a processing unit, which may be, for example, a processor, and a communication unit, which may be, for example, an input/output interface, pins or circuitry, etc. The processing unit may execute the computer-executable instructions stored in the storage unit, so that the chip in the server performs the device search method described in the embodiment shown in fig. 3 to 12. Optionally, the storage unit is a storage unit in the chip, such as a register, a cache, etc., and the storage unit may also be a storage unit in the wireless access device side located outside the chip, such as a read-only memory (ROM) or other type of static storage device that may store static information and instructions, a random access memory (random access memory, RAM), etc.

In particular, the aforementioned processing unit or processor may be a central processing unit (central processing unit, CPU), a Network Processor (NPU), a graphics processor (graphics processing unit, GPU), a digital signal processor (digital signal processor, DSP), an application specific integrated circuit (application specific integrated circuit, ASIC) or field programmable gate array (field programmable gate array, FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, or the like. The general purpose processor may be a microprocessor or may be any conventional processor or the like.

The processor referred to in any of the foregoing may be a general purpose central processing unit, a microprocessor, an ASIC, or one or more integrated circuits for controlling the execution of the programs of the methods of fig. 3-12 described above.

It should be further noted that the above-described apparatus embodiments are merely illustrative, and that the units described as separate units may or may not be physically separate, and that units shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. In addition, in the drawings of the embodiment of the device provided by the application, the connection relation between the modules represents that the modules have communication connection therebetween, and can be specifically implemented as one or more communication buses or signal lines.

From the above description of the embodiments, it will be apparent to those skilled in the art that the present application may be implemented by means of software plus necessary general purpose hardware, or of course may be implemented by dedicated hardware including application specific integrated circuits, dedicated CPUs, dedicated memories, dedicated components and the like. Generally, functions performed by computer programs can be easily implemented by corresponding hardware, and specific hardware structures for implementing the same functions can be varied, such as analog circuits, digital circuits, or dedicated circuits. However, a software program implementation is a preferred embodiment in many cases for the present application. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a readable storage medium, such as a floppy disk, a U-disk, a removable hard disk, a Read Only Memory (ROM), a random access memory (random access memory, RAM), a magnetic disk or an optical disk of a computer, etc., including several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to execute the method described in the embodiments of the present application.

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product.

The computer program product includes one or more computer instructions. When loaded and executed on a computer, produces a flow or function in accordance with embodiments of the present application, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be stored by a computer or a data storage device such as a server, data center, etc. that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a Solid State Disk (SSD)), or the like.

The terms "first," "second," "third," "fourth" and the like in the description and in the claims of this application and in the above-described figures, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments described herein may be implemented in other sequences than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Finally, it should be noted that: the foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes or substitutions are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. An image encoding method, comprising:

memory is allocated for the input image;

dividing the storage memory into a plurality of memory slices;

and reading data from the address of at least one memory slice in the plurality of memory slices through an encoder and encoding to obtain encoded data.

2. The method of claim 1, wherein dividing the storage memory into a plurality of memory slice storage memories comprises:

dividing the storage memory into a plurality of memory slices according to a preset slice size, wherein the preset slice size comprises a preset height and a preset width.

3. The method of claim 2, wherein allocating storage memory for the input image comprises:

and distributing the storage memory for the input image based on the preset slice size.

4. A method according to claim 3, wherein the storage memory includes a first memory and a second memory, the first memory storing information of each pixel in the input image, and the second memory being configured to align the size of the storage memory according to the preset slice size, so that the encoder reads data from the input address in units of the preset slice size.

5. The method of claim 4, wherein the memory cells are arranged in an array, the width of the memory cells being divided by the predetermined width, the height of the memory cells being divided by the predetermined height.

6. The method of claim 4, wherein the second memory comprises a third memory and a fourth memory, the first memory and the third memory are arranged in an array after being combined, the height of the array is divided by the preset height, and the remainder of the last row of the array divided by the preset width is not less than the preset width after being combined with the fourth memory.

7. A method according to claim 2 or 3, wherein the memory cells are arranged in an array, the plurality of memory slices are divided into a first memory slice and a second memory slice, the first memory slice has a height that is the preset height, the second memory slice has a height that is less than the preset height or the second memory slice is the last slice of the last row in the array of the plurality of memory slices, and the first memory slice and the second memory slice are different memory slices;

The method further comprises the steps of:

a fifth memory is allocated for a second memory slice in the memory slices, data in the second memory is copied into the fifth memory, the width of the fifth memory is divided by the preset width, and the height of the fifth memory is divided by the preset height;

the step of reading data from the address of at least one memory slice in the plurality of memory slices and encoding the data by an encoder to obtain the encoded data includes:

and reading data from the address of the first memory slice and the address of the fifth memory in the memory slices through an encoder, and encoding to obtain the encoded data.

8. The method of claim 7, wherein the height of the storage memory is divided by the predetermined height.

9. An image encoding device, comprising:

and the encoding module is used for reading data from the address of at least one memory slice in the plurality of memory slices through the encoder and encoding the data to obtain encoded data.

10. The apparatus of claim 9, wherein the device comprises a plurality of sensors,

the dividing module is specifically configured to divide the storage memory into the plurality of memory slices according to a preset slice size, where the preset slice size includes a preset height and a preset width.

11. The apparatus according to claim 10, wherein the dividing module is specifically configured to: and distributing the storage memory for the input image based on the preset slice size.

12. The apparatus of claim 11, wherein the device comprises a plurality of sensors,

the storage memory comprises a first memory and a second memory, the first memory stores information of each pixel point in the input image, and the second memory is used for enabling the size of the storage memory to be aligned according to the preset slice size, so that the encoder can read data from an input address by taking the preset slice size as a unit.

13. The apparatus of claim 12, wherein the memory cells are arranged in an array, a width of the memory cells being divided by the predetermined width, a height of the memory cells being divided by the predetermined height.

14. The apparatus of claim 12, wherein the second memory comprises a third memory and a fourth memory, the first memory and the third memory are arranged in an array after being combined, the height of the array is divided by the preset height, and the remainder of the last row of the array divided by the preset width is not less than the preset width after being combined with the fourth memory.

15. The apparatus of claim 10 or 11, wherein the plurality of memory slices are divided into a first memory slice and a second memory slice, the first memory slice having a height that is the preset height, the second memory slice having a height that is less than the preset height or the second memory slice being a last slice of a last row in an array of the plurality of memory slices, the first memory slice and the second memory slice being different memory slices;

the allocation module is further configured to allocate a fifth memory for a second memory slice in the plurality of memory slices, and copy data in the second memory to the fifth memory, where a width of the fifth memory is divided by the preset width, and a height of the fifth memory is divided by the preset height;

the encoding module is specifically configured to read and encode data from an address of a first memory slice and an address of the fifth memory among the plurality of memory slices through an encoder, so as to obtain the encoded data.

16. The apparatus of claim 15, wherein the height of the storage memory is divided by the predetermined height.

17. An electronic device comprising one or more processors coupled to a memory, the memory storing a program that when executed by the one or more processors, performs the steps of the method of any of claims 1-8.

18. A computer readable storage medium comprising a program which, when executed by a processing unit, performs the method of any of claims 1 to 8.

19. A computer program product comprising computer programs/instructions which, when executed by a processor, implement the steps of the method of any of claims 1 to 8.

20. A chip, characterized in that it comprises a processing unit and a communication interface, the processing unit obtaining program instructions via the communication interface, the program instructions being executed by the processing unit, the processing unit being adapted to perform the steps of the method according to any of claims 1 to 8.