CN116417454A - High-voltage electrostatic protection structure, forming method thereof and d-TOF device - Google Patents

High-voltage electrostatic protection structure, forming method thereof and d-TOF device Download PDF

Info

Publication number
CN116417454A
CN116417454A CN202111678107.8A CN202111678107A CN116417454A CN 116417454 A CN116417454 A CN 116417454A CN 202111678107 A CN202111678107 A CN 202111678107A CN 116417454 A CN116417454 A CN 116417454A
Authority
CN
China
Prior art keywords
doped region
region
diode structure
doping
diode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202111678107.8A
Other languages
Chinese (zh)
Inventor
张斯日古楞
阎大勇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp, Semiconductor Manufacturing International Beijing Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN202111678107.8A priority Critical patent/CN116417454A/en
Publication of CN116417454A publication Critical patent/CN116417454A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The application provides a high-voltage electrostatic protection structure, a forming method thereof and a d-TOF device, wherein the high-voltage electrostatic protection structure comprises: a logic wafer having a first diode structure disposed therein, the first diode structure being in electrical communication at a first threshold voltage; a pixel wafer, in which a second diode structure is arranged, and is connected in series with the first diode structure, and the second diode structure is electrically connected under a second threshold voltage; the first end of the second diode structure is electrically connected with the high-voltage power supply end of the d-TOF device, the second end of the second diode structure is electrically connected with the first end of the first diode structure, and the second end of the first diode structure is electrically connected with the ground end of the d-TOF device. The high-voltage electrostatic protection structure can protect d-TOF devices from being damaged in the packaging or wire bonding process and under the condition of unstable voltage or in the power-on process of high-voltage power supply.

Description

High-voltage electrostatic protection structure, forming method thereof and d-TOF device
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a high-voltage electrostatic protection structure, a method for forming the same, and a d-TOF device.
Background
Single photon detection avalanche diodes (single photon avalanche diode, SPAD) are the only solution currently implemented for direct time of flight sensing devices (direct time of fly, d-TOF). Single photon applications require SPADs to operate in geiger mode, so SPAD arrays typically require a common terminal to connect to a high voltage power supply.
With the growing demand for 3D imaging in the areas of autopilot, AR/VR, etc., technologies for SPAD arrays and time to digital converter (time to digital circuit, TDC) circuits to implement D-TOF sensing through 3D stacking have matured day by day, and mass production will be achieved in the near future.
However, a problem existing at present is that the high-voltage power supply connected with the public terminal can cause instant high-voltage impact on the SPAD array in the power-on process or under the condition of unstable voltage. This also occurs during chip packaging and routing. Such transient high voltage pulses may cause some damage to the SPAD device itself, and more seriously, may cause serious physical damage to the low voltage logic (mainly the TDC) circuit connected in series with the other end of the SPAD. How to realize high-voltage electrostatic protection in the SPAD array becomes the most urgent problem to be solved for realizing mass production of d-TOF chips in the future.
Therefore, there is a need to provide a more efficient and reliable solution.
Disclosure of Invention
The application provides a high-voltage electrostatic protection structure, a forming method thereof and a d-TOF device, which can protect the d-TOF device from being damaged in the packaging or wire bonding process and under the condition of power-on process or unstable voltage of a high-voltage power supply.
One aspect of the present application provides a high voltage electrostatic protection structure, comprising: a logic wafer having a first diode structure disposed therein, the first diode structure being in electrical communication at a first threshold voltage; a pixel wafer, in which a second diode structure is arranged, and is connected in series with the first diode structure, and the second diode structure is electrically connected under a second threshold voltage; the logic wafer is bonded with the pixel wafer, the first end of the second diode structure is electrically connected with the high-voltage power supply end of the d-TOF device, the second end of the second diode structure is electrically connected with the first end of the first diode structure, and the second end of the first diode structure is electrically connected with the ground end of the d-TOF device.
In some embodiments of the present application, the logic wafer comprises: the first substrate is provided with a well region, the surface of the well region is also provided with a first doped region and a second doped region, and the first doped region, the second doped region and the well region form the first diode structure; the first dielectric layer is positioned on the surface of the first substrate, and a first metal connecting structure and a second metal connecting structure which penetrate through the first dielectric layer and are respectively and electrically connected with the first doping region and the second doping region are arranged in the first dielectric layer.
In some embodiments of the present application, at least one of the first doped region and the second doped region is of opposite doping type to the well region, the first doped region and the second doped region being in electrical communication at the first threshold voltage.
In some embodiments of the present application, the first threshold voltage is 5 to 15V.
In some embodiments of the present application, the pixel wafer includes: the second substrate is provided with a buried well region, a third doped region and a fourth doped region are arranged in the buried well region, and the third doped region, the fourth doped region and the buried well region form the second diode structure; the second dielectric layer is positioned on the surface of the second substrate, and a third metal connecting structure which is electrically connected with the first doped region and the fourth doped region is arranged in the second dielectric layer.
In some embodiments of the present application, the pixel wafer further includes: the first through silicon via structure is positioned at one side of the buried well region, penetrates through the second substrate and extends into the second dielectric layer, and is electrically connected with the third doping region and the high-voltage power end of the d-TOF device; and the second silicon through hole structure is positioned at the other side of the buried well region, penetrates through the second substrate and extends into the second dielectric layer, and is electrically connected with the second doping region and the grounding end of the d-TOF device.
In some embodiments of the present application, the doping types of the third doped region and the fourth doped region are opposite, one of the third doped region and the fourth doped region is the same doping type as the buried well region, and the third doped region and the fourth doped region are in electrical communication at the second threshold voltage.
In some embodiments of the present application, the second threshold voltage is 20 to 60V.
In some embodiments of the present application, the doping concentration of the third doped region and the fourth doped region is 5e16 to 1e18 atoms/cm 3 。
In some embodiments of the present application, the doping type of the third doped region and the fourth doped region is the same, and the doping type of the third doped region and the fourth doped region is opposite to the doping type of the buried well region.
In some embodiments of the present application, a fifth doped region is further disposed on two sides of the third doped region and the fourth doped region, and the doping types of the fifth doped region and the third doped region are opposite.
In some embodiments of the present application, the third doped region and the fourth doped region have a spacing of 0.4 to 2 microns.
In some embodiments of the present application, the bonding manner of the logic wafer and the pixel wafer is hybrid bonding.
Another aspect of the present application provides a method for forming a high voltage electrostatic protection structure as described above, including: providing a logic wafer, wherein a first diode structure is arranged in the logic wafer, and the first diode structure is electrically communicated under a first threshold voltage; providing a pixel wafer, wherein a second diode structure is arranged in the pixel wafer and is connected in series with the first diode structure, and the second diode structure is electrically communicated under a second threshold voltage; and bonding the logic wafer and the pixel wafer, wherein a first end of the second diode structure is electrically connected with a high-voltage power supply end of the d-TOF device, a second end of the second diode structure is electrically connected with a first end of the first diode structure, and a second end of the first diode structure is electrically connected with a ground end of the d-TOF device.
Another aspect of the present application also provides a d-TOF device comprising: a high voltage power supply; a single photon avalanche diode connected with the high voltage power supply; one end of the time-to-digital converter is connected with the single photon avalanche diode, and the other end of the time-to-digital converter is connected with a detection voltage; one end of the reset circuit is connected with the single photon avalanche diode, and the other end of the reset circuit is connected with the working voltage; one end of the quenching circuit is connected with the single photon avalanche diode, and the other end of the quenching circuit is grounded; the high-voltage electrostatic protection structure according to the above, wherein the first end of the second diode structure is connected to the high-voltage power supply, and the second end of the first diode structure is grounded, and when the voltage of the high-voltage power supply is greater than or equal to the sum of the first threshold voltage and the second threshold voltage, the high-voltage electrostatic protection structure is electrically connected to the high-voltage power supply and the ground.
The application provides a high-voltage electrostatic protection structure, a forming method thereof and a d-TOF device, wherein the high-voltage electrostatic protection structure comprises two diodes which are connected in series, and the diodes can be electrically connected under a certain threshold voltage so as to ground a high-voltage power supply, thereby avoiding the damage to the d-TOF device in the packaging or wire bonding process and under the condition of the power-on process or unstable voltage of the high-voltage power supply.
Drawings
The following figures describe in detail exemplary embodiments disclosed in the present application. Wherein like reference numerals refer to like structure throughout the several views of the drawings. Those of ordinary skill in the art will understand that these embodiments are non-limiting, exemplary embodiments, and that the drawings are for illustration and description purposes only and are not intended to limit the scope of the present application, other embodiments may equally well accomplish the intent of the invention in this application. It should be understood that the drawings are not to scale. Wherein:
fig. 1 to 8 are schematic structural diagrams illustrating steps in a method for forming a high-voltage electrostatic protection structure according to an embodiment of the present application;
fig. 9 is a schematic structural diagram of a d-TOF device according to an embodiment of the present application.
Detailed Description
The following description provides specific applications and requirements to enable any person skilled in the art to make and use the teachings of the present application. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the application. Thus, the present application is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.
The technical scheme of the invention is described in detail below with reference to the examples and the accompanying drawings.
For the case of high voltage current damage devices in d-TOF devices, some current high voltage electrostatic protection schemes mainly include: aiming at the static pulse introduced in the packaging and wire bonding process, the process control is mainly realized by controlling the wire bonding machine and the process, but the efficiency is reduced and the cost is increased when the process flow is controlled; aiming at the condition that external high-voltage power supply or power supply voltage is unstable, a part of the external high-voltage power supply is protected by adopting a chip external electrostatic protection device, but the external electrostatic protection device can increase the volume and the weight of the chip. And both schemes have pertinence and cannot be used for both cases.
In summary, since d-TOF technology is currently still in an emerging search phase, there is no more uniform and efficient approach to SPAD high voltage side electrostatic protection schemes.
In view of the above problems, the present application provides a high-voltage electrostatic protection structure, a forming method thereof and a d-TOF device, where the high-voltage electrostatic protection structure includes two diodes connected in series, and the diodes can be electrically connected under a certain threshold voltage to ground a high-voltage power supply, so as to avoid the damage of the high-voltage power supply to the d-TOF device during packaging or wire bonding and during the power-up process or under the unstable voltage condition of the high-voltage power supply.
Fig. 1 to 8 are schematic structural diagrams illustrating steps in a method for forming a high-voltage electrostatic protection structure according to an embodiment of the present application. The following describes in detail a method for forming the high-voltage electrostatic protection structure according to the embodiments of the present application with reference to the accompanying drawings.
Referring to fig. 1-2, a logic wafer 100 is provided, with a first diode structure disposed in the logic wafer 100, the first diode structure being in electrical communication at a first threshold voltage. The technical scheme of this application is in order to protect d-TOF device not damaged by the high-voltage current that is higher than operating voltage, consequently, first diode structure can not communicate under normal operating voltage, can not influence the device work, only when the fluctuation appears in operating voltage and leads to actual voltage to surpass the highest operating voltage of settlement, first diode structure just can communicate to with high-voltage current ground, protection device.
In some embodiments of the present application, the logic wafer 100 is a wafer for fabricating logic devices in the d-TOF device. The first diode structure can be manufactured in the logic wafer as other logic devices, and the first diode structure and the like in the technical scheme can be manufactured by utilizing the unused space in the logic wafer without increasing the area of the original device.
Referring to fig. 1, a first substrate 110 is provided, a well region 120 is formed in the first substrate 110, a first doped region 130 and a second doped region 140 are further formed on the surface of the well region 120, and the first doped region 130, the second doped region 140 and the well region 120 form the first diode structure.
In some embodiments of the present application, the method of forming the first doped region 130, the second doped region 140, and the well region 120 includes an ion implantation process.
In some embodiments of the present application, at least one of the first doped region 130 and the second doped region 140 is opposite to the doping type of the well region 120, and the first doped region 130 and the second doped region 140 are in electrical communication at the first threshold voltage.
In this embodiment, the doping type of the first doped region 130 is opposite to the doping type of the well region 120, and the doping type of the second doped region 140 is the same as the doping type of the well region 120. For example, the doping type of the first doped region 130 is P-type, the doping type of the second doped region 140 is N-type, and the doping type of the well region 120 is N-type. The first diode structure (formed by the first doped region 130, the second doped region 140 and the well region 120) operates according to the following principle: when the voltage applied to the first diode structure is below the first voltage threshold, a PN junction is formed between the first doped region 130 and the well region 120 due to the different doping types, so that the first doped region 130 and the well region 120 are not electrically connected, and further the first doped region 130 and the second doped region 140 are not electrically connected; when the voltage applied to the first diode structure is greater than or equal to the first voltage threshold, the PN junction is broken down, resulting in the first doped region 130 and the well region 120, and thus the first doped region 130 and the second doped region 140, being in electrical communication.
In other embodiments of the present application, the doping type of the first doped region 130 may be the same as the doping type of the well region 120, and the doping type of the second doped region 140 may be opposite to the doping type of the well region 120. In other embodiments of the present application, the doping types of the first doped region 130 and the second doped region 140 may be opposite to the doping type of the well region 120.
In some embodiments of the present application, the doping types of the first doping region 130, the second doping region 140, and the well region 120 may be set according to the P/N type of the second diode structure. Specifically, the unidirectional conduction directions of PN junctions of the first diode and the second diode are consistent.
In some embodiments of the present application, the doping concentration of the first doped region 130 and the second doped region 140 is greater than the doping concentration of the well region 120. Because the first doped region 130 and the second doped region 140 are compatible with ohmic contact between metal and semiconductor materials, the doping concentration needs to be relatively large. The doping concentration of the first doped region 130 is, for example, 5e19 to 5e20 atoms/cm 3; the doping concentration of the second doped region 140 is, for example, 5e19 to 5e20 atoms/cm 3; the doping concentration of the well region 120 is, for example, 5e15 to 1e18 atoms/cm 3. The magnitude of the first threshold voltage may be controlled by controlling the doping concentration differences between the first doped region 130, the second doped region 140, and the well region 120.
In some embodiments of the present application, the first threshold voltage is 5 to 15V.
In some embodiments of the present application, the number of the first diode structures formed in the first substrate 110 may be plural. Only one first diode structure is shown in the figures for the sake of simplicity.
In some embodiments of the present application, the first diode structure in the first substrate 110 may be replaced by other structures that can perform the same function, such as a GGNMOS and a GDPMOS structure.
Referring to fig. 2, a first dielectric layer 150 is formed on the surface of the first substrate 110, and a first metal connection structure 160 and a second metal connection structure 170 penetrating the first dielectric layer 150 and electrically connecting the first doped region 130 and the second doped region 140, respectively, are formed in the first dielectric layer 150.
In some embodiments of the present application, the material of the first dielectric layer 150 is silicon oxide. The method for forming the first dielectric layer 150 includes a chemical vapor deposition process or a physical vapor deposition process.
It should be noted that, the connection relationship, the position and the shape of the first metal connection structure 160 and the second metal connection structure 170 are only generally shown in the drawings. In practice, the first metal connection structure 160 and the second metal connection structure 170 are multi-layered metal wires, which are the same as the multi-layered metal wires formed in the conventional back-end process.
In some embodiments of the present application, a plurality of bonding pads (not shown in the figure) embedded in the first dielectric layer 150 are further formed on the surface of the first dielectric layer 150, for performing hybrid bonding.
Referring to fig. 3 to 6, a pixel wafer 200 is provided, and a second diode structure is formed in the pixel wafer 200, and is connected in series with the first diode structure, and the second diode structure is electrically connected at a second threshold voltage. The technical scheme of this application is in order to protect d-TOF device not damaged by the high-voltage current that is higher than operating voltage, consequently, second diode structure can not communicate under normal operating voltage, can not influence the device work, only when the fluctuation appears in operating voltage and leads to actual voltage to surpass the highest operating voltage of settlement, second diode structure just can communicate to ground the high-voltage current, protection device. The first diode structure and the second diode structure are connected in series, so that the total threshold voltage of the high-voltage electrostatic protection structure is the sum of the first threshold voltage and the second threshold voltage.
In some embodiments of the present application, the pixel wafer 200 is a wafer for fabricating pixel elements in the d-TOF device. The second diode structure can be manufactured in the pixel wafer as the pixel element, and the area of the original device is not increased by utilizing the unused space in the pixel wafer to manufacture the second diode structure and the like in the technical scheme.
Referring to fig. 3, a second substrate 210 is provided, a buried well region 220 is formed in the second substrate 210, a third doped region 230 and a fourth doped region 240 are formed in the buried well region 220, and the third doped region 230, the fourth doped region 240 and the buried well region 220 constitute the second diode structure.
In some embodiments of the present application, the method of forming the third doped region 230, the fourth doped region 240, and the buried well region 220 includes an ion implantation process.
In some embodiments of the present application, the second diode structure is a multi-finger structure in which the doping types of the third doped region 230 and the fourth doped region 240 are opposite, one of the doping types of the third doped region 230 and the fourth doped region 240 is the same as the doping type of the buried well region 220, and the third doped region 230 and the fourth doped region 240 are in electrical communication at the second threshold voltage.
In this embodiment, the doping types of the third doped region 230 and the fourth doped region 240 are opposite, and the doping type of the fourth doped region 240 is the same as that of the buried well region 220. For example, the doping type of the third doped region 230 is P-type, the doping type of the fourth doped region 240 is N-type, and the doping type of the buried well region 220 is N-type. The second diode structure (composed of the third doped region 230, the fourth doped region 240 and the buried well region 220) operates on the following principle: when the voltage applied to the second diode structure is below the second voltage threshold, a PN junction is formed between the third doped region 230 and the buried well region 220 due to the different doping types, so that the third doped region 230 and the buried well region 220 are not electrically connected, and further the third doped region 230 and the fourth doped region 240 are not electrically connected; when the voltage applied to the second diode structure is greater than or equal to the second voltage threshold, the PN junction is broken down, resulting in the third doped region 230 and the buried well region 220, and thus the third doped region 230 and the fourth doped region 240, being in electrical communication.
In other embodiments of the present application, the doping type of the third doped region 230 may be the same as the doping type of the buried well region 220, and the doping type of the fourth doped region 240 may be opposite to the doping type of the buried well region 220.
In some embodiments of the present application, the doping types of the third doped region 230, the fourth doped region 240, and the buried well region 220 may be set according to the type of the d-TOF device. For P-type SPAD (N/P type is defined by the common end of SPAD lightly doped), the third doped region 230 is P-type and the fourth doped region 240 is N-type, and the buried well region 220 may be N-type or P-type. For an N-type SPAD, the third doped region 230 is N-type and the fourth doped region 240 is P-type, and the buried well region 220 may be N-type or P-type.
In some of the present applicationIn an embodiment, the doping concentration of the third doped region 230 and the fourth doped region 240 is greater than the doping concentration of the buried well region 220. The doping concentration of the third doped region 230 is, for example, 5e16 to 1e18 atoms/cm 3 The method comprises the steps of carrying out a first treatment on the surface of the The doping concentration of the fourth doped region 240 is, for example, 5e16 to 1e18 atoms/cm 3 The method comprises the steps of carrying out a first treatment on the surface of the The doping depth of the third doped region 230 and the fourth doped region 240 is greater than 0.5um in order to reduce on-resistance. The doping concentration of the buried well region 220 is, for example, 1e15 to 5e16 atoms/cm 3 The on-resistance of the buried well region 220 may be relatively high when the doping concentration of the buried well region 220 is too low, and the threshold voltage may be too low when the doping concentration of the buried well region 220 is too high. The magnitude of the second threshold voltage may be controlled by controlling the doping concentration differences between the third doped region 230, the fourth doped region 240, and the buried well region 220.
In some embodiments of the present application, the second threshold voltage is 20 to 60V.
In some embodiments of the present application, the total width of the third doped region 230 and the fourth doped region 240 is greater than 500 microns.
In some embodiments of the present application, a third highly doped region 231 may be further formed on the surface of the third doped region 230, where the doping concentration of the third highly doped region 231 is higher than that of the third doped region 230, and the third highly doped region 231 is used to improve the electrical connectivity of the third doped region 230; the fourth highly doped region 241 may further be formed on the surface of the fourth doped region 240, where the doping concentration of the fourth highly doped region 241 is higher than that of the fourth doped region 240, and the fourth highly doped region 241 is used to improve the electrical connectivity of the fourth doped region 240. In order to realize ohmic contact, the doping concentration of the third highly doped region 231 and the fourth highly doped region 241 is greater than 5e19 atoms/cm 3 。
In other embodiments of the present application, the second diode structure may also be a BJT structure in which the doping types of the third doped region 230 and the fourth doped region 240 are the same, the doping types of the third doped region 230 and the fourth doped region 240 are opposite to those of the buried well region 220, and the third doped region 230 and the fourth doped region 240 are in electrical communication at the second threshold voltage.
For example, the doping type of the third doped region 230 is P-type, the doping type of the fourth doped region 240 is P-type, and the doping type of the buried well region 220 is N-type. The second diode structure (composed of the third doped region 230, the fourth doped region 240 and the buried well region 220) operates on the following principle: when the voltage applied to the second diode structure is below the second voltage threshold, PNP or NPN junctions are formed between the third doped region 230 and the fourth doped region 240 and the buried well region 220 due to the different doping types, and thus the third doped region 230 and the buried well region 220 are not in electrical communication or the fourth doped region 240 and the buried well region 220 are not in electrical communication, and thus the third doped region 230 and the fourth doped region 240 are not in electrical communication; when the voltage applied to the second diode structure is greater than or equal to the second voltage threshold, the expansion of the third doped region 230 and the fourth doped region 240 causes the third doped region 230 and the fourth doped region 240 to directly contact and electrically communicate.
In some embodiments of the present application, the third doped region 230 and the fourth doped region 240 have a spacing of 0.4 to 2 microns. The magnitude of the second threshold voltage may be controlled by controlling the pitch, the larger the second threshold voltage.
In some embodiments of the present application, a fifth doped region (not shown in fig. 3, which will be described and illustrated later) is further disposed on both sides of the third doped region 230 and the fourth doped region 240, and the fifth doped region is opposite to the doping type of the third doped region 230 and the fourth doped region 240. The fifth doped region is used to form a PN junction with the third doped region 230 and the fourth doped region 240 so as to protect the third doped region 230 and the fourth doped region 240.
In some embodiments of the present application, the number of second diode structures formed in the second substrate 210 may be a plurality. Only one second diode structure is shown in the figures for the sake of simplicity.
Referring to fig. 4, a second dielectric layer 250 is formed on the surface of the second substrate 210, and a third metal connection structure 260 for electrically connecting the first doped region 130 and the fourth doped region 240 is disposed in the second dielectric layer 250.
In some embodiments of the present application, the material of the second dielectric layer 250 is silicon oxide. The second dielectric layer 250 is formed by a chemical vapor deposition process, a physical vapor deposition process, or the like.
It should be noted that, the connection relationship, the position and the shape of the third metal connection structure 260 are only generally shown in the drawings. In practice, the third metal connection structure 260 is a multi-layer metal connection, which is the same as the multi-layer metal connection formed in the conventional back-end process.
In some embodiments of the present application, a plurality of bonding pads (not shown in the figure) embedded in the second dielectric layer 250 are further formed on the surface of the second dielectric layer 250, for performing hybrid bonding.
Referring to fig. 5, a first through-silicon via structure 270 is formed in the second substrate 210 and is located at one side of the buried well region 220, the first through-silicon via structure 270 penetrates the second substrate 210 and extends into the second dielectric layer 250, and the first through-silicon via structure 270 electrically connects the third doped region 230 and the high-voltage power supply end of the d-TOF device; a second through-silicon via structure 280 is formed in the second substrate 210 and is located at the other side of the buried well region 220, the second through-silicon via structure 280 penetrates through the second substrate 210 and extends into the second dielectric layer 250, and the second through-silicon via structure 280 is used for electrically connecting the second doped region 140 and the ground terminal of the d-TOF device.
Specifically, the electrical connection relationship of the high-voltage electrostatic protection structure can be simplified as follows: the high voltage power supply, the second diode structure, the first diode structure and the ground. When the voltage of the high-voltage power supply end is larger than or equal to the sum of the first threshold voltage and the second threshold voltage, the first diode structure is communicated with the second diode structure, and then the high-voltage power supply is grounded, so that the d-TOF device is protected from being damaged by high voltage.
Referring to fig. 6, fig. 6 is a schematic diagram of electrical connection of a second diode structure of a multi-finger structure according to an embodiment of the present application. The third doped regions 230 and the fourth doped regions 240 are alternately distributed in the second substrate 220, the third doped regions 230 are electrically connected to the high voltage power source HV, and the fourth doped regions 240 are grounded GND.
Referring to fig. 7, fig. 7 is a schematic diagram illustrating electrical connection of a second diode structure of the BJT structure according to an embodiment of the present application. The third doped regions 230 and the fourth doped regions 240 are alternately distributed in the second substrate 220, the third doped regions 230 are electrically connected to the high voltage power source HV, and the fourth doped regions 240 are grounded GND. The third doped region 230 and the fourth doped region 240 are also provided on both sides with the fifth doped region 290 described above. The fifth doped region 290 may be electrically connected to the high voltage power source HV or the ground GND, depending on the type of SPAD and the type of BJT structure.
Referring to fig. 8, the logic wafer 100 and the pixel wafer 200 are bonded, wherein a first end of the second diode structure is electrically connected to a high voltage power supply end of the d-TOF device, a second end of the second diode structure is electrically connected to a first end of the first diode structure, and a second end of the first diode structure is electrically connected to a ground end of the d-TOF device.
In some embodiments of the present application, the bonding manner of the logic wafer 100 and the pixel wafer 200 is hybrid bonding. The bonding mode can directly utilize the bonding pad to realize the electric connection of two wafers, and has a structure simpler than that of a fusion bonding mode.
According to the forming method of the high-voltage electrostatic protection structure, the high-voltage electrostatic protection structure comprises two diodes which are connected in series, the diodes can be electrically connected under a certain threshold voltage, so that the high-voltage power supply is grounded, and the damage to the d-TOF device caused by the high-voltage power supply in the packaging or wire bonding process and under the condition of unstable voltage or in the powering-on process of the high-voltage power supply is avoided.
The embodiment of the application also provides a high-voltage electrostatic protection structure, referring to fig. 8, including: a logic wafer 100, wherein a first diode structure is disposed in the logic wafer 100, and the first diode structure is electrically connected at a first threshold voltage; a pixel wafer 200, wherein a second diode structure is disposed in the pixel wafer 200 and connected in series with the first diode structure, and the second diode structure is electrically connected at a second threshold voltage; the logic wafer 100 and the pixel wafer 200 are bonded, the first end of the second diode structure is electrically connected to the high voltage power supply end of the d-TOF device, the second end of the second diode structure is electrically connected to the first end of the first diode structure, and the second end of the first diode structure is electrically connected to the ground end of the d-TOF device.
Referring to fig. 8, a first diode structure is disposed in the logic wafer 100, the first diode structure being in electrical communication at a first threshold voltage. The technical scheme of this application is in order to protect d-TOF device not damaged by the high-voltage current that is higher than operating voltage, consequently, first diode structure can not communicate under normal operating voltage, can not influence the device work, only when the fluctuation appears in operating voltage and leads to actual voltage to surpass the highest operating voltage of settlement, first diode structure just can communicate to with high-voltage current ground, protection device.
In some embodiments of the present application, the logic wafer 100 is a wafer for fabricating logic devices in the d-TOF device. The first diode structure can be manufactured in the logic wafer as other logic devices, and the first diode structure and the like in the technical scheme can be manufactured by utilizing the unused space in the logic wafer without increasing the area of the original device.
With continued reference to fig. 8, the logic wafer 100 includes: the first substrate 110, a well region 120 is disposed in the first substrate 110, a first doped region 130 and a second doped region 140 are further disposed on the surface of the well region 120, and the first doped region 130, the second doped region 140 and the well region 120 form the first diode structure.
In some embodiments of the present application, at least one of the first doped region 130 and the second doped region 140 is opposite to the doping type of the well region 120, and the first doped region 130 and the second doped region 140 are in electrical communication at the first threshold voltage.
In this embodiment, the doping type of the first doped region 130 is opposite to the doping type of the well region 120, and the doping type of the second doped region 140 is the same as the doping type of the well region 120. For example, the doping type of the first doped region 130 is P-type, the doping type of the second doped region 140 is N-type, and the doping type of the well region 120 is N-type. The first diode structure (formed by the first doped region 130, the second doped region 140 and the well region 120) operates according to the following principle: when the voltage applied to the first diode structure is below the first voltage threshold, a PN junction is formed between the first doped region 130 and the well region 120 due to the different doping types, so that the first doped region 130 and the well region 120 are not electrically connected, and further the first doped region 130 and the second doped region 140 are not electrically connected; when the voltage applied to the first diode structure is greater than or equal to the first voltage threshold, the PN junction is broken down, resulting in the first doped region 130 and the well region 120, and thus the first doped region 130 and the second doped region 140, being in electrical communication.
In other embodiments of the present application, the doping type of the first doped region 130 may be the same as the doping type of the well region 120, and the doping type of the second doped region 140 may be opposite to the doping type of the well region 120. In other embodiments of the present application, the doping types of the first doped region 130 and the second doped region 140 may be opposite to the doping type of the well region 120.
In some embodiments of the present application, the doping types of the first doping region 130, the second doping region 140, and the well region 120 may be set according to the P/N type of the second diode structure. Specifically, the unidirectional conduction directions of PN junctions of the first diode and the second diode are consistent.
In some embodiments of the present application, the doping concentration of the first doped region 130 and the second doped region 140 is greater than the doping concentration of the well region 120. Because the first doped region 130 and the second doped region 140 are compatible with ohmic contact between metal and semiconductor materials, the doping concentration needs to be relatively large. The doping concentration of the first doped region 130 is, for example, 5e19 to 5e20 atoms/cm 3; the doping concentration of the second doped region 140 is, for example, 5e19 to 5e20 atoms/cm 3; the doping concentration of the well region 120 is, for example, 5e15 to 1e18 atoms/cm 3. The magnitude of the first threshold voltage may be controlled by controlling the doping concentration differences between the first doped region 130, the second doped region 140, and the well region 120.
In some embodiments of the present application, the first threshold voltage is 5 to 15V.
In some embodiments of the present application, the number of the first diode structures formed in the first substrate 110 may be plural. Only one first diode structure is shown in the figures for the sake of simplicity.
In some embodiments of the present application, the first diode structure in the first substrate 110 may be replaced by other structures that can perform the same function, such as a GGNMOS and a GDPMOS structure.
With continued reference to fig. 8, the logic wafer 100 further includes a first dielectric layer 150 disposed on the surface of the first substrate 110, where a first metal connection structure 160 and a second metal connection structure 170 penetrating the first dielectric layer 150 and electrically connecting the first doped region 130 and the second doped region 140, respectively, are disposed in the first dielectric layer 150.
In some embodiments of the present application, the material of the first dielectric layer 150 is silicon oxide.
It should be noted that, the connection relationship, the position and the shape of the first metal connection structure 160 and the second metal connection structure 170 are only generally shown in the drawings. In practice, the first metal connection structure 160 and the second metal connection structure 170 are multi-layered metal wires, which are the same as the multi-layered metal wires formed in the conventional back-end process.
In some embodiments of the present application, a plurality of bonding pads (not shown in the figure) embedded in the first dielectric layer 150 are further formed on the surface of the first dielectric layer 150, for performing hybrid bonding.
With continued reference to fig. 8, a second diode structure is disposed in the pixel wafer 200 in series with the first diode structure, the second diode structure being in electrical communication at a second threshold voltage. The technical scheme of this application is in order to protect d-TOF device not damaged by the high-voltage current that is higher than operating voltage, consequently, second diode structure can not communicate under normal operating voltage, can not influence the device work, only when the fluctuation appears in operating voltage and leads to actual voltage to surpass the highest operating voltage of settlement, second diode structure just can communicate to ground the high-voltage current, protection device. The first diode structure and the second diode structure are connected in series, so that the total threshold voltage of the high-voltage electrostatic protection structure is the sum of the first threshold voltage and the second threshold voltage.
In some embodiments of the present application, the pixel wafer 200 is a wafer for fabricating pixel elements in the d-TOF device. The second diode structure can be manufactured in the pixel wafer as the pixel element, and the area of the original device is not increased by utilizing the unused space in the pixel wafer to manufacture the second diode structure and the like in the technical scheme.
With continued reference to fig. 8, the pixel wafer 200 includes: a second substrate 210, a buried well region 220 is disposed in the second substrate 210, a third doped region 230 and a fourth doped region 240 are disposed in the buried well region 220, and the third doped region 230, the fourth doped region 240 and the buried well region 220 form the second diode structure.
In some embodiments of the present application, the second diode structure is a multi-finger structure in which the doping types of the third doped region 230 and the fourth doped region 240 are opposite, one of the doping types of the third doped region 230 and the fourth doped region 240 is the same as the doping type of the buried well region 220, and the third doped region 230 and the fourth doped region 240 are in electrical communication at the second threshold voltage.
In this embodiment, the doping types of the third doped region 230 and the fourth doped region 240 are opposite, and the doping type of the fourth doped region 240 is the same as that of the buried well region 220. For example, the doping type of the third doped region 230 is P-type, the doping type of the fourth doped region 240 is N-type, and the doping type of the buried well region 220 is N-type. The second diode structure (composed of the third doped region 230, the fourth doped region 240 and the buried well region 220) operates on the following principle: when the voltage applied to the second diode structure is below the second voltage threshold, a PN junction is formed between the third doped region 230 and the buried well region 220 due to the different doping types, so that the third doped region 230 and the buried well region 220 are not electrically connected, and further the third doped region 230 and the fourth doped region 240 are not electrically connected; when the voltage applied to the second diode structure is greater than or equal to the second voltage threshold, the PN junction is broken down, resulting in the third doped region 230 and the buried well region 220, and thus the third doped region 230 and the fourth doped region 240, being in electrical communication.
In other embodiments of the present application, the doping type of the third doped region 230 may be the same as the doping type of the buried well region 220, and the doping type of the fourth doped region 240 may be opposite to the doping type of the buried well region 220.
In some embodiments of the present application, the doping types of the third doped region 230, the fourth doped region 240, and the buried well region 220 may be set according to the type of the d-TOF device. For P-type SPAD (N/P type is defined by the common end of SPAD lightly doped), the third doped region 230 is P-type and the fourth doped region 240 is N-type, and the buried well region 220 may be N-type or P-type. For an N-type SPAD, the third doped region 230 is N-type and the fourth doped region 240 is P-type, and the buried well region 220 may be N-type or P-type.
In some embodiments of the present application, the doping concentration of the third doped region 230 and the fourth doped region 240 is greater than the doping concentration of the buried well region 220. The doping concentration of the third doped region 230 is, for example, 5e16 to 1e18 atoms/cm 3 The method comprises the steps of carrying out a first treatment on the surface of the The doping concentration of the fourth doped region 240 is, for example, 5e16 to 1e18 atoms/cm 3 The method comprises the steps of carrying out a first treatment on the surface of the The doping depth of the third doped region 230 and the fourth doped region 240 is greater than 0.5um in order to reduce on-resistance. The doping concentration of the buried well region 220 is, for example, 1e15 to 5e16 atoms/cm 3 The on-resistance of the buried well region 220 may be relatively high when the doping concentration of the buried well region 220 is too low, and the threshold voltage may be too low when the doping concentration of the buried well region 220 is too high. The magnitude of the second threshold voltage may be controlled by controlling the doping concentration differences between the third doped region 230, the fourth doped region 240, and the buried well region 220.
In some embodiments of the present application, the second threshold voltage is 20 to 60V.
In some embodiments of the present application, the total width of the third doped region 230 and the fourth doped region 240 is greater than 500 microns.
In some embodiments of the present application, a third highly doped region 231 may be further formed on the surface of the third doped region 230, where the doping concentration of the third highly doped region 231 is higher than that of the third doped region 230, and the third highly doped region 231 is used to improve the electrical connectivity of the third doped region 230; the fourth highly doped region 241 may further be formed on the surface of the fourth doped region 240, where the doping concentration of the fourth highly doped region 241 is higher than that of the fourth doped region 240, and the fourth highly doped region 241 is used to improve the electrical connectivity of the fourth doped region 240. In order to realize ohmic contact, the doping concentration of the third highly doped region 231 and the fourth highly doped region 241 is greater than 5e19 atoms/cm 3 。
In other embodiments of the present application, the second diode structure may also be a BJT structure in which the doping types of the third doped region 230 and the fourth doped region 240 are the same, the doping types of the third doped region 230 and the fourth doped region 240 are opposite to those of the buried well region 220, and the third doped region 230 and the fourth doped region 240 are in electrical communication at the second threshold voltage.
For example, the doping type of the third doped region 230 is P-type, the doping type of the fourth doped region 240 is P-type, and the doping type of the buried well region 220 is N-type. The second diode structure (formed by the third doped region 230 the fourth doped region 240 and the buried well region 220) operates on the principle that: when the voltage applied to the second diode structure is below the second voltage threshold, PNP or NPN junctions are formed between the third doped region 230 and the fourth doped region 240 and the buried well region 220 due to the different doping types, and thus the third doped region 230 and the buried well region 220 are not in electrical communication or the fourth doped region 240 and the buried well region 220 are not in electrical communication, and thus the third doped region 230 and the fourth doped region 240 are not in electrical communication; when the voltage applied to the second diode structure is greater than or equal to the second voltage threshold, the expansion of the third doped region 230 and the fourth doped region 240 causes the third doped region 230 and the fourth doped region 240 to directly contact and electrically communicate.
In some embodiments of the present application, the third doped region 230 and the fourth doped region 240 have a spacing of 0.4 to 2 microns. The magnitude of the second threshold voltage may be controlled by controlling the pitch, the larger the second threshold voltage.
In some embodiments of the present application, in this BJT structure, a fifth doped region is further disposed on both sides of the third doped region 230 and the fourth doped region 240, and the fifth doped region is opposite to the doping type of the third doped region 230 and the fourth doped region 240. The fifth doped region is used to form a PN junction with the third doped region 230 and the fourth doped region 240 so as to protect the third doped region 230 and the fourth doped region 240.
In some embodiments of the present application, the number of second diode structures formed in the second substrate 210 may be a plurality. Only one second diode structure is shown in the figures for the sake of simplicity.
With continued reference to fig. 8, the pixel wafer 200 further includes a second dielectric layer 250 disposed on the surface of the second substrate 210, where a third metal connection structure 260 is disposed in the second dielectric layer 250 and is used to electrically connect the first doped region 130 and the fourth doped region 240.
In some embodiments of the present application, the material of the second dielectric layer 250 is silicon oxide.
It should be noted that, the connection relationship, the position and the shape of the third metal connection structure 260 are only generally shown in the drawings. In practice, the third metal connection structure 260 is a multi-layer metal connection, which is the same as the multi-layer metal connection formed in the conventional back-end process.
In some embodiments of the present application, a plurality of bonding pads (not shown in the figure) embedded in the second dielectric layer 250 are further formed on the surface of the second dielectric layer 250, for performing hybrid bonding.
With continued reference to fig. 8, the pixel wafer 200 further includes: a first through-silicon via structure 270 located at one side of the buried well region 220, the first through-silicon via structure 270 penetrating the second substrate 210 and extending into the second dielectric layer 250, the first through-silicon via structure 270 electrically connecting the third doped region 230 and the high voltage power supply terminal of the d-TOF device; a second through-silicon via structure 280 is located at the other side of the buried well region 220, the second through-silicon via structure 280 penetrates through the second substrate 210 and extends into the second dielectric layer 250, and the second through-silicon via structure 280 is used for electrically connecting the second doped region 140 and the ground terminal of the d-TOF device.
Specifically, the electrical connection relationship of the high-voltage electrostatic protection structure can be simplified as follows: the high voltage power supply, the second diode structure, the first diode structure and the ground. When the voltage of the high-voltage power supply end is larger than or equal to the sum of the first threshold voltage and the second threshold voltage, the first diode structure is communicated with the second diode structure, and then the high-voltage power supply is grounded, so that the d-TOF device is protected from being damaged by high voltage.
Referring to fig. 6, fig. 6 is a schematic diagram of electrical connection of a second diode structure of a multi-finger structure according to an embodiment of the present application. The third doped regions 230 and the fourth doped regions 240 are alternately distributed in the second substrate 220, the third doped regions 230 are electrically connected to the high voltage power source HV, and the fourth doped regions 240 are grounded GND.
Referring to fig. 7, fig. 7 is a schematic diagram illustrating electrical connection of a second diode structure of the BJT structure according to an embodiment of the present application. The third doped regions 230 and the fourth doped regions 240 are alternately distributed in the second substrate 220, the third doped regions 230 are electrically connected to the high voltage power source HV, and the fourth doped regions 240 are grounded GND. The third doped region 230 and the fourth doped region 240 are also provided on both sides with the fifth doped region 290 described above. The fifth doped region 290 may be electrically connected to the high voltage power source HV or the ground GND, depending on the type of SPAD and the type of BJT structure.
With continued reference to fig. 8, the logic wafer 100 and the pixel wafer 200 are bonded, wherein a first end of the second diode structure is electrically connected to a high voltage power supply end of the d-TOF device, a second end of the second diode structure is electrically connected to a first end of the first diode structure, and a second end of the first diode structure is electrically connected to a ground end of the d-TOF device.
In some embodiments of the present application, the bonding manner of the logic wafer 100 and the pixel wafer 200 is hybrid bonding. The bonding mode can directly utilize the bonding pad to realize the electric connection of two wafers, and has a structure simpler than that of a fusion bonding mode.
The application discloses high-voltage electrostatic protection structure, high-voltage electrostatic protection structure includes two series connection's diode, thereby the diode can be electric intercommunication ground connection high-voltage power supply under certain threshold voltage, thereby avoid high-voltage power supply to damage d-TOF device in encapsulation or routing in-process and high-voltage power supply in-process or under the unstable condition of voltage.
Fig. 9 is a schematic structural diagram of a d-TOF device according to an embodiment of the present application.
Embodiments of the present application also provide a d-TOF device, as shown with reference to FIG. 9, comprising: a high voltage power supply HV; a single photon avalanche diode 340 (SPAD) connected to the high voltage power supply HV; time-to-digital converter 310 (TDC), one end and the other The single photon avalanche diode 340 is connected with the other end of the single photon avalanche diode is connected with the detection voltage V sense The method comprises the steps of carrying out a first treatment on the surface of the A reset circuit 320 (reset circuit) having one end connected to the single photon avalanche diode 340 and the other end connected to an operating voltage VDD; a quenching circuit 330 (sequence circuit) having one end connected to the single photon avalanche diode 340 and the other end grounded GND; as described above, one end of the high voltage electrostatic protection structure 350 is connected to the high voltage power source HV, and the other end is grounded GND. Specifically, the first end of the second diode structure (i.e., the first through silicon via structure 270) is connected to the high voltage power supply HV, the second end of the first diode structure (i.e., the second through silicon via structure 280) is grounded GND, and when the voltage of the high voltage power supply HV is equal to or greater than the sum of the first threshold voltage and the second threshold voltage, the high voltage electrostatic protection structure 350 electrically connects the high voltage power supply HV and the grounded GND, so as to introduce a high voltage current to the bottom surface, thereby protecting the device from being damaged by the high voltage current.
The single photon avalanche diode 340, the time-to-digital converter 310, the reset circuit 320, and the quench circuit 330 in the d-TOF device are the same as the corresponding structures in the conventional d-TOF device, and are not described herein.
The application provides a high-voltage electrostatic protection structure, a forming method thereof and a d-TOF device, wherein the high-voltage electrostatic protection structure comprises two diodes which are connected in series, and the diodes can be electrically connected under a certain threshold voltage so as to ground a high-voltage power supply, thereby avoiding the damage to the d-TOF device in the packaging or wire bonding process and under the condition of the power-on process or unstable voltage of the high-voltage power supply.
In view of the foregoing, it will be evident to those skilled in the art after reading this application that the foregoing application may be presented by way of example only and may not be limiting. Although not explicitly described herein, those skilled in the art will appreciate that the present application is intended to embrace a variety of reasonable alterations, improvements and modifications to the embodiments. Such alterations, improvements, and modifications are intended to be within the spirit and scope of the exemplary embodiments of the present application.
It should be understood that the term "and/or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present.
Similarly, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. It will be further understood that the terms "comprises," "comprising," "includes" or "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It will be further understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element in some embodiments could be termed a second element in other embodiments without departing from the teachings of the present application. Like reference numerals or like reference numerals designate like elements throughout the specification.
Furthermore, the present specification describes example embodiments by reference to idealized example cross-sectional and/or plan and/or perspective views. Thus, differences from the illustrated shapes, due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

Claims (15)

1. A high voltage electrostatic protection structure, comprising:
a logic wafer having a first diode structure disposed therein, the first diode structure being in electrical communication at a first threshold voltage;
a pixel wafer, in which a second diode structure is arranged, and is connected in series with the first diode structure, and the second diode structure is electrically connected under a second threshold voltage;
the logic wafer is bonded with the pixel wafer, the first end of the second diode structure is electrically connected with the high-voltage power supply end of the d-TOF device, the second end of the second diode structure is electrically connected with the first end of the first diode structure, and the second end of the first diode structure is electrically connected with the ground end of the d-TOF device.
2. The high voltage electrostatic protection structure of claim 1, wherein the logic wafer comprises:
the first substrate is provided with a well region, the surface of the well region is also provided with a first doped region and a second doped region, and the first doped region, the second doped region and the well region form the first diode structure;
the first dielectric layer is positioned on the surface of the first substrate, and a first metal connecting structure and a second metal connecting structure which penetrate through the first dielectric layer and are respectively and electrically connected with the first doping region and the second doping region are arranged in the first dielectric layer.
3. The high voltage electrostatic protection structure according to claim 2, wherein at least one of the first doped region and the second doped region is of an opposite doping type to the well region, the first doped region and the second doped region being in electrical communication at the first threshold voltage.
4. The high voltage electrostatic protection structure according to claim 3, wherein the first threshold voltage is 5 to 15V.
5. The high voltage electrostatic protection structure according to claim 2, wherein the pixel wafer comprises:
the second substrate is provided with a buried well region, a third doped region and a fourth doped region are arranged in the buried well region, and the third doped region, the fourth doped region and the buried well region form the second diode structure;
the second dielectric layer is positioned on the surface of the second substrate, and a third metal connecting structure which is electrically connected with the first doped region and the fourth doped region is arranged in the second dielectric layer.
6. The high voltage electrostatic protection structure according to claim 5, wherein the pixel wafer further comprises:
the first through silicon via structure is positioned at one side of the buried well region, penetrates through the second substrate and extends into the second dielectric layer, and is electrically connected with the third doping region and the high-voltage power end of the d-TOF device;
And the second silicon through hole structure is positioned at the other side of the buried well region, penetrates through the second substrate and extends into the second dielectric layer, and is electrically connected with the second doping region and the grounding end of the d-TOF device.
7. The high voltage electrostatic protection structure according to claim 5, wherein a doping type of the third doped region and the fourth doped region is opposite, one of the third doped region and the fourth doped region being the same doping type as the buried well region, the third doped region and the fourth doped region being in electrical communication at the second threshold voltage.
8. The high voltage electrostatic protection structure according to claim 7, wherein the second threshold voltage is 20 to 60V.
9. The high voltage electrostatic protection structure of claim 7, whichCharacterized in that the doping concentration of the third doping region and the fourth doping region is 5e16 to 1e18atom/cm 3 。
10. The high voltage electrostatic protection structure according to claim 5, wherein doping types of the third doping region and the fourth doping region are the same, and doping types of the third doping region and the fourth doping region are opposite to doping types of the buried well region.
11. The structure of claim 10, wherein a fifth doped region is further disposed on both sides of the third doped region and the fourth doped region, the fifth doped region being of opposite doping type to the third doped region and the fourth doped region.
12. The high voltage electrostatic protection structure according to claim 11, wherein a spacing between the third doped region and the fourth doped region is 0.4 to 2 microns.
13. The structure of claim 1, wherein the logic wafer and the pixel wafer are bonded in a hybrid bonding.
14. A method of forming a high voltage electrostatic protection structure according to claims 1-13, comprising:
providing a logic wafer, wherein a first diode structure is arranged in the logic wafer, and the first diode structure is electrically communicated under a first threshold voltage;
providing a pixel wafer, wherein a second diode structure is arranged in the pixel wafer and is connected in series with the first diode structure, and the second diode structure is electrically communicated under a second threshold voltage;
and bonding the logic wafer and the pixel wafer, wherein a first end of the second diode structure is electrically connected with a high-voltage power supply end of the d-TOF device, a second end of the second diode structure is electrically connected with a first end of the first diode structure, and a second end of the first diode structure is electrically connected with a ground end of the d-TOF device.
15. A d-TOF device, comprising:
a high voltage power supply;
a single photon avalanche diode connected with the high voltage power supply;
one end of the time-to-digital converter is connected with the single photon avalanche diode, and the other end of the time-to-digital converter is connected with a detection voltage;
one end of the reset circuit is connected with the single photon avalanche diode, and the other end of the reset circuit is connected with the working voltage;
one end of the quenching circuit is connected with the single photon avalanche diode, and the other end of the quenching circuit is grounded;
the high voltage electrostatic protection structure of any of claims 1-13, a first end of the second diode structure being connected to the high voltage power supply, a second end of the first diode structure being grounded, the high voltage electrostatic protection structure being in electrical communication with the high voltage power supply and a ground when a voltage of the high voltage power supply is greater than or equal to a sum of the first threshold voltage and the second threshold voltage.
CN202111678107.8A 2021-12-31 2021-12-31 High-voltage electrostatic protection structure, forming method thereof and d-TOF device Pending CN116417454A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111678107.8A CN116417454A (en) 2021-12-31 2021-12-31 High-voltage electrostatic protection structure, forming method thereof and d-TOF device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111678107.8A CN116417454A (en) 2021-12-31 2021-12-31 High-voltage electrostatic protection structure, forming method thereof and d-TOF device

Publications (1)

Publication Number Publication Date
CN116417454A true CN116417454A (en) 2023-07-11

Family

ID=87048438

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111678107.8A Pending CN116417454A (en) 2021-12-31 2021-12-31 High-voltage electrostatic protection structure, forming method thereof and d-TOF device

Country Status (1)

Country Link
CN (1) CN116417454A (en)

Similar Documents

Publication Publication Date Title
US7868387B2 (en) Low leakage protection device
US8525299B2 (en) Electrical overstress protection using through-silicon-via (TSV)
US8633509B2 (en) Apparatus and method for transient electrical overstress protection
KR101394913B1 (en) Latch-Up Free Vertical TVS Diode Array Structure Using Trench Isolation
US20180047717A1 (en) Esd protection device and method for manufacturing the same
US10431708B2 (en) Integrated circuit including ESD device and radiation emitting device
JP2004336032A (en) Structure of integrated circuit for conducting electrostatic discharge energy
KR100369496B1 (en) Integrated semiconductor circuit with structure for protecting from electrostatic discharge
EP0703621B1 (en) Electrostatic discharge protection device for MOS integrated circuits
CN109103178A (en) Static discharge device
CN110867487A (en) Silicon controlled rectifier and manufacturing method thereof
US8841696B2 (en) High-trigger current SCR
CN107275324B (en) Electrostatic discharge protective equipment and method
US10147716B2 (en) Electrostatic discharge protection apparatus and applications thereof
US8866228B2 (en) Diode and electrostatic discharge protection circuit including the same
CN116417454A (en) High-voltage electrostatic protection structure, forming method thereof and d-TOF device
JP4854663B2 (en) ESD protection structure of semiconductor element
EP2763171B1 (en) Electrostatic discharge protective device
JP5529436B2 (en) ESD protection circuit
CN112447703A (en) Electrostatic discharge protection element
CN219513104U (en) Electrostatic protection diode
TWI239626B (en) Structure of electrostatic discharge suppressor and method of stacking package with semiconductor devices
US20220328629A1 (en) Thyristor semiconductor device and corresponding manufacturing method
US20230307438A1 (en) Electro-static discharge protection devices having a low trigger voltage
US20240178659A1 (en) Data transmission system

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination