CN116414170B - Zero temperature coefficient current generation circuit - Google Patents
Zero temperature coefficient current generation circuit Download PDFInfo
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- CN116414170B CN116414170B CN202310193662.4A CN202310193662A CN116414170B CN 116414170 B CN116414170 B CN 116414170B CN 202310193662 A CN202310193662 A CN 202310193662A CN 116414170 B CN116414170 B CN 116414170B
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- 239000004065 semiconductor Substances 0.000 description 2
- NAWXUBYGYWOOIX-SFHVURJKSA-N (2s)-2-[[4-[2-(2,4-diaminoquinazolin-6-yl)ethyl]benzoyl]amino]-4-methylidenepentanedioic acid Chemical compound C1=CC2=NC(N)=NC(N)=C2C=C1CCC1=CC=C(C(=O)N[C@@H](CC(=C)C(O)=O)C(O)=O)C=C1 NAWXUBYGYWOOIX-SFHVURJKSA-N 0.000 description 1
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- 238000007796 conventional method Methods 0.000 description 1
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/561—Voltage to current converters
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The application discloses a zero temperature coefficient current generating circuit, which solves the problems that the traditional zero temperature coefficient current generating circuit uses more tubes, the circuit power consumption is larger, and the generated current is influenced by the temperature characteristic of a resistor. The circuit consists of four PMOS tubes, two triodes and three resistors; the circuit comprises: a first circuit comprising a first triode Q1, a first resistor R1 and a second resistor R2 for generating a first positive temperature current I 1 The method comprises the steps of carrying out a first treatment on the surface of the A second circuit comprising a second triode Q2 and a third resistor R3 for generating a second positive temperature current I 2 The method comprises the steps of carrying out a first treatment on the surface of the A third circuit composed of a first PMOS tube M1, a second PMOS tube M2, a third PMOS tube M3, and a fourth PMOS tube M4 for supplying a first positive temperature current I 1 And a second positive temperature current I 2 Combined into zero temperature coefficient current I. The first circuit, the second circuit and the third circuit are connected in pairs, the third resistor R3 is obtained by adopting a combination of a positive temperature resistor and a negative temperature resistor, and the influence of the third resistor R3 on a temperature coefficient on the zero temperature coefficient current I can be eliminated.
Description
Technical Field
The application relates to the field of power management, in particular to a zero temperature coefficient current generation circuit.
Background
In power management circuits (e.g., in various types of DC/DC converters), a zero temperature coefficient current generation circuit is typically required to obtain a zero temperature coefficient current.
The traditional method for obtaining the zero temperature coefficient current is realized through a buffer circuit, and the principle of the buffer circuit is as follows: the passing current is converted into zero temperature coefficient current through the amplifier serving as a buffer, but the number of tubes consumed by the method is large, so that the whole circuit consumes more power, and the current generated by the buffer circuit is influenced by the temperature characteristic of the resistor.
Disclosure of Invention
The embodiment of the application provides a zero temperature coefficient current generation circuit, which aims to solve the problems that the traditional zero temperature coefficient current acquisition circuit uses more tubes, the circuit power consumption is larger, and the generated current is influenced by the temperature characteristic of a resistor.
In order to solve the technical problems, the embodiment of the application is realized as follows:
the embodiment of the application provides a zero temperature coefficient current generating circuit, which consists of four PMOS tubes, two triodes and three resistors; the zero temperature coefficient current generating circuit includes: a first circuit comprising a first triode Q1, a first resistor R1 and a second resistor R2 for generating a first positive temperature current I 1 The method comprises the steps of carrying out a first treatment on the surface of the A second circuit comprising a second triode Q2 and a third resistor R3 for generating a second positive temperature current I 2 The method comprises the steps of carrying out a first treatment on the surface of the A third circuit composed of a first PMOS tube M1, a second PMOS tube M2, a third PMOS tube M3, and a fourth PMOS tube M4 for supplying a first positive temperature current I 1 And a second positive temperature current I 2 Combined into zero temperature coefficient current I. The first circuit, the second circuit and the third circuit are connected in pairs, the third resistor R3 is obtained by adopting a combination of a positive temperature resistor and a negative temperature resistor, and the influence of the third resistor R3 on a temperature coefficient on the zero temperature coefficient current I can be eliminated.
Optionally, in the first circuit: the base electrode of the first triode Q1 is connected with a fixed reference voltage V; the collector electrode of the first triode Q1 is sequentially connected with the drain electrode of the second PMOS tube M2 and the drain electrode of the third PMOS tube M3 and is connected to the grid electrode of the third PMOS tube M3 and the grid electrode of the fourth PMOS tube M4; the emitter of the first triode Q1 is connected with one end of a first resistor R1, the other end of the first resistor R1 is connected with a second resistor R2, and the other end of the second resistor R2 is grounded.
Optionally, in the second circuit: the base electrode of the second triode Q2 is connected with the junction of the first resistor R1 and the second resistor R2, the collector electrode of the second triode Q2 is connected with the drain electrode of the first PMOS tube M1 and is connected to the grid electrode of the second PMOS tube M2, and the emitter electrode of the second triode Q2 is connected with the third resistor R3; one end of the third resistor R3 is connected with the emitter of the second triode Q2, and the other end of the third resistor R is grounded.
Optionally, in the third circuit: the grid electrode of the first PMOS tube M1 is connected with the grid electrode of the second PMOS tube M2 and is connected to the drain electrode of the first PMOS tube M1, the drain electrode of the first PMOS tube M1 is connected with the collector electrode of the second triode Q2 and is connected to the grid electrode of the first PMOS tube M1, and the source electrode of the first PMOS tube M1 is connected with the power supply end VDD; the grid electrode of the second PMOS tube M2 is connected with the grid electrode of the first PMOS tube M1 and is connected to the drain electrode of the first PMOS tube M1, the drain electrode of the second PMOS tube M2 is connected with the collector electrode of the first triode Q1 and is connected to the drain electrode of the third PMOS tube M3, the grid electrode of the third PMOS tube M3 and the grid electrode of the fourth PMOS tube M4, and the source electrode of the second PMOS tube M2 is connected with the power end VDD; the grid electrode of the third PMOS tube M3 is connected with the grid electrode of the fourth PMOS tube M4 and is connected with the drain electrode of the second PMOS tube M2, the collector electrode of the first triode Q1 and the drain electrode of the third PMOS tube M3, the drain electrode of the third PMOS tube M3 is connected with the grid electrode of the third PMOS tube M3 and is connected with the drain electrode of the second PMOS tube M2, the collector electrode of the first triode Q1 and the grid electrode of the fourth PMOS tube M4, and the source electrode of the third PMOS tube M3 is connected with the power supply end VDD; the grid electrode of the fourth PMOS tube M4 is connected with the grid electrode of the third PMOS tube M3 and is connected to the drain electrode of the second PMOS tube M2, the collector electrode of the first triode Q1 and the drain electrode of the third PMOS tube M3, the source electrode of the fourth PMOS tube M4 is connected with the power supply end VDD, and the drain electrode of the fourth PMOS tube M4 is output.
Optionally, the resistance R of the first resistor R1 1 Resistance value R of second resistor R2 2 And a resistance value R of the third resistor R3 3 There is the following relationship:
R 1 +2R 2 ＝R 3
optionally, according to the zero temperature coefficient current generating circuit, the calculation formula for obtaining the zero temperature coefficient current I is as follows:
wherein I is 1 For the first positive temperature current generated by the first circuit, I 2 For the second positive temperature current generated by the second circuit, V is a fixed reference voltage, R 3 The resistance of the third resistor R3.
Optionally, the third resistor R3 is determined as follows:
R 3 ＝R P +R N
R P ＝R P0 +a(t)
R N ＝R N0 +b(t)
wherein R is P Resistance with positive temperature coefficient, R N Resistance with negative temperature coefficient, R P0 Is the fixed resistance value of the positive temperature coefficient resistor, R N0 Is the fixed resistance of the negative temperature coefficient resistor; a (t) > 0 and is a function proportional to the temperature t, b (t) < 0 and is a function inversely proportional to the temperature t, and a (t) +b (t) =0, the resistance value of the obtained third resistor R3 is the resistance value of the zero temperature coefficient resistor.
The application has the beneficial effects that:
on the one hand, the conventional method of using an amplifier as a buffer to obtain the zero temperature coefficient current often needs at least more than 9 MOS transistors to achieve the zero temperature coefficient current. The circuit provided by the application can obtain zero temperature coefficient current by using only 4 MOS transistors and 2 triodes, and the number of the tubes used by the circuit is reduced, so that the power consumption of the whole circuit is reduced.
In another aspect, the present application is operated by a first positive temperature current I 1 And a second positive temperature current I 2 The zero temperature coefficient current I is formed by combining, and the third resistor R3 adopts the combination of the positive temperature resistor and the negative temperature resistor, so that the influence of the resistor on the temperature coefficient when the zero temperature coefficient current is obtained is eliminated.
In summary, the circuit of the application not only obtains zero temperature coefficient current by reducing the use of the tube, but also reduces the power consumption of the whole circuit due to the reduction of the tube, and eliminates the influence of the resistor on the temperature coefficient by the zero temperature coefficient current by adopting the combination of the positive temperature resistor and the negative temperature resistor.
Drawings
FIG. 1 is a schematic diagram of a zero temperature coefficient current generation circuit.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The term "and/or" herein is an association relationship describing an associated object, and means that there may be three relationships, for example, a and/or B may mean: a exists alone, A and B exist together, and B exists alone. The symbol "/" herein indicates that the associated object is or is a relationship, e.g., A/B indicates A or B.
The terms first and second and the like in the description and in the claims, are used for distinguishing between different objects and not necessarily for describing a particular sequential or chronological order of the objects. For example, the first transistor and the second transistor, etc., are used to distinguish between different transistors, and are not used to describe a particular order of thresholds.
In embodiments of the application, words such as "exemplary" or "such as" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "e.g." in an embodiment should not be taken as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.
The zero temperature coefficient current generation circuit provided by the embodiment of the application is suitable for the following scenes:
scene 1: in various types of DC/DC converters in power management circuits.
Scene 2: the protection circuit such as an overcurrent protection circuit and a zero current protection circuit which need zero temperature coefficient current.
Scene 3: in the scenario of reducing chip thermal effects.
As shown in fig. 1, the embodiment of the application provides a zero temperature coefficient current generating circuit, which consists of four PMOS transistors, two triodes and three resistors; the method comprisesThe zero temperature coefficient current generating circuit includes: a first circuit comprising a first triode Q1, a first resistor R1 and a second resistor R2 for generating a first positive temperature current I 1 The method comprises the steps of carrying out a first treatment on the surface of the A second circuit comprising a second triode Q2 and a third resistor R3 for generating a second positive temperature current I 2 The method comprises the steps of carrying out a first treatment on the surface of the A third circuit composed of a first PMOS tube M1, a second PMOS tube M2, a third PMOS tube M3, and a fourth PMOS tube M4 for supplying a first positive temperature current I 1 And a second positive temperature current I 2 Combined into zero temperature coefficient current I.
The first circuit, the second circuit and the third circuit are connected in pairs, the third resistor R3 is obtained by adopting a combination of a positive temperature resistor and a negative temperature resistor, and the influence of the third resistor R3 on a temperature coefficient on the zero temperature coefficient current I can be eliminated.
Alternatively, as shown in fig. 1, in the first circuit: the base electrode of the first triode Q1 is connected with a fixed reference voltage V; the collector electrode of the first triode Q1 is sequentially connected with the drain electrode of the second PMOS tube M2 and the drain electrode of the third PMOS tube M3 and is connected to the grid electrode of the third PMOS tube M3 and the grid electrode of the fourth PMOS tube M4; the emitter of the first triode Q1 is connected with one end of a first resistor R1, the other end of the first resistor R1 is connected with a second resistor R2, and the other end of the second resistor R2 is grounded.
Wherein, the first circuit is used for generating a first positive temperature current I 1 For a specific calculation formula, see formula (1) in the following examples.
Optionally, as shown in fig. 1, in the second circuit: the base electrode of the second triode Q2 is connected with the junction of the first resistor R1 and the second resistor R2, the collector electrode of the second triode Q2 is connected with the drain electrode of the first PMOS tube M1 and is connected to the grid electrode of the second PMOS tube M2, and the emitter electrode of the second triode Q2 is connected with the third resistor R3; one end of the third resistor R3 is connected with the emitter of the second triode Q2, and the other end of the third resistor R is grounded.
Wherein the second circuit is used for generating a second positive temperature current I 2 For a specific calculation formula, see formula (3) in the following examples.
Optionally, as shown in fig. 1, in the third circuit: the grid electrode of the first PMOS tube M1 is connected with the grid electrode of the second PMOS tube M2 and is connected to the drain electrode of the first PMOS tube M1, the drain electrode of the first PMOS tube M1 is connected with the collector electrode of the second triode Q2 and is connected to the grid electrode of the first PMOS tube M1, and the source electrode of the first PMOS tube M1 is connected with the power supply end VDD; the grid electrode of the second PMOS tube M2 is connected with the grid electrode of the first PMOS tube M1 and is connected to the drain electrode of the first PMOS tube M1, the drain electrode of the second PMOS tube M2 is connected with the collector electrode of the first triode Q1 and is connected to the drain electrode of the third PMOS tube M3, the grid electrode of the third PMOS tube M3 and the grid electrode of the fourth PMOS tube M4, and the source electrode of the second PMOS tube M2 is connected with the power end VDD; the grid electrode of the third PMOS tube M3 is connected with the grid electrode of the fourth PMOS tube M4 and is connected with the drain electrode of the second PMOS tube M2, the collector electrode of the first triode Q1 and the drain electrode of the third PMOS tube M3, the drain electrode of the third PMOS tube M3 is connected with the grid electrode of the third PMOS tube M3 and is connected with the drain electrode of the second PMOS tube M2, the collector electrode of the first triode Q1 and the grid electrode of the fourth PMOS tube M4, and the source electrode of the third PMOS tube M3 is connected with the power supply end VDD; the grid electrode of the fourth PMOS tube M4 is connected with the grid electrode of the third PMOS tube M3 and is connected to the drain electrode of the second PMOS tube M2, the collector electrode of the first triode Q1 and the drain electrode of the third PMOS tube M3, the source electrode of the fourth PMOS tube M4 is connected with the power supply end VDD, and the drain electrode of the fourth PMOS tube M4 is output.
Wherein, the first positive temperature current I 1 And a second positive temperature current I 2 Combined into zero temperature coefficient current I, the specific calculation formula is shown in the following formula (5) in the examples.
Optionally, as shown in fig. 1, the power supply voltage is VDD, the input fixed reference voltage is V, and the first positive temperature current I is obtained according to the first circuit 1 The calculation formula of (2) is as follows:
wherein V is a fixed reference voltage, V BEQ1 The emitter base voltage of the first triode Q1, R1 and R2 are respectively the resistance value of the first resistor R1 and the resistance value of the second resistor R2.
Alternatively, as shown in FIG. 1, the voltage V at the X point at the junction of the first circuit and the second circuit X The calculation formula is as follows:
alternatively, as shown in FIG. 1, according to the second circuit, V BE ＝V BEQ1 ＝V BEQ2 Therefore, the formula (2) is simplified to obtain the formula (3), and the calculation formula for obtaining the second positive temperature current is as follows:
wherein V is BEQ2 Is the emitter base voltage of the second transistor Q2.
Optionally, as shown in FIG. 1, the combined current I and the first normal temperature current I are obtained according to a third circuit 1 Second positive temperature current I 2 The following relationship exists:
I＝I 1 -I 2 (4)
bringing equations (1) and (3) into equation (4) yields:
since the combined current I is zero temperature coefficient current, let (R 1 +2R 2 -R 3 ) =0, thereby eliminating V BE Further, the resistance of the first resistor R1, the resistance of the second resistor R2, and the resistance of the third resistor R3 are obtained, and the following relationship exists:
R 1 +2R 2 ＝R 3 (6)
the above equation (6) is brought into equation (5) to be simplified to obtain:
as the fixed reference voltage is V constant, as can be seen from the formula (7), the zero temperature coefficient current I is only related to the resistance value of the third resistor R3, so that the application adopts the combined design of the positive temperature resistor and the negative temperature resistor for the third resistor R3 to eliminate the influence of the zero temperature coefficient current I on the temperature coefficient by the third resistor R3.
Specifically, the third resistor R3 is determined as follows:
R 3 ＝R P +R N (8)
R P ＝R P0 +a(t) (9)
R N ＝R N0 +b(t) (10)
wherein R is P Resistance with positive temperature coefficient, R N Resistance with negative temperature coefficient, R P0 Is the fixed resistance value of the positive temperature coefficient resistor, R N0 Is the fixed resistance of the negative temperature coefficient resistor; a (t) > 0 and is a function proportional to the temperature t, and b (t) < 0 and is a function inversely proportional to the temperature t.
By introducing the formula (9) and the formula (10) into the formula (8), the third resistor R3 can be obtained from the fixed resistance value (R P0 +R N0 ) In order to eliminate the influence of the current I on the temperature coefficient by the third resistor R3, the resistance of the third resistor R3 is not influenced by the temperature change, i.e., the zero temperature coefficient current I is obtained according to the formula (7), by making a (t) +b (t) =0.
It can be understood that the zero temperature coefficient current generating circuit is designed according to the negative temperature characteristic of the triode, and generates two positive temperature currents to be subtracted to obtain zero temperature coefficient current under the condition that an amplifier is not needed to be used as a buffer, and the quantity of MOS (metal oxide semiconductor) tubes is saved. Because the circuit area of the application is small, the design cost is low, no extra bias current is needed, and the application can be used for any circuit which needs zero temperature coefficient current, such as an overcurrent protection circuit, a zero current protection circuit and the like.
The zero temperature coefficient current generation circuit provided by the embodiment of the application only comprises four PMOS tubes, two triodes and three resistors; according to the negative temperature characteristic of the triode, the first circuit and the second circuit are respectively designed by using two triodes to obtain a first positive temperature current I 1 And a second positive temperature current I 2 The third circuit is designed by using four PMOS tubesThe two positive temperature currents are combined into a zero temperature coefficient current I. In addition, in order to eliminate the influence of the zero temperature coefficient current I on the temperature coefficient by the third resistor R3, the third resistor R3 is obtained by using a combination of a positive temperature resistor and a negative temperature resistor. Through the design, on one hand, the traditional method for acquiring the zero temperature coefficient current by using the amplifier as the buffer can be realized by using at least more than 9 MOS (metal oxide semiconductor) tubes, and the circuit provided by the application can acquire the zero temperature coefficient current by using only 4 MOS tubes and 2 triodes, so that the number of tubes used by the circuit is reduced, and the power consumption of the whole circuit is reduced. In another aspect, the present application is operated by a first positive temperature current I 1 And a second positive temperature current I 2 The zero temperature coefficient current I is formed by combining, and the third resistor R3 adopts the combination of the positive temperature resistor and the negative temperature resistor, so that the influence of the resistor on the temperature coefficient when the zero temperature coefficient current is obtained is eliminated.
The embodiments given above are preferred examples for realizing the present application, and the present application is not limited to the above-described embodiments. Any immaterial additions and substitutions made by those skilled in the art according to the technical features of the technical scheme of the application are all within the protection scope of the application.
Claims (4)
1. The zero temperature coefficient current generation circuit is characterized by comprising four PMOS tubes, two triodes and three resistors; the zero temperature coefficient current generation circuit includes:
a first circuit comprising a first triode Q1, a first resistor R1 and a second resistor R2 for generating a first positive temperature current I 1 ；
A second circuit comprising a second triode Q2 and a third resistor R3 for generating a second positive temperature current I 2 ；
A third circuit composed of a first PMOS tube M1, a second PMOS tube M2, a third PMOS tube M3, and a fourth PMOS tube M4 for supplying the first positive temperature current I 1 And the second positive temperature current I 2 Combining into zero temperature coefficient current I;
in the first circuit:
the base electrode of the first triode Q1 is connected with a fixed reference voltage V; the collector electrode of the first triode Q1 is sequentially connected with the drain electrode of the second PMOS tube M2 and the drain electrode of the third PMOS tube M3 and connected to the grid electrode of the third PMOS tube M3 and the grid electrode of the fourth PMOS tube M4;
the emitter of the first triode Q1 is connected with one end of the first resistor R1, the other end of the first resistor R1 is connected with the second resistor R2, and the other end of the second resistor R2 is grounded;
in the second circuit:
the base electrode of the second triode Q2 is connected with the junction of the first resistor R1 and the second resistor R2, the collector electrode of the second triode Q2 is connected with the drain electrode of the first PMOS tube M1 and is connected to the grid electrode of the second PMOS tube M2, and the emitter electrode of the second triode Q2 is connected with the third resistor R3;
one end of the third resistor R3 is connected with the emitter of the second triode Q2, and the other end of the third resistor R is grounded;
in the third circuit:
the grid electrode of the first PMOS tube M1 is connected with the grid electrode of the second PMOS tube M2 and is connected to the drain electrode of the first PMOS tube M1, the drain electrode of the first PMOS tube M1 is connected with the collector electrode of the second triode Q2 and is connected to the grid electrode of the first PMOS tube M1, and the source electrode of the first PMOS tube M1 is connected with the power supply end VDD;
the grid electrode of the second PMOS tube M2 is connected with the grid electrode of the first PMOS tube M1 and is connected to the drain electrode of the first PMOS tube M1, the drain electrode of the second PMOS tube M2 is connected with the collector electrode of the first triode Q1 and is connected to the drain electrode of the third PMOS tube M3, the grid electrode of the third PMOS tube M3 and the grid electrode of the fourth PMOS tube M4, and the source electrode of the second PMOS tube M2 is connected with the power supply end VDD;
the grid electrode of the third PMOS tube M3 is connected with the grid electrode of the fourth PMOS tube M4 and is connected with the drain electrode of the second PMOS tube M2, the collector electrode of the first triode Q1 and the drain electrode of the third PMOS tube M3, the drain electrode of the third PMOS tube M3 is connected with the grid electrode of the third PMOS tube M3 and is connected with the drain electrode of the second PMOS tube M2, the collector electrode of the first triode Q1 and the grid electrode of the fourth PMOS tube M4, and the source electrode of the third PMOS tube M3 is connected with the power supply end VDD;
the grid electrode of the fourth PMOS tube M4 is connected with the grid electrode of the third PMOS tube M3 and is connected to the drain electrode of the second PMOS tube M2, the collector electrode of the first triode Q1 and the drain electrode of the third PMOS tube M3, the source electrode of the fourth PMOS tube M4 is connected with the power supply end VDD, and the drain electrode of the fourth PMOS tube M4 is output;
the first circuit, the second circuit and the third circuit are connected in pairs; the third resistor R3 is obtained by adopting a combination of a positive temperature resistor and a negative temperature resistor, so that the influence of the third resistor R3 on the temperature coefficient of the zero temperature coefficient current I can be eliminated.
2. The circuit according to claim 1, wherein the first resistor R1 has a resistance R 1 Resistance value R of the second resistor R2 2 And the resistance value R of the third resistor R3 3 There is the following relationship:
R 1 +2R 2 ＝R 3 。
3. the circuit of claim 1, wherein the zero temperature coefficient current I is obtained according to the zero temperature coefficient current generation circuit by the following calculation formula:
wherein I is 1 For the first positive temperature current generated by the first circuit, I 2 The second positive temperature current generated by the second circuit is V is a fixed reference voltage, R 3 Is the resistance value of the third resistor R3.
4. The circuit of claim 1, wherein the third resistor R3 is determined as follows:
R 3 ＝R P +R N
R P ＝R P0 +a(t)
R N ＝R N0 +b(t)
wherein R is P Resistance with positive temperature coefficient, R N Resistance with negative temperature coefficient, R P0 Is the fixed resistance value of the positive temperature coefficient resistor, R N0 Is the fixed resistance of the negative temperature coefficient resistor; a (t) > 0 and is a function proportional to the temperature t, b (t) < 0 and is a function inversely proportional to the temperature t, and a (t) +b (t) =0, the resistance of the third resistor R3 is zero temperature coefficient resistance.
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| CN113093855A (en) * | 2021-03-26 | 2021-07-09 | 华中科技大学 | Low-power-consumption wide-voltage-range ultra-low-voltage reference source circuit |
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| KR102391518B1 (en) * | 2015-09-15 | 2022-04-27 | 삼성전자주식회사 | Circuit for generating reference current and semiconductor integrated circuit having the same |
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