CN116404895A - Split inductance type asymmetric double-output multi-level converter topology circuit - Google Patents

Split inductance type asymmetric double-output multi-level converter topology circuit Download PDF

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Publication number
CN116404895A
CN116404895A CN202310234487.9A CN202310234487A CN116404895A CN 116404895 A CN116404895 A CN 116404895A CN 202310234487 A CN202310234487 A CN 202310234487A CN 116404895 A CN116404895 A CN 116404895A
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switching tube
split
output circuit
output
circuit
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CN202310234487.9A
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Inventor
李湘峰
詹胜强
郭芳
林聪�
祝姗姗
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Foshan University
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Foshan University
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Priority to CN202310234487.9A priority Critical patent/CN116404895A/en
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H02M7/53871—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H02M7/487—Neutral point clamped inverters

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)

Abstract

The invention relates to a split inductance type asymmetric double-output multi-level converter topological circuit, which comprises a first split inductance branch, a second split inductance branch, a first output circuit and a second output circuit; the first split inductance branch and the second split inductance branch are sequentially connected with an input power supply in parallel, one end of the first output circuit is connected with the positive electrode of the input power supply, and one end of the second output circuit is connected with the negative electrode of the input power supply; the first split circuit branch and the second split inductance branch are connected with the first output circuit and the second output circuit, and the first output circuit or the second output circuit is selected to output different level voltages by adjusting the switching state of a switching tube in the first split inductance branch or the second split inductance branch. The whole topological circuit is simple, the split inductance branch circuit is adopted, the problem of uneven voltage division of the direct-current side capacitor is not needed to be considered, and meanwhile, two paths of single-phase three-level alternating voltage with adjustable amplitude and frequency can be output by using fewer switching tubes.

Description

Split inductance type asymmetric double-output multi-level converter topology circuit
Technical Field
The invention relates to the technical field of electric energy conversion, in particular to a split inductance type asymmetric double-output multi-level converter topology circuit.
Background
The efficiency is high, the cost is low, which is one of the principles that researchers follow when designing the power electronic converter, in different electric energy conversion technical fields, each alternating current load is often required to be provided with an inverter, and the volume and the cost of electric equipment are increased; in order to improve the quality and the reliability of the system, the prior art proposes a nine-switch inverter and a three-phase T-shaped three-level double-output inverter, both the two inverters can output three-phase alternating voltage with two paths of amplitude and frequency adjustable, and the difference is that the nine-switch inverter can only output two levels, the three-phase T-shaped three-level double-output inverter can output three levels, but more switching tubes, such as 21 switching tubes, are needed, so that the switching tubes needed by the whole circuit are more, the circuit is complicated and the volume is increased, and when the upper and lower two paths of output are realized, the voltage of two capacitors on the input side has larger fluctuation, and the balance control on the capacitor voltage on the direct current side is needed, so that the complexity and the volume of the circuit are further increased.
It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the present disclosure and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
The invention aims to overcome the defects of the prior art, provides a split inductance type asymmetric double-output multi-level converter topology circuit, and solves the problems of more switching tubes, complex circuits and large volume in the prior art.
The aim of the invention is achieved by the following technical scheme: a split inductance type asymmetric double-output multi-level converter topology circuit comprises a first split inductance branch, a second split inductance branch, a first output circuit and a second output circuit;
the first split inductance branch and the second split inductance branch are sequentially connected with an input power supply in parallel, a switching tube shared by the two output circuits is arranged in the first output circuit and the second output circuit, one end of the first output circuit is connected with the positive electrode of the input power supply, and one end of the second output circuit is connected with the negative electrode of the input power supply;
the first split inductance branch circuit and the second split inductance branch circuit are connected with the first output circuit and the second output circuit, and the first output circuit or the second output circuit is selected to output different level voltages by adjusting the opening and closing states of the switching tubes in the first split inductance branch circuit or the second split inductance branch circuit.
The first split inductance branch comprises a first split inductance, a first diode, a third diode, a seventh switching tube and a ninth switching tube;
the collector of the seventh switching tube is connected with the anode of the input power supply and the cathode of the first diode, the emitter is connected with one end of the first split inductor and the cathode of the third diode, the collector of the ninth switching tube is connected with the other end of the first split inductor and the anode of the first diode, and the emitter is connected with the cathode of the input power supply and the anode of the third diode.
The second split inductance branch comprises a second split inductance, a second diode, a fourth diode, an eighth switching tube and a tenth switching tube;
the collector of the eighth switching tube is connected with the positive electrode of the input power supply and the cathode of the second diode, the emitter is connected with one end of the second split inductor and the cathode of the fourth diode, the collector of the tenth switching tube is connected with the other end of the second split inductor and the anode of the second diode, and the emitter is connected with the negative electrode of the input power supply and the anode of the fourth diode.
The first output circuit comprises a first switching tube, a second switching tube, a third switching tube and a fourth switching tube;
the first switching tube and the third switching tube are connected in series to form a first bridge arm of the first output circuit, the second switching tube and the fourth switching tube are connected in series to form a second bridge arm of the first output circuit, the collectors of the first switching tube and the second switching tube are both connected with the positive electrode of an input power supply, the emitter of the first switching tube is connected with the collector of the third switching tube, the emitter of the second switching tube is connected with the collector of the fourth switching tube, the midpoint of the first split inductor is connected with the midpoint of the first bridge arm and leads out a node which is used as an output end A of the first output circuit, the midpoint of the second split inductor is connected with the midpoint of the second bridge arm and leads out another node which is used as an output end B of the first output circuit; the first output circuit realizes the output of multiple level voltages by adjusting and controlling the switching states of the switching tubes in the first split inductance branch and/or the second split inductance branch.
The second output circuit comprises a third switching tube, a fourth switching tube, a fifth switching tube and a sixth switching tube;
the third switching tube and the fifth switching tube are connected in series to form a first bridge arm of the second output circuit, the fourth switching tube and the sixth switching tube are connected in series to form a second bridge arm of the second output circuit, the emitters of the third switching tube and the fourth switching tube are connected with the negative electrode of the input power supply, the middle point of the first bridge arm is connected and led out to form a node which is used as an output end C of the second output circuit, the middle point of the second bridge arm is connected and led out to form another node which is used as an output end D of the second output circuit; the second output circuit realizes the output of multiple level voltages by adjusting and controlling the switching states of the switching tubes in the first split inductance branch and/or the second split inductance branch.
The first split inductor comprises two inductors connected in series, 1/2 direct current bus voltage is obtained through voltage division of the two inductors connected in series, and the midpoint of a first bridge arm of a first output circuit formed by connecting the first switching tube and the third switching tube in series is connected with the midpoint of the two inductors connected in series;
the second split inductor comprises two inductors connected in series, 1/2 direct current bus voltage is obtained through voltage division of the two inductors connected in series, and the midpoint of the second bridge arm of the first output circuit formed by connecting the second switching tube and the fourth switching tube in series is connected with the midpoint of the two inductors connected in series.
The invention has the following advantages: the split inductance type asymmetric double-output multi-level converter topology circuit is simple, the split inductance branch circuit is adopted, the problem of uneven voltage division of direct current side capacitance is not needed to be considered, meanwhile, two paths of single-phase three-level alternating voltage with adjustable amplitude and frequency can be output by using fewer switching tubes, and the split inductance type asymmetric double-output multi-level converter topology circuit can be used for new energy power generation, independent control of double-alternating-current motors and other scenes needing double alternating current.
Drawings
FIG. 1 is a circuit topology of the present invention;
FIG. 2 is a circuit topology diagram of the first output circuit output (load) voltage Vcc;
FIG. 3 is a circuit topology diagram of the first output circuit output (load) voltage Vcc/2;
FIG. 4 is a circuit topology diagram of the first output circuit when the output (load) voltage is 0;
FIG. 5 is a circuit topology diagram of the first output circuit output (load) voltage at-Vcc/2;
FIG. 6 is a circuit topology diagram of the first output circuit output (load) voltage at Vcc;
FIG. 7 is a circuit topology diagram of the second output circuit output (load) voltage Vcc;
FIG. 8 is a circuit topology diagram of the second output circuit output (load) voltage Vcc/2;
FIG. 9 is a circuit topology diagram of the second output circuit when the output (load) voltage is 0;
FIG. 10 is a circuit topology diagram of the second output circuit output (load) voltage at-Vcc/2;
fig. 11 is a circuit topology diagram of the second output circuit output (load) voltage at-Vcc.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations. Accordingly, the following detailed description of the embodiments of the present application, provided in connection with the accompanying drawings, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, are intended to be within the scope of the present application. The invention is further described below with reference to the accompanying drawings.
As shown in fig. 1, the present invention specifically relates to a split inductor type asymmetric dual-output multi-level converter topology circuit, which comprises a first split inductor branch, a second split inductor branch, a first output circuit and a second output circuit;
the first split inductance branch and the second split inductance branch are sequentially connected with an input power supply in parallel, a switching tube shared by the two output circuits is arranged in the first output circuit and the second output circuit, one end of the first output circuit is connected with the positive electrode of the input power supply, and one end of the second output circuit is connected with the negative electrode of the input power supply;
the first split inductance branch and the second split inductance branch are connected with the first output circuit and the second output circuit, and the first output circuit or the second output circuit is selected to output different level voltages by adjusting the opening and closing states of switching tubes in the first split inductance branch and/or the second split inductance branch.
Further, the first split inductor branch comprises a first split inductor, a first diode, a third diode, a seventh switching tube and a ninth switching tube;
the collector of the seventh switching tube is connected with the anode of the input power supply and the cathode of the first diode, the emitter is connected with one end of the first split inductor and the cathode of the third diode, the collector of the ninth switching tube is connected with the other end of the first split inductor and the anode of the first diode, and the emitter is connected with the cathode of the input power supply and the anode of the third diode.
Further, the second split inductor branch comprises a second split inductor, a second diode, a fourth diode, an eighth switching tube and a tenth switching tube;
the collector of the eighth switching tube is connected with the positive electrode of the input power supply and the cathode of the second diode, the emitter is connected with one end of the second split inductor and the cathode of the fourth diode, the collector of the tenth switching tube is connected with the other end of the second split inductor and the anode of the second diode, and the emitter is connected with the negative electrode of the input power supply and the anode of the fourth diode.
Further, the first output circuit comprises a first switching tube, a second switching tube, a third switching tube and a fourth switching tube;
the first switching tube and the third switching tube are connected in series to form a first bridge arm of the first output circuit, the second switching tube and the fourth switching tube are connected in series to form a second bridge arm of the first output circuit, the collectors of the first switching tube and the second switching tube are both connected with the positive electrode of an input power supply, the emitter of the first switching tube is connected with the collector of the third switching tube, the emitter of the second switching tube is connected with the collector of the fourth switching tube, the midpoint of the first split inductor is connected with the midpoint of the first bridge arm and leads out a node which is used as an output end A of the first output circuit, the midpoint of the second split inductor is connected with the midpoint of the second bridge arm and leads out another node which is used as an output end B of the first output circuit; the first output circuit realizes the output of multiple level voltages by adjusting and controlling the switching states of the switching tubes in the first split inductance branch and/or the second split inductance branch.
Further, the second output circuit comprises a third switching tube, a fourth switching tube, a fifth switching tube and a sixth switching tube;
the third switching tube and the fifth switching tube are connected in series to form a first bridge arm of the second output circuit, the fourth switching tube and the sixth switching tube are connected in series to form a second bridge arm of the second output circuit, the emitters of the third switching tube and the fourth switching tube are connected with the negative electrode of an input power supply, the middle point of the first bridge arm is connected and led out to form a node which is used as an output end C of the second output circuit, the middle point of the second bridge arm is connected and led out to form another node which is used as an output end D of the second output circuit; the second output circuit realizes the output of multiple level voltages by adjusting and controlling the switching states of the switching tubes in the first split inductance branch and/or the second split inductance branch.
Further, the first split inductor comprises two inductors connected in series, 1/2 direct current bus voltage is obtained through voltage division of the two inductors connected in series, and the midpoint of a first bridge arm of a first output circuit formed by connecting the first switching tube and the third switching tube in series is connected with the midpoint of the two inductors connected in series; the second split inductor comprises two inductors connected in series, the voltage of the direct current bus bar of 1/2 is obtained through the voltage division of the two inductors connected in series, and the midpoint of the second bridge arm of the first output circuit formed by connecting the second switching tube and the fourth switching tube in series is connected with the midpoint of the two inductors connected in series.
For the first output circuit, the output level condition thereof is as shown in fig. 2 to 6.
As shown in fig. 2, the first switching tube, the fourth switching tube, the fifth switching tube and the sixth switching tube are turned on, the second switching tube, the third switching tube, the seventh switching tube, the eighth switching tube, the ninth switching tube and the tenth switching tube are turned off, the voltage at the point a of the output end is located at the positive electrode Vcc of the input power supply by the first switching tube and the fifth switching tube clamp, and the voltage at the point B of the output end is located at the negative electrode of the power supply by the fourth switching tube and the sixth switching tube clamp, that is, the output (load) voltage is Vcc.
As shown in fig. 3, the fourth switching tube, the fifth switching tube, the sixth switching tube, the seventh switching tube and the ninth switching tube are turned on, the first switching tube, the second switching tube, the third switching tube, the eighth switching tube and the tenth switching tube are cut off, the voltage at the point a of the output end is located at Vcc/2 by the first split inductance branch clamp, and the voltage at the point B of the output end is located at the negative electrode of the power supply by the fourth switching tube and the sixth switching tube clamp, that is, the output (load) voltage is Vcc/2.
As shown in fig. 4, the third switching tube, the fourth switching tube, the fifth switching tube and the sixth switching tube are turned on, the first switching tube, the second switching tube, the seventh switching tube, the eighth switching tube, the ninth switching tube and the tenth switching tube are turned off, the voltage at the point a of the output end is located at the negative electrode of the input power supply by the third switching tube and the fourth switching tube clamp, and the voltage at the point B of the output end is located at the negative electrode of the power supply by the fourth switching tube and the sixth switching tube clamp, namely the output (load) voltage is 0.
As shown in fig. 5, the third switching tube, the fifth switching tube, the sixth switching tube, the eighth switching tube and the tenth switching tube are turned on, the first switching tube, the second switching tube, the fourth switching tube, the seventh switching tube and the ninth switching tube are cut off, the voltage at the point a of the output end is located at the negative electrode of the input power supply by the third switching tube and the fifth switching tube clamp, and the voltage at the point B of the output end is clamped with Vcc/2 by the second split inductance branch, namely the output (load) voltage is-Vcc/2.
As shown in fig. 6, the second switching tube, the third switching tube, the fifth switching tube and the sixth switching tube are turned on, the first switching tube, the fourth switching tube, the seventh switching tube, the eighth switching tube, the ninth switching tube and the tenth switching tube are turned off, the voltage at the point a of the output end is located at the negative electrode of the input power supply by the third switching tube and the fifth switching tube clamp, and the point B of the output end is located at the positive electrode Vcc of the input power supply by the second switching tube clamp, namely the output (load) voltage is-Vcc.
As for the second output circuit, the output level thereof is as shown in fig. 7 to 11.
As shown in fig. 7, the first switching tube, the second switching tube, the third switching tube and the sixth switching tube are turned on, the fourth switching tube, the fifth switching tube, the seventh switching tube, the eighth switching tube, the ninth switching tube and the tenth switching tube are turned off, the voltage at the point C of the output end is located at the input power Vcc by the first switching tube and the third switching tube clamp, and the voltage at the point D of the output end is located at the negative electrode of the input power by the sixth diode clamp, that is, the output (load) voltage is Vcc.
As shown in fig. 8, the third switching tube, the sixth switching tube, the seventh switching tube, the eighth switching tube, the ninth switching tube and the tenth switching tube are turned on, the first switching tube, the second switching tube, the fourth switching tube and the fifth switching tube are cut off, the voltage at the point C of the output end is located at Vcc/2 by the first split inductor branch and the third switching tube clamp, and the voltage at the point D of the output end is located at the negative electrode of the input power supply by the sixth diode clamp, that is, the output (load) voltage is Vcc/2.
As shown in fig. 9, the fifth switching tube and the sixth switching tube are turned on, the first switching tube, the second switching tube, the third switching tube, the fourth switching tube, the seventh switching tube, the eighth switching tube, the ninth switching tube and the tenth switching tube are turned on, the voltage at the point C of the output end is located at the negative electrode of the input power supply by the fifth switching tube clamp, and the voltage at the point D of the output end is located at the negative electrode of the input power supply by the sixth switching tube clamp, that is, the output (load) voltage is 0.
As shown in fig. 10, the fourth switching tube, the fifth switching tube, the seventh switching tube, the eighth switching tube, the ninth switching tube and the tenth switching tube are turned on, the first switching tube, the second switching tube, the third switching tube and the sixth switching tube are turned off, the voltage at the point C of the output end is located at the negative electrode of the input power supply by the fifth switching tube clamp, the voltage at the point D of the output end is located at Vcc/2 by the second split inductance branch and the fourth switching tube clamp, that is, the voltage at the output (load) is-Vcc/2.
As shown in fig. 11, the first switching tube, the second switching tube, the fourth switching tube and the fifth switching tube are turned on, the third switching tube, the sixth switching tube, the seventh switching tube, the eighth switching tube, the ninth switching tube and the tenth switching tube are turned off, the voltage at the point C of the output end is located at the negative electrode of the input power supply by the fifth switching tube clamp, and the voltage at the output end D is located at the positive electrode of the input power supply by the second switching tube and the fourth switching tube clamp, that is, the output (load) voltage is-Vcc.
The invention can output three levels for two paths of output, which are respectively: vcc, vcc/2,0V. Compared with the prior art, the circuit topology structure is simple, the problem of neutral point voltage balance at the input side is not needed to be considered, and meanwhile, the total number of switching tubes is reduced, so that the overall production cost is reduced, and the overall size is reduced.
The foregoing is merely a preferred embodiment of the invention, and it is to be understood that the invention is not limited to the form disclosed herein but is not to be construed as excluding other embodiments, but is capable of numerous other combinations, modifications and environments and is capable of modifications within the scope of the inventive concept, either as taught or as a matter of routine skill or knowledge in the relevant art. And that modifications and variations which do not depart from the spirit and scope of the invention are intended to be within the scope of the appended claims.

Claims (6)

1. A split inductance type asymmetric double-output multi-level converter topological circuit is characterized in that: the circuit comprises a first split inductance branch, a second split inductance branch, a first output circuit and a second output circuit;
the first split inductance branch and the second split inductance branch are sequentially connected with an input power supply in parallel, a switching tube shared by the two output circuits is arranged in the first output circuit and the second output circuit, one end of the first output circuit is connected with the positive electrode of the input power supply, and one end of the second output circuit is connected with the negative electrode of the input power supply;
the first split inductance branch circuit and the second split inductance branch circuit are connected with the first output circuit and the second output circuit, and the first output circuit or the second output circuit is selected to output different level voltages by adjusting the opening and closing states of the switching tubes in the first split inductance branch circuit or the second split inductance branch circuit.
2. A split inductor asymmetric dual output multi-level converter topology as recited in claim 1, wherein: the first split inductance branch comprises a first split inductance, a first diode, a third diode, a seventh switching tube and a ninth switching tube;
the collector of the seventh switching tube is connected with the anode of the input power supply and the cathode of the first diode, the emitter is connected with one end of the first split inductor and the cathode of the third diode, the collector of the ninth switching tube is connected with the other end of the first split inductor and the anode of the first diode, and the emitter is connected with the cathode of the input power supply and the anode of the third diode.
3. A split-inductor asymmetric dual-output multi-level converter topology as recited in claim 2, wherein: the second split inductance branch comprises a second split inductance, a second diode, a fourth diode, an eighth switching tube and a tenth switching tube;
the collector of the eighth switching tube is connected with the positive electrode of the input power supply and the cathode of the second diode, the emitter is connected with one end of the second split inductor and the cathode of the fourth diode, the collector of the tenth switching tube is connected with the other end of the second split inductor and the anode of the second diode, and the emitter is connected with the negative electrode of the input power supply and the anode of the fourth diode.
4. A split-inductor asymmetric dual-output multi-level converter topology as recited in claim 3, wherein: the first output circuit comprises a first switching tube, a second switching tube, a third switching tube and a fourth switching tube;
the first switching tube and the third switching tube are connected in series to form a first bridge arm of the first output circuit, the second switching tube and the fourth switching tube are connected in series to form a second bridge arm of the first output circuit, the collectors of the first switching tube and the second switching tube are both connected with the positive electrode of an input power supply, the emitter of the first switching tube is connected with the collector of the third switching tube, the emitter of the second switching tube is connected with the collector of the fourth switching tube, the midpoint of the first split inductor is connected with the midpoint of the first bridge arm and leads out a node which is used as an output end A of the first output circuit, the midpoint of the second split inductor is connected with the midpoint of the second bridge arm and leads out another node which is used as an output end B of the first output circuit; the first output circuit realizes the output of multiple level voltages by adjusting and controlling the switching states of the switching tubes in the first split inductance branch and/or the second split inductance branch.
5. A split-inductor asymmetric dual-output multi-level converter topology as recited in claim 3, wherein: the second output circuit comprises a third switching tube, a fourth switching tube, a fifth switching tube and a sixth switching tube;
the third switching tube and the fifth switching tube are connected in series to form a first bridge arm of the second output circuit, the fourth switching tube and the sixth switching tube are connected in series to form a second bridge arm of the second output circuit, the emitters of the third switching tube and the fourth switching tube are connected with the negative electrode of the input power supply, the middle point of the first bridge arm is connected and led out to form a node which is used as an output end C of the second output circuit, the middle point of the second bridge arm is connected and led out to form another node which is used as an output end D of the second output circuit; the second output circuit realizes the output of multiple level voltages by adjusting and controlling the switching states of the switching tubes in the first split inductance branch and/or the second split inductance branch.
6. The split inductor type asymmetric dual-output multi-level converter topology as recited in claim 4, wherein: the first split inductor comprises two inductors connected in series, 1/2 direct current bus voltage is obtained through voltage division of the two inductors connected in series, and the midpoint of a first bridge arm of a first output circuit formed by connecting the first switching tube and the third switching tube in series is connected with the midpoint of the two inductors connected in series;
the second split inductor comprises two inductors connected in series, 1/2 direct current bus voltage is obtained through voltage division of the two inductors connected in series, and the midpoint of the second bridge arm of the first output circuit formed by connecting the second switching tube and the fourth switching tube in series is connected with the midpoint of the two inductors connected in series.
CN202310234487.9A 2023-03-10 2023-03-10 Split inductance type asymmetric double-output multi-level converter topology circuit Pending CN116404895A (en)

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CN202310234487.9A CN116404895A (en) 2023-03-10 2023-03-10 Split inductance type asymmetric double-output multi-level converter topology circuit

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CN202310234487.9A Pending CN116404895A (en) 2023-03-10 2023-03-10 Split inductance type asymmetric double-output multi-level converter topology circuit

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116632840A (en) * 2023-07-24 2023-08-22 鹏元晟高科技股份有限公司 Double-line mains supply input split phase output power supply system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116632840A (en) * 2023-07-24 2023-08-22 鹏元晟高科技股份有限公司 Double-line mains supply input split phase output power supply system
CN116632840B (en) * 2023-07-24 2024-02-20 鹏元晟高科技股份有限公司 Double-line mains supply input split phase output power supply system

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