CN116404863B - Power factor correction converter - Google Patents
Power factor correction converter Download PDFInfo
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- CN116404863B CN116404863B CN202310666077.1A CN202310666077A CN116404863B CN 116404863 B CN116404863 B CN 116404863B CN 202310666077 A CN202310666077 A CN 202310666077A CN 116404863 B CN116404863 B CN 116404863B
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- 238000003199 nucleic acid amplification method Methods 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 9
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- 229940088594 vitamin Drugs 0.000 description 3
- 229930003231 vitamin Natural products 0.000 description 3
- 235000013343 vitamin Nutrition 0.000 description 3
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
- H02M1/4208—Arrangements for improving power factor of AC input
- H02M1/4233—Arrangements for improving power factor of AC input using a bridge converter comprising active switches
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
- H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
- H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Rectifiers (AREA)
Abstract
The invention discloses a power factor correction converter, which comprises a first bridge arm and a second bridge arm which are connected into a rectifying circuit, wherein an alternating current input power supply is connected between a middle node of the first bridge arm and a middle node of the second bridge arm, and an upper pipe of the first bridge arm and an upper pipe of the second bridge arm are transistors, or a lower pipe of the first bridge arm and a lower pipe of the second bridge arm are transistors; the first circuit comprises a first resonant circuit formed by connecting a first inductor, a first capacitor and a primary winding of a transformer, a first switching tube and a second switching tube which are connected, wherein two ends of the first resonant circuit are respectively connected with the connecting ends of the first switching tube and the second switching tube and the middle node of one bridge arm. The invention has good power factor correction effect and low stress of the electric power device.
Description
Technical Field
The invention relates to the field of illumination, in particular to a power factor correction converter.
Background
As shown in fig. 1, in the passive charge pump PFC technology, a resonant circuit including a first inductor Lr, a resonant capacitor Cr, and a first capacitor C1 is assumed to be an average value of a resonant circuit current ires=io/Nps, where Io is an output current, and Nps is a turn ratio of the transformer in fig. 1; the first capacitor C1 clamps at Vbus-Vin (x) after each time it is charged from 0V to Vbus-Vin (x) until the input current commutates. The average charging current is ic=c1× (Vbus-Vin (x)) ×fs, which can be easily deduced:
Iin=Ires-Ic=Io/Nps-C1×(Vbus-Vin(x))×Fs；
when the capacitance value of C1 satisfies Io/Nps =c1×vbus×fs, iin=c1×vin (x) ×fs, the input current is a sine wave, and a good power factor effect can be obtained;
according to the input/output power pin=vital x iinrms=po/Effi,
i.e. c1×vitamins×fs×vitamins=c1×vbus×fs× Nps ×vo/Effi, vo=vitamins 2/Vbus/Nps ×effi;
wherein Vin (x) and Vbus are respectively an input voltage and a bus voltage, virms and Iinrms are respectively an effective value of the input voltage and an effective value of the input current, fs is a charging frequency of the capacitor C1, and Effi is output efficiency.
According to the above analysis, vbus and Vo are inversely related under the same input voltage condition, which means that when the output voltage is low, the bus voltage will be very high, and the device stress is very large, which is a fatal defect of the passive charge pump. In addition, when the input voltage changes, iin changes, vbus changes, and the input current cannot continue to maintain sine, which affects the effect of power factor correction.
Disclosure of Invention
The invention aims to provide a power factor correction converter which can adjust the magnitude of input current to enable the input current to approach a sine wave, achieve the aim of better power factor correction, and can also adjust and stabilize bus voltage to avoid the problem of overlarge stress of a power device.
To achieve the above object, the present invention provides a power factor correction converter including,
the rectifier circuit comprises a first bridge arm and a second bridge arm, wherein an alternating current input power supply is connected between a middle node of the first bridge arm and a middle node of the second bridge arm, and an upper pipe of the first bridge arm and an upper pipe of the second bridge arm are transistors, or a lower pipe of the first bridge arm and a lower pipe of the second bridge arm are transistors;
the first circuit comprises a first switching tube and a second switching tube which are connected, a first resonant circuit formed by connecting a first inductor, a first capacitor and a primary winding of a transformer, wherein a first end of the first resonant circuit is connected with a common connection end of the first switching tube and a common connection end of the second switching tube, and a second end of the first resonant circuit is connected with an intermediate node of a bridge arm;
the control circuit is used for carrying out error amplification on an output feedback signal and a reference signal to obtain a first error signal, generating a first coefficient according to half-wave voltage obtained by rectifying the bus voltage and the alternating input voltage, and obtaining the compensation signal according to the product of the first error signal and the first coefficient; and controlling the working state of the transistor according to the input voltage and the compensation signal.
Optionally, the bridge further comprises a second capacitor, wherein the first end of the second capacitor is connected with the first end of the first capacitor, and the second end of the second capacitor is connected with the intermediate node of the other bridge arm.
Optionally, the first capacitor and the second capacitor are equal in size.
Optionally, the upper tube and the lower tube of the first bridge arm are transistors, and the upper tube of the second bridge arm
And the down tube is also a transistor.
Optionally, the control circuit obtains a first ratio according to a ratio of a difference value between the bus voltage and the half-wave voltage to the bus voltage, and generates the first coefficient according to the first ratio.
Optionally, the first control circuit obtains a product of the first ratio and the second coefficient
To the first coefficient; and obtaining the second coefficient according to the bus voltage, the bus reference voltage and the deviation coefficient.
Optionally, the second coefficient is set toWhere Vbus is the bus voltage, vbus_ref is the bus reference voltage, and Kd is the offset coefficient.
Optionally, the deviation coefficient is set to a constant smaller than 1, and a peak value of the second coefficient is larger than 0.5 and smaller than 2.
Optionally, the control circuit compares the first error signal and the first ramp signal to control the switching states of the first switching tube and the second switching tube.
Optionally, the transformer comprises an output circuit, wherein the output circuit comprises a transformer secondary winding, a rectifying tube, an output capacitor and a load, the transformer secondary winding is connected with the rectifying tube in series and then connected with the output capacitor in parallel, and the load is connected with the output capacitor; and after the current of the primary winding of the transformer is freewheeling to zero, the rectifying tube is conducted.
Compared with the prior art, the technical scheme of the invention has the following advantages: an active transistor is introduced to set a power factor correction converter, and the on time of the transistor can be controlled at different positions of power frequency input, so that the input current is close to sine wave, and the aim of better power factor correction is achieved; the average on time of the transistor can be controlled to adjust the voltage of the stable bus, so that the device stress is avoided.
Drawings
FIG. 1 is a schematic diagram of a prior art PFC converter;
FIG. 2 is a schematic diagram of an embodiment 1 of a PFC converter according to the present invention;
FIG. 3 is a schematic diagram of an embodiment 2 of a PFC converter according to the present invention;
FIG. 4 is a schematic diagram of an embodiment 3 of a PFC converter according to the present invention;
fig. 5 is a schematic diagram of a control circuit of the pfc converter of the present invention.
Detailed Description
The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, but the present invention is not limited to these embodiments only. The invention is intended to cover any alternatives, modifications, equivalents, and variations that fall within the spirit and scope of the invention.
In the following description of preferred embodiments of the invention, specific details are set forth in order to provide a thorough understanding of the invention, and the invention will be fully understood to those skilled in the art without such details.
The invention is more particularly described by way of example in the following paragraphs with reference to the drawings. It should be noted that the drawings are in a simplified form and are not to scale precisely, but rather are merely intended to facilitate and clearly illustrate the embodiments of the present invention.
As shown in fig. 2, a schematic diagram of an embodiment 1 of the power factor correction converter of the present invention is illustrated, which includes a rectifying circuit input capacitor Cbus and a resonant circuit, where the rectifying circuit includes a first bridge arm and a second bridge arm, each bridge arm includes an upper tube (diode) D1, D2 and a lower tube (transistor) M4, M3 that are connected, a connection end of each bridge arm upper tube and lower tube is an intermediate node of the bridge arm, an ac input power Vin is connected between the intermediate node of the first bridge arm and an intermediate node of the second bridge arm, the lower tubes of the two bridge arms are transistors, in another embodiment, the upper tubes of the two bridge arms are transistors, and the transistors are preferably NMOS tubes, or may be three-terminal switching tubes such as triodes and thyristors. The input capacitor Cbus and the output end of the rectifying circuit are connected in parallel, and the bus voltage Vbus is obtained after the alternating current input voltage Vin passes through the rectifying circuit and the input capacitor Cbus. The resonant circuit comprises a bridge type switching tube, a first inductor Lr, a first capacitor Cr1 and a primary winding of a transformer T, the bridge type switching tube also comprises an upper tube M1 and a lower tube M2 which are connected, the upper tube M1 and the lower tube M2 are switching tubes, and NMOS tubes are preferred, as shown in figure 2, the connecting ends of the upper tube M1 and the lower tube M2 of the bridge type switching tube are connected with the first inductor Lr, the first capacitor Cr1 and the primary winding of the transformer to form a first end of the first resonant circuit, and the second end of the first resonant circuit is connected with the middle node of one bridge arm of the rectifying circuit. The secondary side of the transformer is connected with a synchronous rectifying diode D2 and a load. The converter further comprises a control circuit for controlling the on-off state of each switching tube of the converter according to the output feedback voltage FB, the first reference voltage Vref, the bus voltage Vbus, the half-wave voltage Vre obtained by rectifying the input current and the input voltage. Taking the example of the alternating current input voltage Vin in the positive half wave, the switching tube M4 of the converter is normally closed, the switching tubes M1 and M2 are complementarily conducted, and the specific working mode is as follows:
in the first stage, the switching tubes M1 and M3 are turned on, the M2 is turned off, the first inductor Lr is charged, and current flows through the input current Cbus, the switching tube M1, the first inductor Lr, the primary winding of the transformer, the first capacitor Cr1, the switching tube M3 and the reference ground;
in the second stage, the switching tube M1 is turned on, the switching tubes M2 and M3 are turned off, the first inductor Lr freewheels, and current flows through the rectifier diode D1, the switching tube M1, the first inductor Lr, the primary winding of the transformer, the first capacitor Cr1 and the power grid;
in the third stage, the switching tubes M1 and M3 are turned off, the M2 is turned on, the first inductor Lr is freewheeled to zero, and current flows through the M2, the first inductor Lr, the primary winding of the transformer, the first capacitor Cr1, the power grid, the rectifier circuit diode D1, the input capacitor Cbus and the reference ground;
in the fourth stage, the switching tubes M1 and M3 are turned off, the M2 is turned on, the current is reversed after the first inductor Lr freewheels to zero, and the current flows through the switching tube M2, the body diode of the switching tube M3, the first capacitor Cr1, the primary winding of the transformer and the first inductor Lr;
in the fifth stage, the switching tubes M1 and M3 are turned on, the switching tube M2 is turned off, the inductance current of the first inductor Lr is reversed, the inductance current is freewheeling, and the current flows through the switching tube M1, the input capacitor Cbus, the reference ground, the switching tube M3, the first capacitor Cr1, the primary winding of the transformer and the first inductor Lr.
When the ac input voltage Vin is in the negative half-wave, the switching tube M3 is normally closed, and the specific working principle is referred to the above analysis, and will not be described here. According to the working principle of the power factor correction converter, when the first inductor Lr is charged with current, the current of the input capacitor Cbus can be controlled by controlling the on time of the switching tube M3 when the input voltage Vin is positive and the on time of the switching tube M4 when the input voltage Vin is negative, and conversely, the smaller the on time of the switching tube M3 and the switching tube M4, the larger the current of the input capacitor Cbus is charged by the longer the on time of the switching tube M3 and the switching tube M4. When the on time of the switching transistors M3 and M4 is at a certain value, the charging and discharging currents of the input capacitor Cbus are equal, and the voltage of the input capacitor Cbus is at a steady state. Therefore, the on time of the switching tubes M3 and M4 is controlled, so that the voltage of the input capacitor Cbus can be limited and stabilized, and overstress of circuit devices is avoided. The invention sets a control circuit to control the switching tubes M3 and M4 to work cooperatively with the bridge rectifier tube, the control circuit obtains a first coefficient K according to a half-wave voltage Vre obtained after the bus voltage Vbus and the alternating input voltage Vin are rectified, and carries out error amplification on an output feedback signal FB and a first reference voltage to obtain a first error signal V1, and controls the conduction time of the transistor M3 according to the first coefficient K and the first error signal V1; there are two embodiments of the specific control circuit of the present invention as shown in fig. 5.
As shown in fig. 3, a schematic diagram of an embodiment 2 of the pfc converter of the present invention is illustrated, and on the basis of embodiment 1, there is further provided a second capacitor Cr2, a first end of the second capacitor Cr2 is connected to a first end of the first capacitor Cr1, a second end of the second capacitor Cr2 is connected to an intermediate node of another bridge arm, that is, if the second end of the first capacitor Cr1 is connected to the intermediate node of the first bridge arm, the second end of the second capacitor Cr2 is connected to the intermediate node of the second bridge arm, and the operation principle is similar to that of embodiment 1, taking the input voltage Vin as an example, the switching tube M4 is normally closed, and the switching tubes M1 and M2 are complementarily turned on, and the specific operation modes are as follows:
in the first stage, the switching tubes M1 and M3 are turned on, the switching tube M2 is turned off, the first inductor Lr is charged, the inductor current flows through the input capacitor Cbus, the switching tube M1, the first inductor Lr and the primary winding of the transformer and then is split, one part of the inductor current flows through the first capacitor Cr1, the switching tube M3 and the reference ground, and the other part of the inductor current flows through the second capacitor Cr2, the power grid, the switching tube M3 and the reference ground.
In the second stage, the switching tube M1 is turned on, the switching tubes M2 and M3 are turned off, the first inductor Lr freewheels, the inductor current is shunted after flowing through the switching tube M1, the first inductor Lr and the primary winding of the transformer, one part of the current flows through the first capacitor Cr1, the power grid and the diode D1, and the other part of the current flows through the second capacitor Cr2 and the diode D1.
In the third stage, the switching tubes M1 and M3 are turned off, the switching tube M2 is turned on, the first inductor Lr is freewheeled, current is split after flowing through the switching tube M2, the first inductor Lr and the primary winding of the transformer, one part of current flows through the first capacitor Cr1, the power grid, the diode D1, the input capacitor Cbus and the reference ground, and the other part of current flows through the second capacitor Cr2, the diode D1, the input capacitor Cbus and the reference ground.
In the fourth stage, the switching tubes M1 and M3 are turned off, the M2 is turned on, after the first inductor Lr freewheels to zero, the current is reversed, one part of the current flows through the body diode of the switching tube M3 and the first capacitor Cr1, the other part of the current flows through the power grid and the second capacitor Cr2, and after the two parts of currents are combined, the two parts of currents flow through the primary winding of the transformer, the first inductor Lr, the switching tube M2 and the reference ground;
in the fifth stage, the switching tubes M1 and M3 are turned on, the switching tube M2 is turned off, the current of the first inductor Lr is reversed, the inductor current is freewheeled, after the current flows through the switching tube M1, the input capacitor Cbus and the switching tube M3, a part of the current flows through the first capacitor Cr1, the primary winding of the transformer and the first inductor Lr, and another part of the current flows through the power grid, the second capacitor Cr2, the primary winding of the transformer and the first inductor Lr.
In embodiment 1, the working states of the converter are not completely consistent under different positive half-wave periods and negative half-wave periods of the input voltage Vin, the voltages loaded on the inductors are different, the currents flowing through the inductors are also different, and the switching states of the first switching tube M3 and the second switching tube M4 are not the same under the positive half-wave periods and the negative half-wave periods, namely the on-off time is not the same; in embodiment 2, the working states of the converter are completely identical in the positive and negative half-wave periods of the input voltage Vin, and the switching states of the first switching tube M3 and the second switching tube M4 are also completely identical, but this embodiment requires a capacitor Cr2. However, both embodiment 1 and embodiment 2 can limit and stabilize the voltage of the input capacitor Cbus by controlling the switching transistors M3 and M4, avoid overstress of the circuit device, and realize good power factor correction.
As shown in fig. 4, a schematic diagram of embodiment 3 of the power factor converter of the present invention is illustrated, which differs from embodiment 1 in that: the rectifying diodes D1, D2 in embodiment 1 are replaced with switching transistors M5, M6 in this embodiment, and the rectifying function as in embodiment 1 can still be realized by controlling the switching of the switching transistors M5, M6 by the body diodes of the switching transistors M5, M6 or according to the positive and negative of the input voltage. The embodiment can flexibly select switching tubes (M3, M4 or M5 and M6) to control and stabilize the Vbus voltage, and realize power factor correction.
As shown in fig. 5, a schematic diagram of a control circuit of the pfc converter according to the present invention is illustrated, in which M3 and M4 switching transistors and a bridge switching transistor in a rectifying circuit are controlled, and the pfc converter includes a first control circuit, a second control circuit, and an error amplifying circuit U101, where the first control circuit includes a multiplier U103, a first coefficient generating circuit U102, a ramp generator U104, a comparator U105, and a driver U106, and the second control circuit includes a comparator U107 and a driver U108. The error amplifying circuit U101 amplifies the output feedback voltage FB and the reference voltage Vref to obtain a first error signal V1, the first coefficient generating circuit U102 generates a first coefficient K, and the multiplier U103 multiplies the first coefficient K by the first error signal V1 to obtain a compensation signal Vcomp. The ramp generator U104 generates a ramp signal Vramp, the comparator U105 compares the compensation signal Vcomp with the ramp signal Vramp, the input voltage Vin is positive, the switching transistor M4 is normally off, the switching transistor M3 is controlled to be turned off when the ramp signal Vramp rises to the compensation signal Vcomp, the switching transistor M3 is normally off when the input voltage Vin is negative, and the switching transistor M4 is controlled to be turned off when the ramp signal Vramp rises to the compensation signal Vcomp. The comparator U107 compares the first error signal V1 with the ramp signal Vramp, and is used for controlling the bridge switching tubes M1 and M2, and when the ramp signal Vramp rises to the first error signal V1, the upper tube M1 is controlled to be turned off; the upper pipe M1 and the lower pipe M2 work complementarily, after the lower pipe M2 is closed, the upper pipe M1 is conducted, and when the upper pipe M1 is closed, the lower pipe M2 is conducted.
The first coefficient K generated by the first coefficient generating circuit U102 determines the on-time of the switching tubes M3 and M4, and the magnitude of the first coefficient K is set to balance the charging current and the discharging current of the input capacitor Cbus, so that the voltage of the input capacitor Cbus is in a steady state, the phenomenon that the device is damaged due to overlarge bus voltage Vbus and overlarge stress of an electric device is avoided, and meanwhile, the condition that the output requirement is not met due to overlarge bus voltage is avoided; the first coefficient K may be set according to the bus voltage Vbus and the half-wave voltage Vre obtained after rectification of the ac input voltage, specifically in the following setting manner:
the single-loop control is adopted, the structure is simple, and the input voltage Vin is larger than zero; given the on-time relationship of transistor M3 and upper transistor M1 of the bridge switch: ton_3=k×ton_1, where ton_3 is the on time of the switching tube M3 and ton_1 is the on time of the upper tube M1;
the control of the switching tube M3 and the upper tube M1 can be directly participated by an output loop, so that the switching tube M3 and the upper tube M1 have good output ripple and dynamic characteristics; to simplify the control, the given first coefficient K satisfies the following relation:
K=(Vbus-Vre)/Vbus（1）；
wherein, the liquid crystal display device comprises a liquid crystal display device,the Virms is the peak voltage of the alternating current input voltage.
At the vicinity of zero crossing of the grid voltage, the alternating current input voltage is close to zero voltage, at this time, k=1, the on-time of the transistor M3 is equal to the on-time of the upper tube M1, the input current can be similar to sine wave, and the harmonic standard requirement can be met. The rectified half-wave voltage can also be adaptively adjusted, for example, the rectified half-wave voltage is multiplied by an adjusting coefficient K1 to obtain a new half-wave voltage Vre, which is provided with
Vre can be substituted into formula (1);
according to equation (1), when the bus voltage Vbus is too high, the first coefficient K increases, and the on-time of the corresponding input current decreases, so as to balance the bus voltage, and vice versa.
In order to further limit the variation range of the bus voltage, the obtained first coefficient of the formula (1) may be further adjusted, that is, the correction of the bus voltage to the first coefficient may be further amplified, to obtain:
（2）；
wherein, the liquid crystal display device comprises a liquid crystal display device,kd is set to be smaller than 1 bus deviation coefficient such as 25%, and Kb has amplitude limit, can be set between 0.5 and 2, and is specifically set according to the needs, so that the set Kb can further compress the change range of bus voltage;
the example adopts single-ring control, has simple control strategy and controlled bus voltage, can limit the bus voltage range, and reduces the stress of circuit devices; given the conduction time relation between the switching tubes M3 and M4 and the upper tube M1, which contains sine wave information of the input voltage, under the control scheme, the input voltage is close to sine wave, and a better power factor correction effect is realized.
In addition, although the embodiments are described and illustrated separately above, it will be apparent to those skilled in the art that some common techniques may be substituted and integrated between the embodiments, and that reference may be made to another embodiment without explicitly recited in one of the embodiments.
The above-described embodiments do not limit the scope of the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the above embodiments should be included in the scope of the present invention.
Claims (9)
1. A power factor correction converter, characterized by: comprising the steps of (a) a step of,
the rectifier circuit comprises a first bridge arm and a second bridge arm, wherein an alternating current input power supply is connected between a middle node of the first bridge arm and a middle node of the second bridge arm, and an upper pipe of the first bridge arm and an upper pipe of the second bridge arm are transistors, or a lower pipe of the first bridge arm and a lower pipe of the second bridge arm are transistors;
the first circuit comprises a first switching tube and a second switching tube which are connected, a first resonant circuit formed by connecting a first inductor, a first capacitor and a primary winding of a transformer, wherein a first end of the first resonant circuit is connected with a common connection end of the first switching tube and a common connection end of the second switching tube, and a second end of the first resonant circuit is connected with an intermediate node of a bridge arm;
the control circuit performs error amplification on the output feedback signal and the reference signal to obtain a first error signal, generates a first coefficient according to half-wave voltage obtained by rectifying the bus voltage and the alternating input voltage, and obtains a compensation signal according to the product of the first error signal and the first coefficient; controlling the working state of the transistor according to the input voltage and the compensation signal;
the control circuit obtains a first ratio according to the ratio of the difference value of the bus voltage and the half-wave voltage to the bus voltage, and generates the first coefficient according to the first ratio.
2. The power factor correction converter of claim 1, wherein: the bridge further comprises a second capacitor, wherein the first end of the second capacitor is connected with the first end of the first capacitor, and the second end of the second capacitor is connected with the intermediate node of the other bridge arm.
3. The power factor correction converter of claim 2, wherein: the first capacitor and the second capacitor are equal in size.
4. The power factor correction converter of claim 1, wherein: the upper tube and the lower tube of the first bridge arm are transistors, and the upper tube and the lower tube of the second bridge arm are transistors.
5. The power factor correction converter of claim 1, wherein: the control circuit obtains the first coefficient according to the product of the first ratio and the second coefficient; and obtaining a second coefficient according to the bus voltage, the bus reference voltage and the deviation coefficient.
6. The power factor correction converter of claim 5, wherein: the second coefficient is set toWhere Vbus is the bus voltage, vbus_ref is the bus reference voltage, and Kd is the offset coefficient.
7. The power factor correction converter of claim 6, wherein: the deviation coefficient is set to a constant less than 1, and the peak value of the second coefficient is greater than 0.5 and less than 2.
8. The power factor correction converter of claim 1, wherein: the control circuit compares the first error signal with a first ramp signal to control the switching states of the first and second switching transistors.
9. The power factor correction converter of claim 1, wherein: the output circuit comprises a transformer secondary winding, a rectifying tube, an output capacitor and a load, wherein the transformer secondary winding is connected with the rectifying tube in series and then connected with the output capacitor in parallel, and the load is connected with the output capacitor; and after the current of the primary winding of the transformer is freewheeling to zero, the rectifying tube is conducted.
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| CN214014106U (en) * | 2020-11-02 | 2021-08-20 | 安徽乐图电子科技有限公司 | Low-cost single-stage power factor correction control circuit and switching power supply |
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| CN115566904A (en) * | 2021-07-02 | 2023-01-03 | 台达电子工业股份有限公司 | Power conversion circuit |
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| CN111835092B (en) * | 2020-07-27 | 2021-05-18 | 北京理工大学 | Bilateral LCC compensation network adjusting method and system of wireless charging system |
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| CN115566904A (en) * | 2021-07-02 | 2023-01-03 | 台达电子工业股份有限公司 | Power conversion circuit |
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