CN116367532A

CN116367532A - Semiconductor device and method for manufacturing the same

Info

Publication number: CN116367532A
Application number: CN202211173475.1A
Authority: CN
Inventors: 丁贤玉; 朴孝珍; 成豪镇; 李知恩; 曹永丞
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2021-12-24
Filing date: 2022-09-26
Publication date: 2023-06-30
Also published as: US20230209814A1; KR20230097849A

Abstract

A semiconductor device including a substrate having a peripheral region and a cell region therein, and a method of manufacturing the same are provided. A first semiconductor active pattern protruding from a substrate in a peripheral region is provided. A second semiconductor active pattern protruding from the substrate in the cell region is provided. The first edge of the upper portion of the first semiconductor active pattern has a circular shape, and the second edge of the upper portion of the second semiconductor active pattern has a circular shape. The curvature of the first edge is greater than the curvature of the second edge.

Description

Semiconductor device and method for manufacturing the same

The present application claims priority from korean patent application No. 10-2021-0187727, filed 24 at 12 months of 2021, the entire contents of which are incorporated herein by reference.

Technical Field

The present disclosure relates to an integrated circuit device and a method of manufacturing the same, and in particular, to a semiconductor switching device having reduced sensitivity to degradation of electrical characteristics caused by an electric field and a method of manufacturing the same.

Background

Semiconductor devices are considered to be important components in the electronics industry due to their small size, multi-function, and/or low cost characteristics. Those skilled in the art will understand that semiconductor devices can be broadly classified into semiconductor memory devices for storing data, semiconductor logic devices for processing data, and hybrid semiconductor devices having both memory elements and logic elements therein.

With the recent trend of higher speed and lower power consumption of electronic devices, semiconductor devices therein also require higher operation speed and/or lower operation voltage. To meet this requirement, it is generally necessary to increase the integration density of the semiconductor device. However, as the integration density of the semiconductor device increases, the reliability of the semiconductor device may deteriorate, and the production yield of the semiconductor device may decrease to an unacceptable level. Accordingly, many studies on how to improve the reliability and the production yield of the semiconductor device are currently being conducted.

Disclosure of Invention

One embodiment of the inventive concept provides a semiconductor device having improved reliability.

Another embodiment of the inventive concept provides a method of manufacturing a semiconductor device with high yield.

According to still another embodiment of the inventive concept, a semiconductor device may include: a substrate having a peripheral region and a cell region therein; and an active pattern protruding from the substrate. The active patterns may include a first active pattern in the peripheral region and a second active pattern in the cell region. The first edge of the upper portion of the first active pattern and the second edge of the upper portion of the second active pattern may have a circular shape. Advantageously, the curvature of the first edge may be greater than the curvature of the second edge in order to improve device performance and yield.

According to an embodiment of the inventive concept, a semiconductor device may include: a substrate including a peripheral region; an active pattern protruding from the substrate on the peripheral region; a device isolation pattern disposed between the active pattern and another active pattern adjacent thereto; and a gate dielectric pattern extending along a top surface of the active pattern and a top surface of the device isolation pattern. The edge of the upper portion of the active pattern may have a circular shape, and the top surface of the device isolation pattern may be located at a height substantially equal to or lower than the top surface of the active pattern. The bottom surface of the gate dielectric pattern may have a circular shape corresponding to an edge of the upper portion of the active pattern.

According to another embodiment of the inventive concept, a method of manufacturing a semiconductor device may include: sequentially forming a lower mask layer and an upper mask layer on a substrate having a peripheral region and a cell region therein; forming a first mask pattern and a second mask pattern on the upper mask layer, the first mask pattern and the second mask pattern being placed on the peripheral region and the cell region, respectively; removing a portion of the upper mask layer exposed by the second mask pattern from the cell region; thereafter removing the first mask pattern from the peripheral region; and forming an upper mask pattern by etching the peripheral region and the remaining portion of the upper mask layer on the cell region using the second mask pattern as an etching mask. The upper mask pattern may cover the lower mask layer on the peripheral region, and may expose a portion of the lower mask layer on the cell region.

Drawings

Fig. 1 is a block diagram illustrating a plan layout of a semiconductor device according to an embodiment of the inventive concept.

Fig. 2 to 12 are diagrams illustrating a method of manufacturing a semiconductor device according to an embodiment of the inventive concept, wherein: fig. 2 and 8 are plan views illustrating the peripheral region and the cell region of fig. 1, fig. 3 to 7 are cross-sectional views taken along lines A-A 'and B-B' of fig. 2, and fig. 9 to 12 are cross-sectional views taken along lines A-A 'and B-B' of fig. 8.

Fig. 13 and 14 are enlarged cross-sectional views illustrating portions P1 and P2 of fig. 12.

Fig. 15 is an enlarged sectional view showing portions P3 and P4 of fig. 12.

Fig. 16 is a plan view illustrating a semiconductor device according to an embodiment of the inventive concept.

Fig. 17 is a cross-sectional view taken along lines A-A 'and B-B' of fig. 16.

Fig. 18 and 19 are enlarged sectional views of a portion P5 corresponding to fig. 17.

Detailed Description

Example embodiments of the inventive concepts will now be described more fully with reference to the accompanying drawings, in which example embodiments are shown.

Fig. 1 is a block diagram illustrating a layout of a semiconductor device according to an embodiment of the inventive concept. Referring to fig. 1, the semiconductor device may include cell blocks CB and peripheral blocks PB disposed to surround each of the cell blocks CB. The semiconductor device may be a memory device, and each of the cell blocks CB may include a cell circuit (e.g., a memory integrated circuit). For example, the cell blocks CB may be spaced apart from each other in a first direction D1 and a second direction D2 orthogonal to each other.

The peripheral block PB may include various peripheral circuits for operating the unit circuits and the peripheral circuits may be electrically connected to the unit circuits. The peripheral block PB may also include a sense amplifier circuit SA and a sub word line driver circuit SWD. In an embodiment, the sense amplifier circuits SA may be disposed to face each other with the cell block CB interposed therebetween, and the sub-word line driver circuits SWD may be disposed to face each other with the cell block CB interposed therebetween. The peripheral block PB may further include a power circuit and a ground circuit for driving the sense amplifier, but the inventive concept is not limited to this example.

Fig. 2 to 12 are diagrams including intermediate structures illustrating a method of manufacturing a semiconductor device according to an embodiment of the inventive concept. Specifically, fig. 2 and 8 are plan layout views showing the peripheral region and the cell region of fig. 1, fig. 3 to 7 are cross-sectional views of the intermediate structure taken along lines A-A 'and B-B' of fig. 2, and fig. 9 to 12 are cross-sectional views of the intermediate structure taken along lines A-A 'and B-B' of fig. 8. Further, fig. 13 and 14 are enlarged sectional views showing portions P1 and P2 of fig. 12, and fig. 15 is an enlarged sectional view showing portions P3 and P4 of fig. 12.

Referring to fig. 2 and 3, a substrate 10 including a peripheral region PR and a cell region CR may be provided. The substrate 10 may be a semiconductor substrate (e.g., a silicon substrate, a germanium substrate, or a silicon germanium substrate). The peripheral region PR may be a region of the substrate 10 in which the peripheral blocks PB of fig. 1 are disposed, and the cell region CR may be another region of the substrate 10 in which each of the cell blocks CB of fig. 1 is disposed. The bottom surface of the substrate 10 may extend in a "horizontal" plane parallel to a plane defined by the first direction D1 and the second direction D2.

The lower mask layer 12 and the upper mask layer 14 may be sequentially formed on the substrate 10. The lower mask layer 12 and the upper mask layer 14 may be formed on the peripheral region PR and the cell region CR to cover the top surface of the substrate 10. The lower mask layer 12 may be formed of (or include) a material having a high etch selectivity with respect to the material of the upper mask layer 14. As an example, the lower mask layer 12 may be formed of (or include) silicon oxide, and the upper mask layer 14 may be formed of (or include) polysilicon.

The first mask pattern 20 may be formed on the peripheral region PR, and the second mask pattern 22 may be formed on the cell region CR. In an embodiment, the first mask pattern 20 and the second mask pattern 22 may be formed using a Quad Patterning Technique (QPT). The first mask pattern 20 may be a multi-layered structure including at least one of a carbon-based material, such as an Amorphous Carbon Layer (ACL) and a spin-on hard mask (SOH), and silicon oxynitride. As an example, the first mask pattern 20 may be a multi-layered structure in which carbon-based material and silicon oxynitride layers are sequentially stacked. The second mask pattern 22 may be a line-shaped pattern extending in a third direction D3, and the third direction D3 is not parallel to the first and second directions D1 and D2 but is parallel to the bottom surface of the substrate 10. Adjacent ones of the second mask patterns 22 may be spaced apart from each other in the first direction D1. In an embodiment, the second mask pattern 22 may be formed of (or include) silicon oxide.

The upper mask layer 14 may include a first portion 14a, a second portion 14b, and a third portion 14c. The first portion 14a may be a region of the upper mask layer 14 vertically overlapped with the first mask pattern 20 and the second mask pattern 22. A top surface of the first portion 14a may be in contact with a bottom surface of the first mask pattern 20 or a bottom surface of the second mask pattern 22, and a bottom surface of the first portion 14a may be in contact with a top surface of the lower mask layer 12. The second portion 14b may be another region of the upper mask layer 14 that is not vertically overlapped with the second mask pattern 22. A top surface of the second portion 14b may be exposed by the second mask pattern 22. The third portion 14c may be a region of the upper mask layer 14 that is not vertically overlapped with the second mask pattern 22 and is disposed under the second portion 14 b. The bottom surface of the third portion 14c may be in contact with the top surface of the lower mask layer 12. The second portion 14b may be removed by a removal process to be described with reference to fig. 4, and the third portion 14c may remain below the second portion 14 b. In other words, the areas of the second portion 14b and the third portion 14c may be adjusted by the removal process of fig. 4. In addition, the final curvature of the active pattern AP, which will be described with reference to fig. 12 to 14, may also be adjusted by the removal process of fig. 4.

Referring to fig. 4, the second portion 14b of the upper mask layer 14 may be removed from the cell region CR, however, the first portion 14a and the third portion 14c may not be removed by the removal process. The removal process may include an anisotropic etching process using the second mask pattern 22 as an etching mask.

In some embodiments, the first portion 14a may remain on the peripheral region PR and the cell region CR and the third portion 14c may remain on the cell region CR. The top surface of the third portion 14c may be exposed to the outside and may be located at a lower level than the top surface of the first portion 14 a. The top surface of the lower mask layer 12 may be covered by the first and

third portions

14a and 14c and may not be exposed to the outside. In an embodiment, a removal process may be performed to remove the upper portion of the first mask pattern 20 and the upper portion of the second mask pattern 22.

Referring to fig. 5, the first mask pattern 20 on the peripheral region PR may be removed. The removal process may include performing an ashing process. As a result of the removal process, the top surface of the first portion 14a on the peripheral region PR may become exposed. Thereafter, the top surface of the first portion 14a on the cell region CR may be covered by the second mask pattern 22, and may not be exposed to the outside. The removal process of the first mask pattern 20 and the removal process of the second portion 14b of the upper mask layer 14 may be performed in an in-situ manner.

Referring to fig. 6, an etching process may be performed on the upper mask layer 14 to form an upper mask pattern 15. The etching process may include an anisotropic etching process performed using the second mask pattern 22 as an etching mask. The etching process may then be used to etch the upper portion of the second mask pattern 22. In detail, the third portion 14c on the cell region CR may be etched. Thus, as shown, the lower mask layer 12 may be partially exposed. For example, the lower mask layer 12 may be exposed to the outside at a region not vertically overlapped with the second mask pattern 22. The first portion 14a of the upper mask layer 14 on the cell region CR may not be etched by the etching process, and an unetched portion (i.e., the first portion 14 a) may be used as the upper mask pattern 15.

On the peripheral region PR, an upper portion of the first portion 14a of the upper mask layer 14 may be etched by an etching process. Therefore, the thickness of the first portion 14a on the peripheral region PR in the fourth direction D4 can be reduced. The fourth direction D4 may be a direction perpendicular to the bottom surface of the substrate 10. On the peripheral region PR, the remaining portion of the first portion 14a on the peripheral region PR may not be etched by the etching process, and may remain on the lower mask layer 12 to constitute the upper mask pattern 15.

The top surface of the upper mask pattern 15 on the peripheral region PR may be located at a height substantially equal to or lower than the top surface of the upper mask pattern 15 on the cell region CR. The thickness of the upper mask pattern 15 on the peripheral region PR may be substantially equal to or less than the thickness of the upper mask pattern 15 on the cell region CR, as measured in the fourth direction D4. The thickness difference between the upper mask pattern 15 on the peripheral region PR and the upper mask pattern 15 on the cell region CR may be adjusted by the removal process described with reference to fig. 4. The thickness of the second portion 14b and the third portion 14c may be defined by the removal process of fig. 4. The greater the thickness of the third portion 14c (i.e., the smaller the amount of the upper mask layer 14 removed by the removal process of fig. 4), the greater the thickness difference between the upper mask patterns 15.

Referring to fig. 7, the second mask pattern 22 may be removed. During the removal of the second mask pattern 22, the lower mask layer 12 on the cell region CR may be partially etched. For example, during the removal of the second mask pattern 22, portions of the lower mask layer 12 that are not vertically overlapped with the upper mask pattern 15 and are exposed by the upper mask pattern 15 may be etched. The top surface of the substrate 10 may be covered by the lower mask layer 12 and may not be exposed. The lower mask layer 12 on the peripheral region PR may not be removed.

Referring to fig. 8 and 9, the third mask layer 30 and the photoresist pattern 32 may be sequentially formed. In detail, a third mask layer 30 may be formed on the peripheral region PR and the cell region CR to cover the upper mask pattern 15. Thereafter, a photoresist layer (not shown) may be formed to cover the third mask layer 30, and then, the photoresist pattern 32 may be formed by patterning the photoresist layer using an exposure process and a development process.

On the peripheral region PR, adjacent ones of the photoresist patterns 32 may be spaced apart from each other in the first direction D1. On the cell region CR, the photoresist pattern 32 may include holes H spaced apart from each other in the first and second directions D1 and D2. As shown, each hole H may vertically overlap a portion of the upper mask pattern 15.

Referring to fig. 10, the third mask layer 30 may be etched using the photoresist pattern 32 as an etching mask, and as a result, a third mask pattern (not shown) may be formed. Next, the fourth mask pattern 16 may be formed by etching the upper mask pattern 15 using the third mask pattern as an etching mask. Although not shown, the upper mask pattern 15 having a linear shape extending in the third direction D3 on the cell region CR may be divided into a plurality of fourth mask patterns 16 extending in the third direction D3 and spaced apart from each other in the third direction D3 when viewed from a planar view. The fourth mask pattern 16 on the peripheral region PR may have substantially the same shape as the photoresist pattern 32 when viewed in a plan view.

As an example, the etching process using the photoresist pattern 32 and the third mask pattern may be performed only once. As another example, the etching process may be performed several times. In this case, the position of the hole H of fig. 8 may be changed every time each etching process is performed.

The top surface of the fourth mask pattern 16 on the peripheral region PR may be located at a height substantially equal to or lower than the top surface of the fourth mask pattern 16 on the cell region CR. The thickness of the fourth mask pattern 16 on the peripheral region PR may be substantially equal to or less than the thickness of the fourth mask pattern 16 on the cell region CR, as measured in the fourth direction D4. The thickness difference between the fourth mask pattern 16 on the peripheral region PR and the fourth mask pattern 16 on the cell region CR may be proportional to the thickness difference between the upper mask pattern 15 on the peripheral region PR and the upper mask pattern 15 on the cell region CR described with reference to fig. 6. As a result, the thickness difference between the fourth mask patterns 16 may be controlled by the removal process described with reference to fig. 4. The width of the bottom surface of the fourth mask pattern 16 on the peripheral region PR may be greater than the width of the bottom surface of the fourth mask pattern 16 on the cell region CR.

Referring to fig. 11, the upper portion of the substrate 10 and the lower mask layer 12 may be etched using the fourth mask pattern 16 as an etching mask, and as a result, the lower mask pattern 13 and the active pattern AP may be formed. The active pattern AP may include first and second active patterns AP1 and AP2 disposed on the peripheral region PR and the cell region CR, respectively. The active pattern AP may be an unetched upper portion of the substrate 10. Hereinafter, for convenience of description, the remaining portion of the substrate 10 except for the active pattern AP may be referred to as the substrate 10. Accordingly, the active pattern AP may protrude from the substrate 10, and a bottom surface of the active pattern AP may contact a top surface of the substrate 10. In detail, the bottom surface 52 of the first active pattern AP1 may contact the top surface 56 of the substrate 10 on the peripheral region PR, and the bottom surface 62 of the second active pattern AP2 may contact the top surface 66 of the substrate 10 on the cell region CR. The width of the first active pattern AP1 in the first direction D1 may be greater than the width of the second active pattern AP2 in the first direction D1 when measured at the same height. As an example, the width of the top surface 54 (see fig. 12) of the first active pattern AP1 may be greater than the width of the top surface 64 (see fig. 12) of the second active pattern AP2.

A recess may be formed between adjacent ones of the active patterns AP. The first concave portion RE1 may be formed between adjacent first active patterns AP1, and the second concave portion RE2 may be formed between adjacent second active patterns AP 2. The width of the first concave portion RE1 may be larger than the width of the second concave portion RE2 when measured at the same height. The depth of the first concave portion RE1 may be different from the depth of the second concave portion RE2. As an example, in the case where the first concave portion RE1 has a width larger than that of the second concave portion RE2, the first concave portion RE1 may be deeper than the second concave portion RE2 due to an etching load effect. As another example, although not shown, in the case where the first concave portion RE1 has a width larger than that of the second concave portion RE2, the region to be etched in the first concave portion RE1 may be larger than that in the second concave portion RE2, and thus, the depth of the first concave portion RE1 may be smaller than that of the second concave portion RE2. Accordingly, a length L1 (see fig. 12) of the first active pattern AP1 in the fourth direction D4 may be different from a length L2 (see fig. 12) of the second active pattern AP2 in the fourth direction D4.

The lower mask pattern 13 may be formed on the active pattern AP. The top surface of the lower mask pattern 13 on the peripheral region PR may be located at a height substantially equal to or lower than the top surface of the lower mask pattern 13 on the cell region CR. The thickness of the lower mask pattern 13 on the peripheral region PR may be substantially equal to or less than the thickness of the lower mask pattern 13 on the cell region CR, as measured in the fourth direction D4. The thickness difference between the lower mask pattern 13 of the peripheral region PR and the lower mask pattern 13 on the cell region CR may be adjusted by the thickness difference between the fourth mask pattern 16 of the peripheral region PR and the fourth mask pattern 16 on the cell region CR described with reference to fig. 10. As a result, the thickness difference between the lower mask patterns 13 may be controlled by the removal process described with reference to fig. 4.

Referring to fig. 12, the lower mask pattern 13 may be removed. Next, the recess may be filled with a device isolation pattern STI. In detail, the device isolation pattern STI may include a first device isolation pattern STI1 formed to fill the first recess RE1, and a second device isolation pattern STI2 formed to fill the second recess RE 2. The device isolation pattern STI may be formed of (or include) at least one of silicon oxide, silicon nitride, and a combination thereof.

The first device isolation pattern STI1 may include a seam SM formed therein. In an embodiment, the seam SM may be an empty space (e.g., an inflated void). The top portion of the seam SM may be located at a height lower than the top surface 58 of the first device isolation pattern STI 1. In other words, the seam SM may not be exposed to the outside of the first device isolation pattern STI 1.

Referring to fig. 12 to 14, the top surface 58 of the device isolation pattern STI may be located at a height substantially equal to or lower than the top surface of the active pattern AP adjacent thereto. In detail, the top surface 58 of the first device isolation pattern STI1 may be located at a height substantially equal to or lower than the top surface 54 of the first active pattern AP1, and the top surface 68 of the second device isolation pattern STI2 may be located at a height substantially equal to or lower than the top surface 64 of the second active pattern AP 2. As an example, as shown in fig. 13, the top surface 58 of the first device isolation pattern STI1 may be located at substantially the same height as the top surface 54 of the first active pattern AP 1. As another example, as shown in fig. 14, the top surface 58 of the first device isolation pattern STI1 may be located at a lower level than the top surface 54 of the first active pattern AP 1.

The edge of the upper portion of the active pattern AP may have a circular shape. As an example, an edge of an upper portion of the active pattern AP may have a convex shape. As shown in fig. 13, the first edge EG1 of the upper portion of the first active pattern AP1 may have a more rounded shape than the second edge EG2 of the upper portion of the second active pattern AP 2. In other words, the curvature of the first edge EG1 may be greater than the curvature of the second edge EG2 (i.e., the radius of curvature of the first edge EG1 may be smaller than the radius of curvature of the second edge EG 2).

The curvature difference between the first edge EG1 and the second edge EG2 may be adjusted by the thickness difference between the fourth mask pattern 16 on the peripheral region PR and the fourth mask pattern 16 on the cell region CR described with reference to fig. 10. The larger the thickness difference between the fourth mask pattern 16 on the peripheral region PR and the fourth mask pattern 16 on the cell region CR, the larger the curvature difference. This is because the fourth mask pattern 16 serves as an etching mask in the process of forming the active pattern AP. As an example, when the first active pattern AP1 is formed, the smaller the thickness of the fourth mask pattern 16 on the peripheral region PR, the greater the etching amount of the first edge EG1, and this may cause the curvature of the first edge EG1 to increase. The curvature difference between the first edge EG1 and the second edge EG2 may be increased. As a result, the curvature difference between the first edge EG1 and the second edge EG2 may be controlled by the removal process described with reference to fig. 4.

The first active pattern AP1 may have a first width w1, a second width w2, and a third width w3. Here, the first, second, and third widths w1, w2, and w3 may be cross-sectional widths of the first active pattern AP 1. The first width w1 may be located at a base extending adjacent to the substrate 10 of the first active pattern AP 1. The first width w1 may be a width of the bottom surface 52 of the first active pattern AP 1. The second width W2 may be adjacent to the top surface 54 of the first active pattern AP 1. The second width W2 may be a width of the top surface 54 of the first active pattern AP 1. The third width w3 may be located at a midpoint between the substrate 10 and the top surface 54 of the first active pattern AP 1. The third width W3 may be a width of the first active pattern AP1 measured at a height (e.g., a midpoint) between the bottom surface 52 of the first active pattern AP1 and the top surface 54 of the first active pattern AP 1. The third width W3 may be smaller than the first width W1 and may be larger than the second width W2. The difference between the third width W3 and the first width W1 may be smaller than the difference between the third width W3 and the second width W2.

Referring to fig. 12 and 15, the first and second active patterns AP1 and AP2 may have first and second side surfaces S1 and S2, respectively. The first and second side surfaces S1 and S2 may be in contact with the first and second device isolation patterns STI1 and STI2, respectively. At the bottom level of the first active pattern AP1, the first side surface S1 may be inclined at a first angle A1 with respect to the top surface 56 of the substrate 10 on the peripheral region PR. At the bottom level of the second active pattern AP2, the second side surface S2 may be inclined at a second angle A2 with respect to the top surface 66 of the substrate 10 on the cell region CR. Each of the first angle A1 and the second angle A2 may be greater than 90 °. The first angle A1 may be substantially equal to or greater than the second angle A2.

According to an embodiment of the inventive concept, the second portion 14b of the upper mask layer 14 on the cell region CR may be previously removed before the first mask pattern 20 on the peripheral region PR is removed as shown in fig. 3 and 4. Conversely, the third portion 14c of the upper mask layer 14 may be removed after the first mask pattern 20 is removed as shown in fig. 5 and 6. In other words, the upper mask layer 14 on the peripheral region PR may not be covered by the first mask pattern 20 during the removing process of the third portion 14c. Therefore, the upper portion of the upper mask layer 14 on the peripheral region PR can also be removed. Accordingly, the thickness of the fourth mask pattern 16 to be formed in the subsequent step in the fourth direction D4 may have a relatively small value on the peripheral region PR. In other words, the fourth mask pattern 16, which serves as an etching mask in the process for forming the first active pattern AP1, may have a reduced thickness on the peripheral region PR. Accordingly, the first active pattern AP1 may be more affected by the etching process performed to form the active pattern AP than in the case where the fourth mask pattern 16 on the peripheral region PR is not thinned. As a result, the first edge EG1 of the first active pattern AP1 may have a circular shape, and as shown in fig. 19, the bottom surface of the gate dielectric pattern 305 may have a circular shape due to the circular shape of the first edge EG 1. Accordingly, it is advantageously possible to prevent an excessive electric field from concentrating on the gate dielectric pattern 305 near the first edge EG1, thereby preventing the gate dielectric pattern 305 from being degraded (e.g., undergoing field breakdown). Therefore, the reliability of the semiconductor device can be improved.

Further, the first angle A1 between the first side surface S1 of the first active pattern AP1 and the top surface 56 of the substrate 10 may be greater than 90 ° due to a strong influence of the etching process on the first active pattern AP 1. Accordingly, the seam SM in the first device isolation pattern STI1 may be formed in a lower portion of the first device isolation pattern STI1 and may not be exposed to the outside of the first device isolation pattern STI 1. As a result, process failures in subsequent processes (e.g., residues in exposed seams) may be reduced, thereby improving production yields.

Fig. 16 is a plan layout view illustrating a semiconductor device according to an embodiment of the inventive concept, and fig. 17 is a cross-sectional view taken along lines A-A 'and B-B' of fig. 16. Fig. 18 and 19 are enlarged sectional views of a portion P5 corresponding to fig. 17.

Referring to fig. 16 to 19, a substrate 10 including a peripheral region PR and a cell region CR may be provided. The substrate 10 may be a semiconductor substrate (e.g., a silicon substrate, a germanium substrate, or a silicon germanium substrate). The active pattern AP may be disposed on the substrate 10. The active pattern AP may protrude from the substrate 10. The active pattern AP may include first and second active patterns AP1 and AP2 disposed on the peripheral region PR and the cell region CR, respectively. The second active pattern AP2 may be a stripe pattern extending in the third direction D3 when viewed from a planar view angle.

The first active pattern AP1 may have a first edge EG1 disposed at an upper portion thereof, and the second active pattern AP2 may have a second edge EG2 disposed at an upper portion thereof. The first edge EG1 and the second edge EG2 may have a circular shape. As further shown in fig. 14, the curvature of the first edge EG1 may be greater than the curvature of the second edge EG2.

The device isolation pattern STI may be disposed between adjacent ones of the active patterns AP. The device isolation pattern STI may include a first device isolation pattern STI1 interposed between the first active patterns AP1 and a second device isolation pattern STI2 interposed between the second active patterns AP 2. The device isolation pattern STI may be formed of (or include) at least one of silicon oxide, silicon nitride, and a combination thereof. The first device isolation pattern STI1 of the device isolation pattern STI may include a seam SM disposed therein.

The top surface of the device isolation pattern STI may be located at a height substantially equal to or lower than the top surface of the active pattern AP adjacent thereto. The top surface 58 of the first device isolation pattern STI1 may be located at a height substantially equal to or lower than the top surface 54 of the first active pattern AP 1. As an example, as shown in fig. 18, the top surface 58 of the first device isolation pattern STI1 may be located at substantially the same height as the top surface 54 of the first active pattern AP 1. As another example, as shown in fig. 19, the top surface 58 of the first device isolation pattern STI1 may be located at a lower level than the top surface 54 of the first active pattern AP 1.

The impurity region may be disposed in the active pattern AP. The impurity regions may include a first impurity region 111, a second impurity region 112, and a third impurity region 113. The first impurity region 111 may be disposed in an upper portion of the first active pattern AP 1. The second impurity region 112 may be disposed in an upper portion of the second active pattern AP2 when viewed in a plan view, and may be disposed adjacent to a central portion of the second active pattern AP 2. The third impurity region 113 may be disposed in an upper portion of the second active pattern AP2 when viewed in a plan view, and may be disposed adjacent to an end portion of the second active pattern AP 2. The second impurity region 112 may be doped with impurities to have the same conductivity type (e.g., n-type) as that of the third impurity region 113.

A pair of word lines WL may be disposed on the cell region CR to cross the second active pattern AP2 in the first direction D1. The pair of word lines WL may be spaced apart from each other in the second direction D2. The second impurity region 112 may be disposed between the pair of word lines WL, and the third impurity region 113 may be disposed near an end of the second active pattern AP2 not disposed between the pair of word lines WL. The pair of word lines WL may be buried in the substrate 10.

On the peripheral region PR, a gate dielectric pattern 305 and a gate structure GS may be disposed on the first active pattern AP 1. The gate dielectric pattern 305 and the gate structure GS may be sequentially stacked on the first active pattern AP 1. The gate dielectric pattern 305 may extend along the top surface 54 of the first active pattern AP1 and the top surface 58 of the first device isolation pattern STI 1. In an embodiment, the gate dielectric pattern 305 may be formed of (or include) silicon oxide.

The top surface of the gate dielectric pattern 305 on the first device isolation pattern STI1 may be located at a height substantially equal to or lower than the top surface of the gate dielectric pattern 305 on the first active pattern AP 1. As an example, as shown in fig. 18, the top surface of the gate dielectric pattern 305 on the first device isolation pattern STI1 may be located at substantially the same height as the top surface of the gate dielectric pattern 305 on the first active pattern AP 1. As another example, as shown in fig. 19, the top surface of the gate dielectric pattern 305 on the first device isolation pattern STI1 may be located at a lower height than the top surface of the gate dielectric pattern 305 on the first active pattern AP 1.

Due to the above-described curvature and shape of the first edge EG1, the bottom surface of the gate dielectric pattern 305 may also have a circular shape. That is, the gate dielectric pattern 305 may have curvature (i.e., a non-planar profile) at a region adjacent to the first edge EG1 of the upper portion of the first active pattern AP 1. Unfortunately, in case that the first edge EG1 has a sharp shape, the bottom surface of the gate dielectric pattern 305 may also have a sharp shape corresponding to the shape of the first edge EG 1. In this case, during the operation of the semiconductor device, an electric field may concentrate on the sharp region, and thus, the gate dielectric pattern 305 may be deteriorated. In contrast, as in the foregoing embodiment, in the case where the bottom surface of the gate dielectric pattern 305 has a non-sharp shape or a circular shape, it is possible to prevent an excessive concentration of an electric field on the gate dielectric pattern 305, thereby preventing the gate dielectric pattern 305 from being deteriorated by dielectric field-induced breakdown.

The gate structure GS may be disposed to intersect the first active pattern AP 1. The gate structure GS may include a peripheral polysilicon pattern 310a, a first peripheral ohmic pattern 331a, a peripheral metal-containing pattern 330a, a first peripheral cap pattern 351a, and a spacer 355. The peripheral polysilicon pattern 310a, the first peripheral ohmic pattern 331a, the peripheral metal-containing pattern 330a, and the first peripheral cap pattern 351a may be sequentially stacked on the gate dielectric pattern 305. The spacers 355 may be disposed on the side surfaces of the peripheral polysilicon pattern 310a, the first peripheral ohmic pattern 331a, the peripheral metal-containing pattern 330a, and the first peripheral cap pattern 351 a. The second peripheral cap pattern 352a may be disposed to cover a top surface of the first peripheral cap pattern 351a, and the second peripheral cap pattern 352a may extend along side surfaces of the spacers 355 and a top surface of the gate dielectric pattern 305 to have a substantially uniform thickness. The lower insulating pattern 370 may be disposed to surround the gate structure GS and the second peripheral cap pattern 352a.

In an embodiment, the peripheral polysilicon pattern 310a may be formed of (or include) doped or undoped polysilicon. The first peripheral ohmic pattern 331a may be formed of (or include) at least one of metal silicide materials. The peripheral metal-containing pattern 330a may be formed of (or include) at least one of metal materials (e.g., tungsten, titanium, and tantalum). The first and second

peripheral cap patterns

351a and 352a may be formed of (or include) silicon nitride. The spacer 355 may be formed of (or include) silicon oxide.

The third peripheral cap pattern 353a, the peripheral diffusion preventing pattern 342a, and the contact plug CPLG may be sequentially stacked on the lower insulating pattern 370. The peripheral fill pattern 400a may be disposed between adjacent ones of the contact plugs CPLG. The peripheral filling pattern 400a may penetrate the peripheral diffusion preventing pattern 342a and may extend into the third peripheral cap pattern 353 a.

According to an embodiment, the third peripheral cap pattern 353a may be formed of (or include) silicon nitride. The peripheral diffusion preventing pattern 342a may be formed of (or include) at least one of metal nitride materials (e.g., titanium nitride and tantalum nitride). The contact plug CPLG may be formed of (or include) a metal-containing material (e.g., tungsten).

The peripheral etch stop pattern 420a and the upper insulating pattern 500 may be sequentially stacked on the contact plug CPLG and the peripheral fill pattern 400 a. In an embodiment, the peripheral etch stop pattern 420a may be formed of (or include) SiBN. The etch stop pattern 420 may include a single layer or multiple layers. As an example, the upper insulating pattern 500 may be formed of (or include) silicon oxide.

On the cell region CR, a buffer pattern 306 may be disposed to cover the second active pattern AP2, the second device isolation pattern STI2, and the pair of word lines WL. In an embodiment, the buffer pattern 306 may be formed of (or include) at least one of silicon oxide, silicon nitride, and silicon oxynitride.

The bit line BL may be disposed on the buffer pattern 306. The bit lines BL may extend in the second direction D2 and may be spaced apart from each other in the first direction D1. Each of the bit lines BL may include a first cell ohmic pattern 331b and a cell metal-containing pattern 330b sequentially stacked. The first cell ohmic pattern 331b and the cell metal-containing pattern 330b may be formed of the same material as the first peripheral ohmic pattern 331a and the peripheral metal-containing pattern 330a, respectively (or include the same material as the first peripheral ohmic pattern 331a and the peripheral metal-containing pattern 330 a).

The cell polysilicon pattern 310b may be interposed between the bit line BL and the buffer pattern 306. The unit polysilicon pattern 310b may be formed of the same material as that of the peripheral polysilicon pattern 310a (or include the same material as that of the peripheral polysilicon pattern 310 a).

The bit line contacts DC may be respectively disposed between the bit lines BL and the second impurity regions 112. The bit line BL may be electrically connected to the second impurity region 112 through a bit line contact DC. The bit line contacts DC may be formed of (or include) doped or undoped polysilicon.

The bit line contact DC may be disposed in the third recess region RE 3. The third recess region RE3 may be disposed in an upper portion of the second impurity region 112 and an upper portion of the second device isolation pattern STI2 adjacent thereto. A first "gap-fill" insulating pattern 314 and a second "gap-fill" insulating pattern 315 may be provided to fill the remaining portion of the third recess region RE 3.

The cell cover pattern 350 may be disposed on each bit line BL and may extend in the second direction D2. The unit cover pattern 350 may include a first unit cover pattern 351b, a second unit cover pattern 352b, and a third unit cover pattern 353b sequentially stacked and extending in the second direction D2. The first to third

unit cover patterns

351b, 352b, and 353b may be formed of the same material as the first to first

peripheral cover patterns

351a, 352a, and 353a (or include the same material as the first to first

peripheral cover patterns

351a, 352a, and 353 a), respectively.

The side surface of each cell polysilicon pattern 310b, the upper side surface of each bit line contact DC, the side surface of each bit line BL, and the side surface of the cell cap pattern 350 may be covered by the bit line spacer SP. The bit line spacers SP may be disposed on each bit line BL and may extend in the second direction D2.

The bit line spacer SP may include a first sub-spacer 321 and a second sub-spacer 325 spaced apart from each other. In an embodiment, the first and

second sub-spacers

321 and 325 may be spaced apart from each other by an air gap AG. The first sub-spacer 321 may contact a side surface of each bit line BL and may extend to cover a side surface of the cell cover pattern 350. The second sub-spacer 325 may be disposed along a side surface of the first sub-spacer 321. The first and

second sub-spacers

321 and 325 may be formed of (or include) silicon nitride.

The upper spacer 360 may cover a side surface of the first sub-spacer 321 and may extend to an area on a top surface of the second sub-spacer 325. The upper spacer 360 may cover or block the air gap AG.

The storage node contact BC may be placed between adjacent ones of the bit lines BL. The storage node contacts BC may be spaced apart from each other in the first and second directions D1 and D2. The storage node contact BC may be formed of (or include) doped or undoped polysilicon.

The second cell ohmic pattern 341b may be disposed on each storage node contact BC. Although not shown, a cell diffusion preventing pattern may be provided to conformally cover the second cell ohmic pattern 341b, the bit line spacer SP, and the cell cap pattern 350. In some further embodiments, the cell diffusion preventing pattern may be formed of the same material as that of the peripheral diffusion preventing pattern 342a (or include the same material as that of the peripheral diffusion preventing pattern 342 a). The second cell ohmic pattern 341b may be interposed between the cell diffusion preventing pattern and each storage node contact BC.

Landing pads LP may be disposed on the storage node contacts BC, respectively. The landing pads LP may be spaced apart from each other in the first direction D1 and the second direction D2. The landing pad LP may be formed of (or include) a metal-containing material such as tungsten (W).

The cell filling pattern 400b may be disposed to surround each landing pad LP. The cell fill pattern 400b may be disposed between adjacent ones of the landing pads LP. The cell filling pattern 400b may be formed of the same material as that of the peripheral filling pattern 400a (or include the same material as that of the peripheral filling pattern 400 a).

The bottom electrodes BE may BE respectively disposed on the landing pads LP. The bottom electrode BE may BE formed of (or include) at least one of doped polysilicon, a metal nitride material (e.g., titanium nitride), and a metal material (e.g., tungsten, aluminum, and copper). Each of the bottom electrodes BE may BE shaped like a cylinder, a hollow cylinder or a cup. The upper support pattern SS1 may BE provided to support an upper side surface of the bottom electrode BE, and the lower support pattern SS2 may BE provided to support a lower side surface of the bottom electrode BE. The upper and lower support patterns SS1 and SS2 may be formed of (or include) at least one of insulating materials (e.g., silicon nitride, silicon oxide, and silicon oxynitride).

The cell etch stop pattern 420b may BE disposed between the bottom electrodes BE and on the cell fill pattern 400 b. A dielectric layer DL may BE disposed to cover the bottom electrode BE and the upper and lower support patterns SS1 and SS2. In an embodiment, the dielectric layer DL may be formed of (or include) at least one of silicon oxide, silicon nitride, silicon oxynitride, and a high-k dielectric material (e.g., hafnium oxide). The top electrode TE may BE disposed on the dielectric layer DL to fill the space between the bottom electrodes BE. The top electrode TE may be formed of (or include) at least one of doped polysilicon, doped silicon germanium, a metal nitride material (e.g., titanium nitride) and a metal material (e.g., tungsten, aluminum and copper). The bottom electrode BE, the dielectric layer DL, and the top electrode TE may constitute a capacitor CA.

According to an embodiment of the inventive concept, an edge of an upper portion of the active pattern on the peripheral region may have a circular shape, and thus, a bottom surface of the gate dielectric pattern on the active pattern may have a circular shape due to the circular shape of the edge. As a result, it is possible to prevent a high electric field from concentrating on the gate dielectric pattern near the edge, thereby preventing the gate dielectric pattern from undergoing field degradation or breakdown. Therefore, the reliability of the semiconductor device can be improved.

Further, even when the seam is formed in the device isolation pattern adjacent to the active pattern, the seam may be formed in a lower portion of the device isolation pattern and may not be exposed to the outside of the device isolation pattern. As a result, process failures in subsequent processes (e.g., residues in exposed seams) may be reduced, thereby improving production yields.

While example embodiments of the inventive concepts have been particularly shown and described, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.

Claims

1. A semiconductor device, the semiconductor device comprising:

A substrate having a peripheral region and a cell region therein; a first active pattern protruding from the substrate in the peripheral region; and

a second active pattern protruding from the substrate in the cell region;

wherein a first edge of an upper portion of the first active pattern has a circular shape and a second edge of an upper portion of the second active pattern has a circular shape; and is also provided with

Wherein the curvature of the first edge is greater than the curvature of the second edge.

2. The semiconductor device according to claim 1, wherein the first active pattern has: a first cross-sectional width at a base of the first active pattern, the base extending adjacent the substrate; a second cross-sectional width adjacent to a top surface of the first active pattern; and a third cross-sectional width at a midpoint intermediate the base and the top surface; and wherein the first cross-sectional width is greater than the third cross-sectional width, which is greater than the second cross-sectional width.

3. The semiconductor device of claim 2, wherein a difference between the third profile width and the first profile width is less than a difference between the third profile width and the second profile width.

4. The semiconductor device of claim 1, wherein a width of a top surface of the first active pattern is greater than a width of a top surface of the second active pattern.

5. The semiconductor device of claim 1, wherein an angle between a top surface of the substrate and a side surface of the first active pattern, as measured at a bottom level of the first active pattern, is greater than 90 °.

6. The semiconductor device according to claim 1, further comprising:

a first device isolation pattern extends adjacent to a sidewall of the first active pattern and has a seam therein.

7. The semiconductor apparatus of claim 6, wherein a height of a top portion of the seam is less than a height of the first device isolation pattern as measured with respect to the substrate.

8. The semiconductor device according to claim 1, further comprising:

a first device isolation pattern extending on a sidewall of the first active pattern and having a height less than or equal to a height of a top surface of the first active pattern as measured with respect to the substrate.

9. The semiconductor device according to claim 8, further comprising:

A gate dielectric pattern extending along the top surface of the first active pattern and the top surface of the first device isolation pattern; and is also provided with

Wherein a bottom surface of the gate dielectric pattern has a circular shape corresponding to the first edge of the upper portion of the first active pattern.

10. The semiconductor device of claim 9, wherein a radius of curvature of a circular shape along the bottom surface of the gate dielectric pattern corresponds to a radius of curvature of the first edge along the upper portion of the first active pattern.

11. A semiconductor device, the semiconductor device comprising:

a substrate having a peripheral region therein;

an active pattern protruding from the substrate in the peripheral region;

a device isolation pattern disposed between the active pattern and another active pattern adjacent thereto; and

a gate dielectric pattern extending along a top surface of the active pattern and along a top surface of the device isolation pattern;

wherein an edge of an upper portion of the active pattern has a circular shape;

wherein the top surface of the device isolation pattern is located at a height equal to or lower than the top surface of the active pattern; and is also provided with

Wherein a bottom surface of the gate dielectric pattern has a circular shape corresponding to an edge of an upper portion of the active pattern.

12. The semiconductor device of claim 11, wherein a first angle between a top surface of the substrate and a side surface of the active pattern is greater than 90 ° at a bottom level of the active pattern.

13. The semiconductor apparatus of claim 11, wherein the device isolation pattern includes a seam disposed therein.

14. The semiconductor device of claim 13, wherein a top portion of the seam is located at a height below the top surface of the device isolation pattern.

15. The semiconductor device of claim 11, wherein the gate dielectric pattern has a non-zero curvature at a region adjacent to the edge of the upper portion of the active pattern.

16. A method of manufacturing a semiconductor device, the method comprising:

sequentially forming a lower mask layer and an upper mask layer on a substrate having a peripheral region and a cell region therein;

forming a first mask pattern and a second mask pattern on the upper mask layer, the first mask pattern and the second mask pattern being placed on the peripheral region and the cell region, respectively;

Removing a portion of the upper mask layer exposed by the second mask pattern from the cell region; then

Removing the first mask pattern from the peripheral region; and

forming an upper mask pattern by etching the remaining portions of the upper mask layer on the cell region and the peripheral region using the second mask pattern as an etching mask; and is also provided with

Wherein the upper mask pattern covers the lower mask layer on the peripheral region and exposes a portion of the lower mask layer on the cell region.

17. The method of claim 16, wherein a top surface of the upper mask pattern on the peripheral region is located at a height equal to or lower than a top surface of the upper mask pattern on the cell region.

18. The method of claim 16, wherein removing the portion of the upper mask layer exposed by the second mask pattern and removing the first mask pattern are performed in-situ.

19. The method of claim 16, the method further comprising:

forming a third mask pattern on the upper mask pattern;

forming a fourth mask pattern by etching the upper mask pattern using the third mask pattern as an etching mask; and

Forming a lower mask pattern and an active pattern by etching the lower mask layer and an upper portion of the substrate using the fourth mask pattern as an etching mask; and is also provided with

Wherein a top surface of the fourth mask pattern on the peripheral region is located at a height equal to or lower than a top surface of the fourth mask pattern on the cell region.

20. The method of claim 19, wherein a top surface of the lower mask pattern on the peripheral region is located at a height equal to or lower than a top surface of the lower mask pattern on the cell region.