CN116365911A - Boost type five-level inverter with double voltage gain - Google Patents
Boost type five-level inverter with double voltage gain Download PDFInfo
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- CN116365911A CN116365911A CN202310343222.2A CN202310343222A CN116365911A CN 116365911 A CN116365911 A CN 116365911A CN 202310343222 A CN202310343222 A CN 202310343222A CN 116365911 A CN116365911 A CN 116365911A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The invention relates to a boost five-level inverter with double voltage gain, which comprises a direct current input power supply and two switch capacitors C 1 、C 2 The device comprises an inductor L, four pairs of complementarily-conducted switching tubes and a load; wherein the four pairs of complementarily-conducted switching tubes comprise a switching tube S 1 And a switch tube S 2 Switch tube S 3 And a switch tube S 4 Switch tube S 5 And a switch tube S 6 And a switching tube S 7 And a switch tube S 8 The method comprises the steps of carrying out a first treatment on the surface of the In the switching tube S 1 Switch tube S 2 Switch tube S 3 Switch tube S 4 Switch tube S 5 Switch tube S 6 Switch tube S 7 And a switch tube S 8 The upper parts are connected in reverse parallel with a diode D; the voltage at the DC input power supply is denoted as DC input voltage V dc The ac output voltage of the inverter is denoted as load voltage U o . Due to the topological structure, the five-level double-voltage boosting gain can be generated; in actual regulation and control, a carrier phase shift modulation strategy can be adopted, and the capacitor voltage can be automatically balanced; the pulse current caused by the charging of the switched capacitor is small.
Description
Technical Field
The invention relates to the technical field of multilevel inverters, in particular to a boost type five-level inverter with twice voltage gain.
Background
At present, new energy power generation is developed at home and abroad, but under the general condition, the direct current output by the new energy power generation device is unstable and cannot be directly supplied to users needing the alternating current. Thus, inversion techniques employing DC-AC conversion are required to convert direct current to alternating current, which may be incorporated into the utility grid if desired. The multilevel inverter has the advantages of low output voltage harmonic content, low switching tube voltage stress, low switching loss, low electromagnetic interference and the like, and is widely applied to new energy power generation. The traditional multilevel inverter comprises an inverter circuit such as a diode clamping type, a flying capacitor type, a cascade H bridge and the like. However, as the number of output levels increases, the current inverter circuit structure is complex and requires more electronic devices, increasing the system cost and complexity of system control.
However, the conventional multilevel inverter has a problem of insufficient voltage gain, and thus, how to use a smaller number of elements to generate higher voltage gain has become a hot spot of research. At present, the problem is subjected to deep theoretical analysis by existing academic papers, and a practical engineering method is also provided, for example, a boost type single-phase seven-level inverter disclosed in 10/6 of 2018 in Chinese patent application publication No. CN108616224A is mainly a seven-level inverter circuit formed by combining and designing a direct current power supply, a switch tube, a capacitor, an inductor and a diode. The inverter circuit can output seven-level voltage, generate 1.5 times of voltage gain, and effectively reduce the harmonic wave of output current. However, this single-phase seven-level inverter has the following drawbacks:
1) The voltage gain is insufficient, and the maximum value of the output voltage is only 1.5 times of the input voltage;
2) The circuit has a very complex structure due to the excessive variety and number of elements used in the circuit.
In addition, chinese patent application publication CN112564529a, a boost seven-level inverter disclosed in 12/9/2020, mainly comprises a dc power supply, a diode, a floating capacitor, and a switching tube. The inverter circuit can output seven-level voltage, and the harmonic wave of output current can be effectively reduced by generating 1.5 times of voltage gain. However, this single-phase seven-level inverter has the following drawbacks:
1) The voltage gain is insufficient, and the maximum value of the output voltage is only 1.5 times of the input voltage;
2) The circuit has a very complex structure due to the excessive variety and number of elements used in the circuit.
Disclosure of Invention
The invention aims to provide a boost type five-level inverter with double voltage boost gain, which has a simple circuit structure and can generate the double voltage boost gain of five levels.
In order to achieve the above purpose, the present invention adopts the following technical scheme: a boost-type five-level inverter with twice voltage gain comprises a DC input power supply, two switch capacitors C 1 、C 2 The device comprises an inductor L, four pairs of complementarily-conducted switching tubes and a load; wherein the four pairs of complementarily-conducted switching tubes comprise a switching tube S 1 And a switch tube S 2 Switch tube S 3 And a switch tube S 4 Switch tube S 5 And a switch tube S 6 ToSwitch tube S 7 And a switch tube S 8 The method comprises the steps of carrying out a first treatment on the surface of the In the switching tube S 1 Switch tube S 2 Switch tube S 3 Switch tube S 4 Switch tube S 5 Switch tube S 6 Switch tube S 7 And a switch tube S 8 The upper parts are connected in reverse parallel with a diode D; the voltage at the DC input power supply is denoted as DC input voltage V dc The ac output voltage of the inverter is denoted as load voltage u o ；
The positive pole of the direct current input power supply is respectively connected with the switch tube S 3 Switch tube S 7 Drain electrode of (d) switch tube S 5 The negative pole of the direct current input power source is connected with the switch tube S respectively 4 Source electrode of (S) switch tube 8 Source electrode of (S) switch tube 6 Is connected with the drain electrode of the transistor; switch tube S 7 Source electrode of (S) switch tube 8 The drains of the capacitors are connected with one end of an inductor L; switch capacitor C 1 Negative electrode of (C) and switch capacitor (C) 2 The positive poles of the inductor L are connected with the other end of the inductor L; switch tube S 5 The drain electrode of (C) is respectively connected with the switch capacitor C 1 Positive electrode of (a) switching tube S 1 Is connected with the drain electrode of the transistor; switch tube S 6 The source of (C) is respectively connected with the switch capacitor C 2 Is a cathode of the switch tube S 2 Is connected with the source electrode of the transistor; the positive pole of the load is respectively connected with the switch tube S 3 Source electrode of (S) switch tube 4 The negative electrode of the load is connected with the switch tube S respectively 1 Source electrode of (S) switch tube 2 Is connected to the drain of the transistor.
When the load voltage U o ＝+2V dc Switch tube S 2 Switch tube S 3 Switch tube S 5 Switch tube S 8 Conduction and switch tube S 1 Switch tube S 4 Switch tube S 6 Switch tube S 7 All turn off, at this time, the switch capacitor C 1 Charging in parallel with DC input power supply, switch capacitor C 1 The voltage at two ends is charged to V dc Switch capacitor C 2 Discharging in series with the DC input power supply, wherein the output voltage at the two ends of the load is +2V dc 。
When the load voltage U o ＝+V dc Switch tube S 2 SwitchTube S 3 Switch tube S 6 Switch tube S 7 Conduction and switch tube S 1 Switch tube S 4 Switch tube S 5 Switch tube S 8 All turn off, at this time, the switch capacitor C 2 A switch capacitor C connected in parallel with the DC input power supply 2 The voltage at two ends is charged to V dc Switch capacitor C 1 Idle, the output voltage at the two ends of the load is +V dc 。
When the load voltage U o When = +0, switch tube S 2 Switch tube S 4 Switch tube S 6 Switch tube S 7 Conduction and switch tube S 1 Switch tube S 3 Switch tube S 5 Switch tube S 8 All turn off, at this time, the switch capacitor C 2 A switch capacitor C connected in parallel with the DC input power supply 2 The voltage at two ends is charged to V dc Switch capacitor C 1 Idle, the two ends of the load are short-circuited under the state, and the output voltage of the two ends of the load is +0V dc 。
When the load voltage U o When= -0, switch tube S 1 Switch tube S 3 Switch tube S 5 Switch tube S 8 Conduction and switch tube S 2 Switch tube S 4 Switch tube S 6 Switch tube S 7 All turn off, at this time, the switch capacitor C 1 A switch capacitor C connected in parallel with the DC input power supply 1 The voltage at two ends is charged to V dc Switch capacitor C 2 Idle, the two ends of the load are short-circuited under the state, and the output voltage of the two ends of the load is-0V dc 。
When the load voltage U o ＝-V dc Switch tube S 1 Switch tube S 4 Switch tube S 5 Switch tube S 8 Conduction and switch tube S 2 Switch tube S 3 Switch tube S 6 Switch tube S 7 All turn off, at this time, the switch capacitor C 1 A switch capacitor C connected in parallel with the DC input power supply 1 The voltage at two ends is charged to V dc Switch capacitor C 2 Idle, the output voltage of the two ends of the load is-V dc 。
When the load voltage U o ＝-2V dc Switch tube S 1 Switch tube S 4 Switch tube S 6 Switch tube S 7 Conduction and switch tube S 2 Switch tube S 3 Switch tube S 5 Switch tube S 8 All turn off, at this time, the switch capacitor C 2 Charging in parallel with DC input power supply, switch capacitor C 2 The voltage at two ends is charged to V dc Switch capacitor C 1 Discharging in series with the DC input power supply, in which the output voltage of the two ends of the load is-2V dc 。
The switch tube S 1 Switch tube S 2 Switch tube S 3 Switch tube S 4 Switch tube S 5 Switch tube S 6 Switch tube S 7 And a switch tube S 8 Are power switch tubes.
According to the technical scheme, the beneficial effects of the invention are as follows: firstly, due to the topological structure, the circuit structure is simple, and can generate voltage boosting gain twice as high as five levels; secondly, due to the topological structure, a carrier phase shift modulation strategy can be adopted in actual regulation and control, and the capacitor voltage can be automatically balanced; third, due to the topology of the present invention, the pulse current caused by the charging of the switched capacitor is small.
Drawings
FIG. 1 is a topological structure diagram of the present invention;
FIG. 2 is a schematic diagram of the circuit in a first operating state of the present invention;
FIG. 3 is a schematic diagram of the circuit in a second operating mode according to the present invention;
FIG. 4 is a schematic diagram of the circuit in a third operating mode according to the present invention;
FIG. 5 is a schematic diagram of the circuit in a fourth operating mode according to the present invention;
FIG. 6 is a schematic diagram of the circuit in a fifth operating mode according to the present invention;
FIG. 7 is a schematic diagram of the circuit in a sixth operating mode according to the present invention;
FIG. 8 is a schematic diagram of the driving signals of each switching tube obtained by logically combining the six working states of the present invention;
FIG. 9 is a simulation diagram of an AC load voltage waveform of the present invention;
fig. 10 is a simulation diagram of a load current waveform of the present invention.
Detailed Description
As shown in FIG. 1, a boost type five-level inverter with double voltage gain comprises a DC input power supply, two switch capacitors C 1 、C 2 The device comprises an inductor L, four pairs of complementarily-conducted switching tubes and a load; wherein the four pairs of complementarily-conducted switching tubes comprise a switching tube S 1 And a switch tube S 2 Switch tube S 3 And a switch tube S 4 Switch tube S 5 And a switch tube S 6 And a switching tube S 7 And a switch tube S 8 The method comprises the steps of carrying out a first treatment on the surface of the In the switching tube S 1 Switch tube S 2 Switch tube S 3 Switch tube S 4 Switch tube S 5 Switch tube S 6 Switch tube S 7 And a switch tube S 8 The upper parts are connected in reverse parallel with a diode D; the voltage at the DC input power supply is denoted as DC input voltage V dc The ac output voltage of the inverter is denoted as load voltage u o ；
The positive pole of the direct current input power supply is respectively connected with the switch tube S 3 Switch tube S 7 Drain electrode of (d) switch tube S 5 The negative pole of the direct current input power source is connected with the switch tube S respectively 4 Source electrode of (S) switch tube 8 Source electrode of (S) switch tube 6 Is connected with the drain electrode of the transistor; switch tube S 7 Source electrode of (S) switch tube 8 The drains of the capacitors are connected with one end of an inductor L; switch capacitor C 1 Negative electrode of (C) and switch capacitor (C) 2 The positive poles of the inductor L are connected with the other end of the inductor L; switch tube S 5 The drain electrode of (C) is respectively connected with the switch capacitor C 1 Positive electrode of (a) switching tube S 1 Is connected with the drain electrode of the transistor; switch tube S 6 The source of (C) is respectively connected with the switch capacitor C 2 Is a cathode of the switch tube S 2 Is connected with the source electrode of the transistor; the positive pole of the load is respectively connected with the switch tube S 3 Source electrode of (S) switch tube 4 The negative electrode of the load is connected with the switch tube S respectively 1 Source electrode of (S) switch tube 2 Drain connection of (c)。
As shown in fig. 2, the first operating state: switch tube S 2 Switch tube S 3 Switch tube S 5 Switch tube S 8 Conduction and switch tube S 1 Switch tube S 4 Switch tube S 6 Switch tube S 7 Are all turned off. Compared with the second working state, the switching tube S is changed 5 (switch tube S) 6 ) Switch tube S 8 (switch tube S) 7 ) Is a switching state of (a). At this time, switch capacitor C 1 Charging in parallel with DC input power supply, switch capacitor C 1 The voltage at two ends is charged to V dc Switch capacitor C 2 Discharging in series with the DC input power supply, wherein the output voltage value of the two ends of the load is 2 times of the voltage value of the DC power supply in the state, namely U o ＝+2V dc 。
As shown in fig. 3, the second operating state: switch tube S 2 Switch tube S 3 Switch tube S 6 Switch tube S 7 Conduction and switch tube S 1 Switch tube S 4 Switch tube S 5 Switch tube S 8 Are all turned off. Compared with the third working state, only the switching tube S is changed 3 (switch tube S) 4 ) Is a switching state of (a). At this time, switch capacitor C 2 A switch capacitor C connected in parallel with the DC input power supply 2 The voltage at two ends is charged to V dc Switch capacitor C 1 Idling, in which the output voltage value at the two ends of the load is equal to the DC power supply voltage value, namely U o ＝+V dc 。
As shown in fig. 4, the third operating state: switch tube S 2 Switch tube S 4 Switch tube S 6 Switch tube S 7 Conduction and switch tube S 1 Switch tube S 3 Switch tube S 5 Switch tube S 8 All turn off, at this time, the switch capacitor C 2 A switch capacitor C connected in parallel with the DC input power supply 2 The voltage at two ends is charged to V dc Switch capacitor C 1 Idle, in which the two ends of the load are short-circuited, the output voltage value of the two ends of the load is 0, namely U o ＝+0。
As shown in fig. 5, the fourth operating state: switch tube S 1 Switch tube S 3 Switch tube S 5 Switch tube S 8 Conduction and switch tube S 2 Switch tube S 4 Switch tube S 6 Switch tube S 7 All turn off, at this time, the switch capacitor C 1 A switch capacitor C connected in parallel with the DC input power supply 1 The voltage at two ends is charged to V dc Switch capacitor C 2 Idle, in which the two ends of the load are short-circuited, the output voltage value of the two ends of the load is 0, the output direction of the voltage is opposite to the output voltage of the load obtained in the third working state, namely U o ＝-0。
As shown in fig. 6, the fifth operating state: switch tube S 1 Switch tube S 4 Switch tube S 5 Switch tube S 8 Conduction and switch tube S 2 Switch tube S 3 Switch tube S 6 Switch tube S 7 Are all turned off. Compared with the fourth working state, only the switching tube S is changed 4 (switch tube S) 3 ) Is a switching state of (a). At this time, switch capacitor C 1 A switch capacitor C connected in parallel with the DC input power supply 1 The voltage at two ends is charged to V dc Switch capacitor C 2 Idling, in which the output voltage value at the two ends of the load is equal to the DC power supply voltage value, and the voltage output direction is opposite to the output voltage of the load obtained in the second working state, namely U o ＝-V dc 。
As shown in fig. 7, the sixth operating state: switch tube S 1 Switch tube S 4 Switch tube S 6 Switch tube S 7 Conduction and switch tube S 2 Switch tube S 3 Switch tube S 5 Switch tube S 8 Are all turned off. Compared with the fifth working state, the switching tube S is changed 6 (switch tube S) 5 ) Switch tube S 7 (switch tube S) 8 ) Is a switching state of (a). At this time, the switch capacitor C 2 Charging in parallel with DC input power supply, switch capacitor C 2 The voltage at two ends is charged to V dc Switch capacitor C 1 Discharging in series with the DC input power supply, wherein the output voltage value of the two ends of the load is 2 times of the voltage value of the DC power supply in the state, and the voltage output direction is the output power of the load obtained in the first working stateOpposite in pressure, i.e. U o ＝-2V dc 。
The switch capacitor C is determined from the output level states 1 、C 2 Respectively pass through the switch tube S 8 And a switch tube S 7 Thus in the switching tube S 8 Switch tube S 7 And a switch capacitor C 1 、C 2 An inductor is connected in series, and the current when the capacitor is charged can reduce the instantaneous pulse current through the inductor.
The switch tube S 1 Switch tube S 2 Switch tube S 3 Switch tube S 4 Switch tube S 5 Switch tube S 6 Switch tube S 7 And a switch tube S 8 Are power switch tubes.
Fig. 8 is a schematic diagram of driving signals of each switching tube of the inverter obtained by logically combining the six operating states in the present invention. As can be seen from fig. 8, the switching state calculation is performed using a carrier phase shift modulation strategy with a sinusoidal modulation wave compared to three triangular carriers, where |x| is the sum of the absolute values of the sinusoidal waves. The [ +2], [ +1], [ +0], [ -0], [ -1], [ -2] are respectively corresponding working states of each switch tube of the inverter under six working states of the topological structure.
Specifically, wherein [ +2]Representing load voltage U o ＝+2V dc When the inverter is in a working state corresponding to each switching tube; [+1]Representing load voltage U o ＝+V dc When the inverter is in a working state corresponding to each switching tube; [+0]Representing load voltage U o When the voltage is = +0, the working state of each switch tube of the inverter corresponds to the working state; [ -0]Representing load voltage U of inverter circuit o When the temperature is minus 0, the working state of each switching tube of the inverter corresponds to the working state; [ -1]Representing load voltage U o ＝-V dc When the inverter is in a working state corresponding to each switching tube; [ -2]Representing load voltage U of inverter circuit o ＝-2V dc And the working state of each switching tube of the inverter corresponds to the working state.
The following table shows the on-off conditions of each switching tube in the inverter in six operating states corresponding to fig. 2 to 7, wherein 0 represents the switching tube being off and 1 represents the switching tube being on.
TABLE 1 switching on and off of the switching tubes under the operating states of the proposed topology
In order to demonstrate the technical effects of the present invention, simulations were performed on the present invention. In the simulation, the DC input voltage V is taken dc 100V. As can be seen from fig. 9, the load voltage U o The waveform of (2) is five-level alternating current voltage, and the maximum load voltage is 200V, namely the direct current input voltage V dc Is 2 times as large as the above. As can be seen from fig. 10, the load current of the circuit is an alternating current.
In summary, due to the topology structure of the invention, the five-level double-voltage boost gain can be generated; because of the topological structure, the carrier phase shift modulation strategy can be adopted in actual regulation and control, and the capacitor voltage can be automatically balanced; due to the topology of the invention, the pulse current caused by the charging of the switched capacitor is small.
Claims (8)
1. A boost five-level inverter with twice voltage gain, characterized by: comprises a direct current input power supply and two switch capacitors C 1 、C 2 The device comprises an inductor L, four pairs of complementarily-conducted switching tubes and a load; wherein the four pairs of complementarily-conducted switching tubes comprise a switching tube S 1 And a switch tube S 2 Switch tube S 3 And a switch tube S 4 Switch tube S 5 And a switch tube S 6 And a switching tube S 7 And a switch tube S 8 The method comprises the steps of carrying out a first treatment on the surface of the In the switching tube S 1 Switch tube S 2 Switch tube S 3 Switch tube S 4 Switch tube S 5 Switch tube S 6 Switch tube S 7 And a switch tube S 8 The upper parts are connected in reverse parallel with a diode D; the voltage at the DC input power supply is denoted as DC input voltage V dc The ac output voltage of the inverter is denoted as load voltage u o ；
The positive pole of the direct current input power supply is respectively connected with the switch tube S 3 Switch tube S 7 Drain electrode of (d) switch tube S 5 The negative pole of the direct current input power source is connected with the switch tube S respectively 4 Source electrode of (S) switch tube 8 Source electrode of (S) switch tube 6 Is connected with the drain electrode of the transistor; switch tube S 7 Source electrode of (S) switch tube 8 The drains of the capacitors are connected with one end of an inductor L; switch capacitor C 1 Negative electrode of (C) and switch capacitor (C) 2 The positive poles of the inductor L are connected with the other end of the inductor L; switch tube S 5 The drain electrode of (C) is respectively connected with the switch capacitor C 1 Positive electrode of (a) switching tube S 1 Is connected with the drain electrode of the transistor; switch tube S 6 The source of (C) is respectively connected with the switch capacitor C 2 Is a cathode of the switch tube S 2 Is connected with the source electrode of the transistor; the positive pole of the load is respectively connected with the switch tube S 3 Source electrode of (S) switch tube 4 The negative electrode of the load is connected with the switch tube S respectively 1 Source electrode of (S) switch tube 2 Is connected to the drain of the transistor.
2. The boost five-level inverter with twice voltage gain of claim 1, wherein: when the load voltage U o ＝+2V dc Switch tube S 2 Switch tube S 3 Switch tube S 5 Switch tube S 8 Conduction and switch tube S 1 Switch tube S 4 Switch tube S 6 Switch tube S 7 All turn off, at this time, the switch capacitor C 1 Charging in parallel with DC input power supply, switch capacitor C 1 The voltage at two ends is charged to V dc Switch capacitor C 2 Discharging in series with the DC input power supply, wherein the output voltage at the two ends of the load is +2V dc 。
3. The boost five-level inverter with twice voltage gain of claim 1, wherein: when the load voltage U o ＝+V dc Switch tube S 2 Switch tube S 3 Switch tube S 6 Switch tube S 7 Conduction and switch tube S 1 Switch tube S 4 Switch tube S 5 Switch tube S 8 All turn off, at this time, the switch capacitor C 2 A switch capacitor C connected in parallel with the DC input power supply 2 The voltage at two ends is charged to V dc Switch capacitor C 1 Idle, the output voltage at the two ends of the load is +V dc 。
4. The boost five-level inverter with twice voltage gain of claim 1, wherein: when the load voltage U o When = +0, switch tube S 2 Switch tube S 4 Switch tube S 6 Switch tube S 7 Conduction and switch tube S 1 Switch tube S 3 Switch tube S 5 Switch tube S 8 All turn off, at this time, the switch capacitor C 2 A switch capacitor C connected in parallel with the DC input power supply 2 The voltage at two ends is charged to V dc Switch capacitor C 1 Idle, the two ends of the load are short-circuited under the state, and the output voltage of the two ends of the load is +0V dc 。
5. The boost five-level inverter with twice voltage gain of claim 1, wherein: when the load voltage U o When= -0, switch tube S 1 Switch tube S 3 Switch tube S 5 Switch tube S 8 Conduction and switch tube S 2 Switch tube S 4 Switch tube S 6 Switch tube S 7 All turn off, at this time, the switch capacitor C 1 A switch capacitor C connected in parallel with the DC input power supply 1 The voltage at two ends is charged to V dc Switch capacitor C 2 Idle, the two ends of the load are short-circuited under the state, and the output voltage of the two ends of the load is-0V dc 。
6. The boost five-level inverter with twice voltage gain of claim 1, wherein: when the load voltage U o ＝-V dc Switch tube S 1 Switch tube S 4 Switch tube S 5 Switch tube S 8 Conduction and switch tube S 2 Switch tube S 3 Switch tube S 6 Switch tube S 7 All turn off, at this time, the switch capacitor C 1 And direct currentInput power supply is connected in parallel, and switch capacitor C 1 The voltage at two ends is charged to V dc Switch capacitor C 2 Idle, the output voltage of the two ends of the load is-V dc 。
7. The boost five-level inverter with twice voltage gain of claim 1, wherein: when the load voltage U o ＝-2V dc Switch tube S 1 Switch tube S 4 Switch tube S 6 Switch tube S 7 Conduction and switch tube S 2 Switch tube S 3 Switch tube S 5 Switch tube S 8 All turn off, at this time, the switch capacitor C 2 Charging in parallel with DC input power supply, switch capacitor C 2 The voltage at two ends is charged to V dc Switch capacitor C 1 Discharging in series with the DC input power supply, in which the output voltage of the two ends of the load is-2V dc 。
8. The boost five-level inverter with twice voltage gain of claim 1, wherein: the switch tube S 1 Switch tube S 2 Switch tube S 3 Switch tube S 4 Switch tube S 5 Switch tube S 6 Switch tube S 7 And a switch tube S 8 Are power switch tubes.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118157508A (en) * | 2024-05-11 | 2024-06-07 | 福州大学 | Modularized multifunctional series-parallel topology switchable multi-output inverter |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN118157508A (en) * | 2024-05-11 | 2024-06-07 | 福州大学 | Modularized multifunctional series-parallel topology switchable multi-output inverter |
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