CN1163482A - Semiconductor integrated circuit device with leak reducing circuit device - Google Patents
Semiconductor integrated circuit device with leak reducing circuit device Download PDFInfo
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- CN1163482A CN1163482A CN 97102373 CN97102373A CN1163482A CN 1163482 A CN1163482 A CN 1163482A CN 97102373 CN97102373 CN 97102373 CN 97102373 A CN97102373 A CN 97102373A CN 1163482 A CN1163482 A CN 1163482A
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Abstract
The invention relates to a circuit and method for reducing leakage current as transistor is not activated. In the first embodiment, the circuit selectively excites grid of the transistor to a voltage level higher than source voltage. As a result, gate-source voltage is reversed and leakage current flowing through the transistor is greatly reduced. In the second embodiment, the circuit makes well of the transistor to selectively bias to a voltage level higher than normal bias voltage. As a result, voltage-current character of the transistor is corrected as to substantially eliminate leakage current.
Description
Present invention generally relates to the semiconductor design technology, relate to the apparatus and method that are used for reducing the leakage current in the semiconductor circuit more precisely.
Because the progress of many-sided technology, integrated circuit (being chip) contains millions of transistors on same monolithic device.This just provides lot of advantages, comprise that speed improves and size reduces, but along with number of transistors purpose on the single chip increases, the caused electric current of each transistor has just more and more become problem.Because all crystals pipe on the same chip will never all activate simultaneously, and transistor only just causes electric current in its activation in theory, so this problem has obtained alleviating slightly.But transistor also causes little leakage current really when not activating.Though the leakage current of single transistor generally is about several micromicroamperes and since single chip on transistorized number very big, so each not activating transistor cause that all several picoampires have just become very big electric current.
For example, Fig. 1 a and 1b show a conventional P-channel metal-oxide-semiconductor (PMOS) transistor 10a and a correspondent voltage-current curve 10b.Transistor 10a has a grid G, source S, a leakage D and a trap W.Trap W is biased to the voltage identical with the voltage that is added on source S usually.By means of working as voltage V
GSForm the P type raceway groove (not shown) of minority carrier when being added on transistor in trap W between source-drain junction (not shown), transistor 10a just is activated.
Be in operation, if voltage V
GSFor negative, then transistor 10a is activated and causes drain current I shown in Figure 10 b
DIf voltage V
GSEqual 0V, then transistor 10a does not activate and drain current I
DNear 0 peace.Yet, because transistor 10a still causes very little leakage current I
LK(causing this electric current to flow through leakage-source knot by the minority carrier that still is in the P ditch) is so drain current also not exclusively reaches 0 ampere.
Therefore, need a kind of transistor that makes and to work in circuit and method in the pattern that leakage current reduced significantly.The method that reduces leakage current was described in United States Patent (USP) 5274601 (on December 28th, 1993), 5408144 (April 18 nineteen ninety-five) and 5521527 (on Mays 28th, 1996).
Therefore, the invention provides circuit and the method that reduces the leakage current that transistor causes when not activating.In first embodiment, circuit optionally is activated to the voltage level that is higher than source voltage with transistorized grid.As a result, gate source voltage is reversed, and makes to flow through transistorized leakage current and reduce greatly.In a second embodiment, circuit optionally is biased to the voltage level that is higher than normal bias voltage with transistorized trap.As a result, transistorized voltage-current characteristic is corrected, and leakage current is eliminated basically.
The technological merit that obtains with the present invention is that it makes transistor work in normal mode with typical voltage-current characteristic, or works in ready mode with the leakage current that has reduced greatly.
Fig. 1 a is conventional transistorized schematic diagram.
Fig. 1 b is the transistorized voltage-to-current curve of Fig. 1 a.
Fig. 2 is the schematic diagram that embodies a circuit of first embodiment of the invention.
Fig. 3 is the schematic diagram that embodies a circuit of second embodiment of the invention.
Fig. 4 is transistorized voltage-current characteristic figure in Fig. 3 circuit.
Fig. 5 adopts a DRAM block diagram of the present invention.
Fig. 6 is an another embodiment of the present invention.
As mentioned above, Fig. 1 a and 1b show a conventional transistor and its voltage-current characteristic respectively.The conventional transistor such as transistor 10a is adopted in following description, thereby the description of most preferred embodiment will be adopted and independent component and the characteristic of reference crystal pipe 10a.
With reference to Fig. 2, reference number 12 general expressions embody first embodiment of the integrated circuit of characteristics of the present invention.Circuit 12 utilizes one first positive supply (V
PERI), second a positive supply (V
PP) and a ground level power supply (V
SS), V wherein
SS＜V
PERI＜V
PPFor example, think V respectively
SS, V
PERIAnd V
PPEqual 0V, 2.5V and 3.6V.Circuit 12 comprises an input signal IN, stand-by signal STB, output signal OUT, two phase inverters 14 and 16, path transistors 18 and a stand-by transistor 20.Phase inverter 14 comprises a P-channel metal-oxide-semiconductor (PMOS) transistor 22 and a n ditch metal-oxide semiconductor (MOS) (NMOS) transistor 24, and phase inverter 16 comprises a PMOS transistor 26 and a nmos pass transistor 28.And all nmos pass transistors 18,24,28 all have a V
SSThe trap of biasing, the trap of a PMOS transistor 20 is V
PPBiasing, two PMOS transistors 22 and 26 trap are V
PERIBiasing.
Be in operation, when stand-by signal STB is " height " (V
PP) time, circuit 12 is in normal mode and with the form work of conventional driver.The signal that receives at input signal IN place is by 14 paraphase of phase device, by path transistor 18, by phase inverter 16 paraphase once more, and is energized at output signal OUT place.But when stand-by signal STB is " low " (V
SS) time, circuit 12 enters ready mode.Because stand-by signal STB is " low ", path transistor (first switching transistor) 18 becomes and does not activate, and stand-by transistor (second switch transistor) 20 becomes activation.At this moment, the input N1 of phase inverter 16 is enhanced V
PPVoltage level (3.6V).As a result, the voltage V of transistor 26
GSJust become,, reduced the number of the minority carrier in source transistor-drain junction raceway groove, thereby reduced shown in Fig. 1 b by transistorized leakage current (I because the voltage at transistor 26 grid places is located voltage greater than the source
LK).
With reference to Fig. 3, reference number 30 general expressions embody second embodiment of the integrated circuit of characteristics of the present invention.Circuit 30 adopts three the power supply Vs identical with circuit 12 (Fig. 2)
SS, V
PERIAnd V
PP, and comprise identical signal IN, OUT and STB.Circuit 30 also comprises two phase inverters 32 and 34 and two trap bias transistors 36 and 38.Phase inverter 32 comprises a PMOS transistor 40 and a nmos pass transistor 42, and phase inverter 34 comprises a PMOS transistor 44 and a nmos pass transistor 46.And the trap of all nmos pass transistors 38,42,46 all is V
SSBiasing, the trap of PMOS transistor 36 is V
PPBiasing, the trap of PMOS transistor 40 is V
PERIBiasing.The trap of PMOS transistor 44 is connected in two its source electrodes and is connected to V
PERIAnd V
PP Trap bias transistor 36 and 38.
Be in operation, when stand-by signal STB is " height " (V
PP) time, circuit 30 is in normal mode and with the form work of conventional driver.The signal that receives at input signal IN place by phase inverter 32 paraphase, again by phase inverter 34 paraphase, and is energized at output signal OUT place.Because stand-by signal STB is " height ", trap bias transistor 38 activates so trap bias transistor 36 does not activate.As a result, the trap of PMOS transistor 44 is biased to V
PERI(2.5V) and with normal usual manner work.But when stand-by signal STB is " low " (V
SS) time, circuit 30 enters ready mode.In ready mode, trap bias transistor 38 does not activate and 36 activation of trap bias transistor.As a result, the trap of PMOS transistor 44 is biased to V
PP(3.6V) also work in a different manner, as described below.
With reference to Fig. 4, curve 50 comprises a dotted line 52 and a solid line 54.Dotted line 52 expression V
PERIThe voltage-current characteristic of the transistor 44 of trap biasing, just in time alike with the conventional transistor 10a of Fig. 1.V in solid line 54 presentation graphs 3
PPThe voltage-current characteristic of the transistor 44 of trap biasing.By means of with bias voltage V
PP(3.6V) add to the trap of transistor 44, trap is biased to and is higher than transistorized source voltage (source voltage is V
PERIVoltage level).As a result, the voltage-current characteristic of transistor 44 is offset from the normal attribute shown in the dotted line 52.Because this skew is as voltage V
GSDuring for 0V, corresponding leakage current I
LKReduced significantly.
Fig. 5 shows and adopts a DRAM block diagram of the present invention.DRAM shown in this figure is produced on the single Semiconductor substrate that is made of single piece of silicon with the semiconductor circuit manufacturing process.
This DRAM receives the outer power voltage VDD of 3.3V and the ground voltage VSS of 0V from the external power source termination.Memory array (MARY) 1 comprise word line, data wire to and dynamic storage cell.In the DRAM of this embodiment, each transistor of storage array 1 is made to increase storage capacity by compactness.When reducing the grid length of MOS transistor, gate oxidation films is also done thin.Reduce the operating voltage of storage array 1 thus, adopted the voltage VARY that has reduced, for example 2.0V.Substrate bias voltage VBB (1V) is added on the substrate (well region) of having made MOS transistor on it.
By means of receiving external address signal A0-Ai, decoder and word line driver (DEC/WDRIV) 2 selected a predetermined word line.Voltage VPERI to peripheral circuit has adopted such as the reduction of 2.5V has obtained low power consumption.Starting voltage such as 3.6V is used to encourage word line.Circuit of the present invention shown in Fig. 2 and 3 can be used for the decoding district in above-mentioned decoder and the word line driver 2.
Circuit shown in Figure 6 shows another embodiment of the present invention.Transistor 61,62,65 and 66 is corresponding to transistor shown in Figure 2 26,28,22 and 24.In the embodiment of Fig. 6, provide first and second switching transistors 64 and 63 to reduce the leakage current that in nmos pass transistor 62, flows when nmos pass transistor 62 turn-offs.
In circuit shown in Figure 2, output signal is fixed in " low " (VSS).On the contrary, when standby conditions, output signal is fixed in high level (VPERI).In Fig. 6, when stand-by signal STB was low (VBB), PMOS transistor 64 was opened, and nmos pass transistor 63 turn-offs, and can obtain the output signal OUT corresponding to input signal IN.In addition, when stand-by signal STB was high (VPERI), circuit was in standby conditions.At this moment, PMOS transistor 64 turn-offs and nmos pass transistor 63 unlatchings.In the standby conditions process, the gate voltage of nmos pass transistor 62 (VBB) becomes and is lower than source voltage (VSS).As a result, nmos pass transistor 62 is fully turn-offed, thereby has reduced leakage current.
Though described exemplary embodiment of the present invention, in aforementioned disclosing, can make an amendment, change and replace, and in some cases, need not other characteristics of corresponding employing and just can use some characteristic of the present invention.For example, just can realize reducing the purpose of leakage current in register or buffer, only be to describe in order to be easy to and be described with driver.And nmos pass transistor also can cause leakage current, thereby also may benefit from application of the present invention.At last, can also add the element of extra other and other circuit and not change scope of the present invention.Therefore, should admit that appended what is claimed is conforms to scope of the present invention widely.
Claims (21)
1, a kind of output circuit, it comprises:
First end that is used for receiving positive voltage;
Second end that is used for receiving the ground level supply voltage; And
One first phase inverter, it comprises a PMOS transistor and nmos pass transistor that is connected in series between above-mentioned first and second ends;
Wherein, in normal mode, be added on the input signal of the grid of above-mentioned PMOS and nmos pass transistor as above-mentioned first phase inverter, its first voltage level is equivalent to above-mentioned ground level supply voltage, and second voltage level is equivalent to above-mentioned positive voltage, and
Wherein, in ready mode, the above-mentioned input signal of above-mentioned first phase inverter has the tertiary voltage level that is higher than above-mentioned positive voltage level.
2, the output circuit according to claim 1 also comprises:
One second phase inverter;
The 3rd end that is used for receiving voltage with above-mentioned tertiary voltage level;
A first transistor, it provides a source-drain path between the input of the output of above-mentioned second phase inverter and above-mentioned first phase inverter; And
A transistor seconds, it provides a source-drain path between the input of above-mentioned first phase inverter and above-mentioned the 3rd end;
Wherein, in above-mentioned normal mode, above-mentioned the first transistor activates and above-mentioned transistor seconds does not activate, and
Wherein, in above-mentioned ready mode, above-mentioned the first transistor does not activate and the activation of above-mentioned transistor seconds.
3, a kind of output circuit, it comprises:
First end that is used for receiving positive voltage;
Second end that is used for receiving the ground level supply voltage; And
A phase inverter, it comprises a PMOS transistor and nmos pass transistor that is connected in series between above-mentioned first and second ends,
Wherein, in normal mode, first voltage level that is equivalent to above-mentioned supply voltage is added to the transistorized trap of above-mentioned PMOS,
And wherein, in ready mode, second voltage level is added to the transistorized above-mentioned trap of above-mentioned PMOS, and above-mentioned second voltage level is higher than the level of above-mentioned positive voltage.
4, a kind of circuit that is used for reducing leakage current in the transistor, this circuit comprises that a grid is connected in circuit input end, drain electrode is connected in circuit output end and source electrode is connected in the output transistor of first power supply and be used for optionally making grid to disconnect with input and make grid be connected in the device of second source, and wherein the voltage level of second source is higher than the first power source voltage level.
5, the circuit of claim 4 wherein is used for optionally connecting and the device that disconnects comprises a PMOS transistor and a nmos pass transistor that is connected between grid and the input that is connected between grid and the second source.
6, a kind of method that is used for making the PMOS transistor optionally to change between normal mode (this moment, the PMOS transistor was worked in a usual manner) and ready mode (the transistorized leakage current of PMOS this moment is reduced greatly), the method comprise optionally the transistorized grid of PMOS are connected to the power supply that voltage level is higher than the transistorized source voltage of PMOS.
7, the method for claim 6, wherein in normal mode, the transistorized grid of PMOS is connected to input signal, works in to be less than or equal to PMOS source transistor power source voltage level.
8, a kind of method that is used for making nmos pass transistor optionally to change between normal mode (this moment, nmos pass transistor was worked in a usual manner) and ready mode (this moment, the leakage current of nmos pass transistor was reduced greatly), the method comprise and optionally transistorized grid are connected to the power supply that voltage level is lower than the source voltage of nmos pass transistor.
9, the method for claim 8, wherein in normal mode, the grid of nmos pass transistor is connected to input signal, works in the voltage level that is greater than or equal to nmos pass transistor source voltage.
10, a kind of circuit that is used for reducing the leakage current in the transistor, this circuit comprises that input, drain electrode that a grid is connected in circuit are connected in output and source electrode is connected in the output transistor of first power supply and be used for optionally the trap of this output transistor being connected in the device of first power supply or second source, and wherein the voltage level of second source is higher than the first power source voltage level.
11, the circuit of claim 10, the device that wherein is used for optionally connecting comprises one first trap bias transistor and one second trap bias transistor, the first trap bias transistor wherein is connected to first power supply with the trap of output transistor, and the second trap bias transistor is connected to second source with the trap of output transistor.
12, the trap that a kind of method that is used for making output transistor optionally to change between normal mode (this moment, output transistor was worked in a usual manner) and ready mode (leakage current that flows through output transistor this moment is reduced), the method comprise optionally output transistor is connected in one of two separate power source.
13, the method for claim 12, selectivity Connection Step wherein comprises activation and is connected in series in the trap of output transistor and the first trap bias transistor between first power supply, or activation is connected in series in the trap of output transistor and the second trap bias transistor between the second source.
14, a kind of semiconductor memory, it comprises:
A memory array;
A peripheral circuit that is connected in above-mentioned memory array; And
A generation is higher than the booster circuit of the second source voltage of first supply voltage,
Wherein said peripheral circuit comprises: (a) grid is connected in that input, drain electrode are connected in output and source electrode receives the output transistor of above-mentioned first supply voltage and (b) switching circuit, it is fed to above-mentioned grid with above-mentioned second source voltage, and above-mentioned grid is disconnected from above-mentioned input.
15, according to the semiconductor memory of claim 14, the high level that wherein adds to the input signal of above-mentioned input is equivalent to the level of above-mentioned first supply voltage.
16, according to the semiconductor memory of claim 15, wherein said peripheral circuit is a decoder, and it produces the selection signal of an above-mentioned memory array by means of the receiver address signal.
17, a kind of semiconductor memory, it comprises:
A memory array;
A decoder that is connected in above-mentioned memory array;
A control circuit, control signal of its output is to be in operate as normal attitude or standby conditions to indicate above-mentioned decoder; And
A booster circuit, it produces a second source voltage that is higher than first supply voltage,
Wherein said decoder comprises: comprise (a) that a PMOS transistor gate is connected in input, drain electrode is connected in output and source electrode receives the output circuit of above-mentioned first supply voltage and (b) switching circuit, it is fed to above-mentioned grid with above-mentioned second source voltage, and above-mentioned grid is disconnected from above-mentioned input.
18, comprise also according to the semiconductor memory of claim 17 that a grid is connected in above-mentioned input, drain electrode is connected in above-mentioned output and source electrode receives the nmos pass transistor of ground level voltage.
19, according to the semiconductor memory of claim 18, wherein said switching circuit comprises: (a) one provide between above-mentioned nmos pass transistor and transistorized public grid of PMOS and the above-mentioned input active-leak first switch mos transistor of passage and (b) one in the second switch MOS transistor that active-leakage passage is provided between above-mentioned public grid and the end points that receives above-mentioned second source voltage.
20, according to the semiconductor memory of claim 19, wherein said first switch mos transistor is a nmos pass transistor, above-mentioned second switch MOS transistor is a PMOS transistor, and above-mentioned control signal is added to the public grid of above-mentioned first and second switch mos transistors.
21, according to the semiconductor memory of claim 19, the high level that wherein adds to the input signal of above-mentioned input is equivalent to the level of above-mentioned first supply voltage, and the low level of input signal is equivalent to above-mentioned ground level voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 97102373 CN1163482A (en) | 1996-01-30 | 1997-01-29 | Semiconductor integrated circuit device with leak reducing circuit device |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US010,073 | 1996-01-30 | ||
| CN 97102373 CN1163482A (en) | 1996-01-30 | 1997-01-29 | Semiconductor integrated circuit device with leak reducing circuit device |
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|---|---|
| CN1163482A true CN1163482A (en) | 1997-10-29 |
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|---|---|---|---|
| CN 97102373 Pending CN1163482A (en) | 1996-01-30 | 1997-01-29 | Semiconductor integrated circuit device with leak reducing circuit device |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100375388C (en) * | 1999-04-30 | 2008-03-12 | 英特尔公司 | Integrated circuit low leakage power circuitry for use with advanced CMOS process |
| CN102693753A (en) * | 2011-03-22 | 2012-09-26 | 台湾积体电路制造股份有限公司 | Sense amplifier |
| CN109979501A (en) * | 2017-12-28 | 2019-07-05 | 长鑫存储技术有限公司 | Drain current suppressing circuit and the memory circuit structure for applying it |
| CN112557935A (en) * | 2020-12-11 | 2021-03-26 | 重庆西南集成电路设计有限责任公司 | High-precision battery string single cell voltage detection system based on voltage moving |
-
1997
- 1997-01-29 CN CN 97102373 patent/CN1163482A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100375388C (en) * | 1999-04-30 | 2008-03-12 | 英特尔公司 | Integrated circuit low leakage power circuitry for use with advanced CMOS process |
| CN102693753A (en) * | 2011-03-22 | 2012-09-26 | 台湾积体电路制造股份有限公司 | Sense amplifier |
| CN109979501A (en) * | 2017-12-28 | 2019-07-05 | 长鑫存储技术有限公司 | Drain current suppressing circuit and the memory circuit structure for applying it |
| CN109979501B (en) * | 2017-12-28 | 2021-03-19 | 长鑫存储技术有限公司 | Leakage current suppression circuit and memory circuit structure using same |
| CN112557935A (en) * | 2020-12-11 | 2021-03-26 | 重庆西南集成电路设计有限责任公司 | High-precision battery string single cell voltage detection system based on voltage moving |
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