CN116346231B - Multi-channel E1 data transmission system and method based on Ethernet PHY chip - Google Patents
Multi-channel E1 data transmission system and method based on Ethernet PHY chip Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
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- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
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- H—ELECTRICITY
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- H04Q11/00—Selecting arrangements for multiplex systems
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Abstract
The invention discloses a multipath E1 data transmission system and a multipath E1 data transmission method based on an Ethernet PHY chip, wherein the multipath E1 data transmission system comprises two identical first devices and second devices which are used for interconnecting and transmitting Ethernet signals and E1 signals, the multipath E1 data transmission method comprises the steps that the first devices receive multipath E1 signals, the multipath E1 signals are multiplexed into E2 data streams through single-double conversion, the received Ethernet signals are converted into parallel MII interfaces to transmit Ethernet data, each group of E2 data streams and the Ethernet data are time division multiplexed into total data streams and sent to the Ethernet PHY chip of the first device, and the clock frequency of the Ethernet PHY chip is calculated and set based on the bandwidth of the Ethernet signal transmission and the bandwidth of the E2 data streams; the ethernet PHY chip transmits the total data stream to the second device. The system and the method for transmitting the multi-path E1 data based on the Ethernet PHY chip realize the low-cost and reliable multi-path E1 and Ethernet transmission and ensure that the bandwidth of the Ethernet is not occupied.
Description
Technical Field
The invention relates to the technical field of network communication, in particular to a multipath E1 data transmission system and method based on an Ethernet PHY chip.
Background
The E1 interface adopts a PCM coding mode, accords with the G.703 standard, and is an interface standard commonly used by a transmission network in large-scale domestic systems such as a military system, a power system and the like. Ethernet is a commonly used computer local area network technology. The Ethernet and the E1 are combined, multiplexing of the Ethernet and the E1 is realized, the requirement on high-capacity data transmission can be met, and the access functions of telephone service and other special communication systems can be realized.
In the existing implementation method, most of the implementation methods adopt an FPGA with a high-speed serial transceiver to transmit data, and the cost is relatively high. In addition, other implementation methods are a method of converting E1 data into an Ethernet data packet and transmitting the Ethernet data packet, but occupying the bandwidth of the Ethernet.
Disclosure of Invention
In order to overcome the defects of the technology, the invention provides a multipath E1 data transmission system based on an Ethernet PHY chip, and the cost of the multipath E1 and the Ethernet transmission system is reduced by setting the clock frequency of the Ethernet PHY chip, so that the bandwidth of the Ethernet is ensured not to be occupied.
The technical scheme adopted for overcoming the technical problems is as follows: the first aspect of the present invention proposes a multipath E1 data transmission system based on an ethernet PHY chip, which at least includes two identical first devices and second devices for interconnecting and transmitting ethernet signals and E1 signals, where the first devices or the second devices at least include a circuit board. The circuit board at least comprises a logic control circuit module, an E1 circuit module, an Ethernet circuit module, a PHY chip module and a data transceiver module, wherein the E1 circuit module, the Ethernet circuit module and the PHY chip module are respectively coupled with the logic control circuit module; two ends of the E1 circuit module are respectively coupled with an external E1 interface and a logic control circuit module and are used for single-double conversion or double-single conversion of E1 signals; the two ends of the Ethernet circuit module are respectively coupled with an external Ethernet and a logic control circuit module and are used for converting serial and parallel signals of the Ethernet signals; the logic control circuit module at least comprises an E1 multiplexing unit, an E1 tapping unit, a total data multiplexing unit and a total data tapping unit,
the output ends of the E1 multiplexing unit and the Ethernet circuit module are coupled with the total data multiplexing unit, the E1 tapping unit and the input end of the Ethernet circuit module are coupled with the total data tapping unit, the data output end of the total data multiplexing unit and the data input end of the total data tapping unit are respectively coupled with the PHY chip module, the PHY chip module at least comprises a PHY chip, and the clock frequency of the PHY chip is calculated and set based on the bandwidth of Ethernet signal transmission and the bandwidth of a data stream of E1 data signal multiplexing; the PHY chip module is used for outputting the total data stream received by the data receiving and transmitting module to the total data tapping unit, or receiving the total data stream output by the total data multiplexing unit and outputting the total data stream to the receiving and transmitting module; the total data multiplexing unit is used for multiplexing the E1 signal output by the E1 multiplexing unit and the Ethernet signal output by the Ethernet circuit module into a total data stream; the total data tapping unit is used for tapping the received total data stream into an E1 signal and an Ethernet signal, outputting the E1 signal to the E1 tapping unit and outputting the Ethernet signal to the Ethernet module.
E1 data is converted and multiplexed with Ethernet data to form a total data stream, and the bandwidth of the Ethernet is ensured not to be occupied by calculating and setting a clock used by a PHY chip.
Further, the E1 multiplexing unit is configured to multiplex the received E1 signal into a plurality of groups of E2 data streams, and output the groups of E2 data streams to the total data multiplexing unit.
Further, the E1 tap is configured to tap the E2 data stream received from the total data tap into a plurality of E1 signals to the E1 circuit module.
Further, the data transceiver module is an optical fiber module.
The data transmission of the total data flow is realized through the low-price light module, and the data transmission is carried out without adopting an FPGA with a high-speed serial transceiver, so that the cost of combining and transmitting E1 data and Ethernet data is greatly saved.
The invention also provides a multi-path E1 data transmission method based on the Ethernet PHY chip, which is applied to the multi-path E1 data transmission system based on the Ethernet PHY chip, and comprises a transmission method for receiving an external E1 signal and an Ethernet signal by a first device and forwarding the external E1 signal and the Ethernet signal to a second device, and specifically comprises the following steps: the first equipment receives external multipath E1 signals and respectively carries out single-double conversion; the first equipment receives an external Ethernet signal, performs serial-parallel signal conversion on the external Ethernet signal, and converts the external Ethernet signal into parallel MII interface transmission Ethernet data; multiplexing the multi-path E1 signals subjected to single-double conversion into N groups of E2 data streams, wherein each E2 data stream comprises N paths of E1 signals; the method comprises the steps of time division multiplexing each group of E2 data streams and Ethernet data into total data streams and sending the total data streams to an Ethernet PHY chip of first equipment, wherein the clock frequency of the Ethernet PHY chip is calculated and set based on the bandwidth of Ethernet signal transmission and the bandwidth of the E2 data streams; the ethernet PHY chip transmits the total data stream to a second device in the multi-way E1 data transmission system.
Further, the method for transmitting the data of the total data stream of the second device received by the first device specifically includes: the second device receives the total data stream transmitted by the first device and forwards the total data stream through an Ethernet PHY chip of the second device, wherein the clock frequency of the Ethernet PHY chip of the second device is equal to the clock frequency of the Ethernet PHY chip of the first device; the total data stream forwarded by the Ethernet PHY chip is demultiplexed and multiplexed into an E2 data stream and Ethernet data; the E2 data stream is divided into multiple paths of E1 data, and then double single conversion transmission is carried out to the outside; the Ethernet data is converted into serial Ethernet data and then transmitted to the outside.
Further, the clock frequency of the ethernet PHY chip is calculated based on the bandwidth of the ethernet signal transmission and the bandwidth of the E2 data stream, and specifically includes: the time length of each transmission frame period of the total data stream is T, the frame frequency is F, the time length of the E2 data stream occupying each transmission frame period is T1, the bandwidth is BW1, the time length of the Ethernet data occupying each transmission frame period is T2, the bandwidth is BW2, the transmission bandwidth of the E2 data stream is BW1 xF, the bandwidth BW2 xF of the Ethernet transmission is, the clock frequency of the total data stream is set to be > BW1 xF+BW2 xF > the transmission bandwidth required by the Ethernet standard.
Further, the clock frequency of the transmission total data stream is set to be a multiple of BW1 xf.
The clock frequency of the Ethernet PHY chip can be set according to the Ethernet signal transmission bandwidth and the E2 data stream bandwidth calculation, so that the Ethernet bandwidth is not occupied.
Further, each transmission frame of the total data stream transmission includes at least each group of E2 data streams and ethernet data.
Further, each transmission frame further includes control data.
The beneficial effects of the invention are as follows:
1. and the FPGA with the high-speed serial transceiver is not used for transmitting data, so that the cost of combining E1 data and Ethernet data for transmission is greatly saved.
2. E1 data is converted and multiplexed with Ethernet data to form a total data stream, and the bandwidth of the Ethernet is ensured not to be occupied by calculating and setting a clock used by a PHY chip.
3. The data transmission of the total data stream is realized only through the low-cost optical fiber module, so that the transmission of multiple paths of E1 signals and Ethernet signals is realized, and the cost of combining and transmitting E1 data and Ethernet data is further saved.
Drawings
Fig. 1 is a schematic diagram of a multi-path E1 data transmission system based on an ethernet PHY chip according to an embodiment of the present invention;
FIG. 2 is a schematic block diagram of a first/second device according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of data flow in a device according to an embodiment of the present invention;
FIG. 4 is a schematic block diagram of a logic control circuit module according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of the overall data flow;
fig. 6 is a flowchart of a transmission method in which a first device receives an external E1 signal and an ethernet signal and forwards the external E1 signal and the ethernet signal to a second device according to an embodiment of the present invention;
fig. 7 is a flowchart of a data transmission method in which a first device receives a total data stream of a second device according to an embodiment of the present invention.
Detailed Description
The invention will now be described in further detail with reference to the drawings and the specific examples, which are given by way of illustration only and are not intended to limit the scope of the invention, in order to facilitate a better understanding of the invention to those skilled in the art.
As shown in fig. 1, a schematic diagram of a multi-path E1 data transmission system based on an ethernet PHY chip according to this embodiment at least includes two identical first devices and second devices for interconnecting and transmitting ethernet signals and E1 signals, where the first/second devices receive external ethernet signals and E1 signals and convert the external ethernet signals and E1 signals into total data streams for transmission to the second/first devices, and the second/first devices convert the received total data streams into ethernet signals and E1 signals for transmission to the outside.
It should be noted that two devices may implement simultaneous input, and the input and output are relatively independent.
As shown in fig. 2, the functional block diagram of the first/second device, either the first device or the second device includes at least a circuit board,
the circuit board comprises a logic control circuit module, an E1 circuit module, an Ethernet circuit module, a PHY chip module and a data transceiver module, wherein the E1 circuit module, the Ethernet circuit module and the PHY chip module are respectively coupled with the logic control circuit module. The function of each circuit module is described below in terms of the data transfer flow shown in fig. 3.
Two ends of the E1 circuit module are respectively coupled with an external E1 interface and the logic control circuit module.
In one embodiment of the invention, the E1 circuit module at least comprises 16E 1 interfaces, an E1 transformer and an E1 single-double conversion unit. The 16-path E1 interface is used for directly connecting external multipath E1 signals. E1 transformers are used for filtering, isolation and impedance transformation. The E1 single-double conversion unit is used for single-double conversion or double-single conversion of E1 signals, namely conversion between single-path bipolar codes and double-path unipolar codes.
As shown in fig. 3, two ends of the ethernet circuit module are respectively coupled to an external ethernet and a logic control circuit module, and the ethernet data received from the outside is converted into parallel MII interface ethernet data RXD [0:3] by the ethernet circuit module, or the received parallel MII interface ethernet data TXD [0:3] is converted into serial ethernet data.
In one embodiment of the invention, the externally connected ethernet is a hundred mega ethernet.
As shown in fig. 4, the logic control circuit module includes at least an E1 multiplexing unit, an E1 tapping unit, a total data multiplexing unit, and a total data tapping unit.
And the E1 multiplexing unit multiplexes the received multipath E1 data subjected to single-double conversion of the E1 circuit module into an E2 data stream, and sends the E2 data stream to the total data multiplexing unit.
In one embodiment of the present invention, as shown in FIG. 4, the E1 multiplexing unit multiplexes 16 paths of E1 data of 2.048MHz, each 4 paths being a group, into 4 paths of E2 data streams E2R [0:3] of 8.448MHz, and sends the data streams to the total data multiplexing unit.
The total data multiplexing unit also receives parallel MII interface Ethernet data RXD [0:3] output by the Ethernet circuit module, the corresponding clock RXCLK is 25.34 MHz, RXDV is an effective signal, and the E2 data stream E2R [0:3] and the Ethernet data RXD [0:3] adopt a time division multiplexing mode to transmit data to the PHY chip module.
It should be noted that time division multiplexing is to transmit different signals using different time periods of the same physical connection, that is, dividing the time of transmitting information by a channel into a plurality of time slots, and allocating each time slot to a corresponding signal source for use. The 4E 2 data streams, ethernet data and some control data are multiplexed into a total data stream TXD [0:3], and sent to the PHY chip module, the corresponding clock TXCLK is 38.016MHz, TXEN is an enable signal.
Fig. 5 is a schematic diagram of time division multiplexing, and the corresponding data is transmitted in different time periods according to time division. Each transmission frame period has a duration of T, a frame rate of F, and a total bandwidth of bw= 38.016MHz. The duration of each transmission frame period occupied by the E2 data stream is t1, the bandwidth is BW1, the total bandwidth occupied by the E2 is BW1×F=8.448 MHz, the duration of each transmission frame period occupied by the Ethernet is t2, the bandwidth is BW2, the total bandwidth occupied by the Ethernet is BW2×F=25.344 MHz, wherein BW > BW1×F+BW2×F= 33.792MHz, a small amount of bandwidth is occupied to transmit some control data for positioning and state interaction, BW needs to take a value slightly larger than 33.792 and needs to take a multiple relation of 8.448 so as to be convenient for locking a phase-locked loop, and BW takes 38.016MHz; the frame frequency F is 8KHz, which is the same as the common frame frequency of the E1 signal, and the length of each frame is 38.016M/8K=4752 bits, wherein E2 data is 8.448M/8K=1056 bits, ethernet data is 25.344M/8K=3168 bits, and the rest is control data; the specific frame structure is 16bits (idle code) +16bits (preamble+synchronization code) +1056bits (E2 data) +16bits (idle code) +3168bits (ethernet data) +16bits (idle code) +464bits (state interaction code) =4752 bits. The 38.016MHz bandwidth is equal to the MII interface clock frequencies TXCLK and RXCLK of the PHY chip.
The PHY chip module receives the total data stream and outputs the total data stream RXD [0:3] to the total data tapping unit, the corresponding clock RXCLK is 38.016MHz, RXDV is an effective signal, the total data tapping unit taps the total data stream RXD [0:3] into 4 paths of E2 data streams E2T [0:3] of 8.448MHz and sends the E1 tapping unit, the tapped Ethernet data TXD [0:3] is sent to the Ethernet circuit module, the corresponding clock TXCLK is 25.34 MHz, and TXEN is an enabling signal.
And the E1 tapping unit taps the received E2 data stream E2R [0:3] into 16 paths of E1 data and sends the 16 paths of E1 data to the E1 circuit module.
The PHY chip module at least comprises a PHY chip and comprises an MII interface and a differential serial interface, wherein the MII interface is connected with the logic control circuit module, and the differential serial interface is connected with the data transceiver module.
In one embodiment of the invention, the MII interface of the PHY chip uses a clock frequency higher than 25MHz, 38.016MHz, which is commonly used for Ethernet, so that larger volumes of data can be transferred. It should be noted that, TXCLK and RXCLK in fig. 3 and fig. 4 are output by the logic control module. The two clocks on the ethernet circuit module side are both 25.344MHz and the two clocks on the phy chip module side are both 38.016MHz.
The data receiving and transmitting module comprises an optical module, and the optical modules between the two devices are connected through optical fibers.
In one embodiment of the invention, the PHY chip and the 155M optical fiber module are adopted, so that the cost is low, the FPGA of the high-speed serial transceiver is not needed, the requirement can be met, and the cost is greatly reduced.
It should be noted that other fiber optic modules with rates greater than 155M may be used, and the cost is far lower than FPGAs using high-speed serial transceivers.
The invention also provides a multi-path E1 data transmission method of the Ethernet PHY chip based on the multi-path E1 data transmission system, and a flow chart is shown in FIG. 6. The data transmission method in which the first device receives the external E1 signal and the ethernet signal and forwards the received signals to the second device includes the following steps, and each step is described below in this embodiment.
S11, the first equipment receives external multipath E1 signals and respectively carries out single-double conversion.
In one embodiment of the present invention, the first device receives an external 16-way E1 signal, sends the external 16-way E1 signal to the E1 single-double conversion circuit through the E1 transformer in the E1 circuit module, and sends the external 16-way E1 signal to the E1 multiplexing unit of the logic control circuit module after the single-double conversion is completed.
S12, the first device receives an external Ethernet signal, converts the external Ethernet signal into a parallel MII interface and transmits the Ethernet data.
In one embodiment of the present invention, the first device receives an external ethernet signal, converts the external ethernet signal into parallel MII interface ethernet data RXD [0:3] through the ethernet circuit module, and outputs the ethernet data RXD to the total data multiplexing unit of the logic control circuit module, where the corresponding clock RXCLK is 25.34 mhz and rxdv is an effective signal.
S13, multiplexing the multi-path E1 signals subjected to single-double conversion into N groups of E2 data streams, wherein each E2 data stream comprises N paths of E1 signals.
The E1 multiplexing unit of the logic control circuit module multiplexes the E1 data of 16 paths of 2.048MHz into 4 paths of E2 data streams E2R [0:3] of 8.448MHz, wherein in one embodiment of the invention, N=4 and n=4 are sent to the total data multiplexing module.
And S14, multiplexing each group of E2 data streams and Ethernet data into total data streams in a time division manner, and sending the total data streams to an Ethernet PHY chip of the first device, wherein the clock frequency of the Ethernet PHY chip is calculated and set based on the bandwidth of Ethernet signal transmission and the bandwidth of the E2 data streams.
The total data multiplexing module adopts a time division multiplexing mode to transmit data. In one embodiment of the invention, 4E 2 data streams, ethernet data and some control data are multiplexed into a total data stream TXD [0:3], which is sent to the PHY chip module with a corresponding clock TXCLK of 38.016MHz and TXEN as an enable signal.
Wherein, the duration of each transmission frame period is T, the frame frequency is F, and the total bandwidth is bw= 38.016MHz. The duration of each transmission frame period occupied by the E2 data stream is t1, the bandwidth is BW1, the total bandwidth occupied by E2 is BW1×F=8.448 MHz, the duration of each transmission frame period occupied by the Ethernet is t2, the bandwidth is BW2, the total bandwidth occupied by the Ethernet is B2×F=25.344 MHz, wherein BW > BW1×F+BW2×F= 33.792MHz, a small amount of bandwidth is occupied to transmit some control data for positioning and state interaction, BW needs to take a value slightly larger than 33.792 and needs to be a multiple of 8.448 so as to facilitate locking of a phase-locked loop, and BW takes 38.016MHz; the frame frequency F is 8KHz, which is the same as the common frame frequency of the E1 signal, and the length of each frame is 38.016M/8k=4752 bits, wherein the E2 data is 8.448M/8k=1056 bits, the ethernet data is 25.344M/8k=3168 bits, and the rest is control data.
In one embodiment of the present invention, the specific frame structure is 16bits (idle code) +16bits (preamble+sync code) +1056bits (E2 data) +16bits (idle code) +3168bits (ethernet data) +16bits (idle code) +464bits (state interaction code) =4752 bits.
And S15, the Ethernet PHY chip transmits the total data stream to a second device in the multi-path E1 data transmission system.
The PHY chip receives the total data stream and transmits the total data stream to the opposite terminal equipment through the data transceiver module, namely the optical fiber.
In one embodiment of the present invention, the method further includes a data transmission method for receiving, by the first device, a total data stream of the second device, where the flowchart is shown in fig. 7, and specifically includes:
s21, the second device receives the total data stream transmitted by the first device and forwards the total data stream through an Ethernet PHY chip of the second device, wherein the clock frequency of the Ethernet PHY chip of the second device is equal to that of the Ethernet PHY chip of the first device.
The data transceiver module of the second device receives the total data stream and transmits the total data stream to the PHY chip module, the PHY chip module transmits the total data stream RXD [0:3] to the logic control circuit module, the corresponding clock RXCLK is 38.016MHz, and RXDV is an effective signal.
S22, the total data stream forwarded by the Ethernet PHY chip is demultiplexed and multiplexed into E2 data stream and Ethernet data.
The total data tapping unit in the logic control circuit module taps the total data flow into 4 paths of E2 data flow E2T [0:3] of 8.448MHz, and sends the total data flow into the E1 tapping unit, taps Ethernet data TXD [0:3], and sends the total data flow into the Ethernet circuit module, the corresponding clock TXCLK is 25.34 MHz, and TXEN is an enabling signal.
S23, after the E2 data stream is tapped into multiple paths of E1 data, double single conversion transmission is carried out to the outside.
The E1 tapping unit taps the 4 paths of E2 data streams into 16 paths of E1 data and sends the 16 paths of E1 data to the E1 circuit module, and the E1 circuit module performs double-single conversion on the 16 paths of E1 data and sends the 16 paths of E1 data to the E1 transformer to be transmitted to the outside through an E1 interface.
S24, converting the Ethernet data into serial Ethernet data and transmitting the serial Ethernet data to the outside.
The Ethernet circuit module converts the parallel MII interface Ethernet data into serial Ethernet data, and transmits the serial Ethernet data to the outside through the Ethernet interface.
In one embodiment of the invention, the clock frequency of the ethernet PHY chip is calculated based on the bandwidth of the ethernet signal transmission and the E2 data stream bandwidth.
Wherein, the duration of each transmission frame period is T, the frame frequency is F, and the total bandwidth is bw= 38.016MHz. The duration of each transmission frame period occupied by the E2 data stream is t1, the bandwidth is BW1, the total bandwidth occupied by the E2 is BW1 xf=8.448 MHz, the duration of each transmission frame period occupied by the ethernet is t2, the bandwidth is BW2, the total bandwidth occupied by the ethernet is BW2 xf=25.344 MHz, wherein BW > BW1 xf+bw 2 xf= 33.792MHz, a small amount of bandwidth is required to transmit some control data for positioning and state interaction, BW is required to take a value slightly larger than 33.792 and a multiple relation of 8.448 is required to facilitate locking of a phase-locked loop, and BW takes 38.016MHz.
The multichannel E1 data transmission system and method based on the Ethernet PHY chip provided by the invention abandons the scheme of transmitting data by using a common FPGA with a high-speed serial transceiver, and does not need to convert E1 data into an Ethernet data packet for transmission by using the Ethernet. The Ethernet PHY chip is adopted, and the transmission of the total data stream is realized through the setting of the clock frequency of the Ethernet PHY chip and the optical fiber module. On the premise of ensuring that the bandwidth of the Ethernet is not occupied, the reliable and low-cost combination transmission of the multipath E1 and the Ethernet is realized.
It should be noted that: in other embodiments, the steps of the corresponding method are not necessarily performed in the order shown and described in this specification. In some other embodiments, the method may include more or fewer steps than described in this specification. Furthermore, individual steps described in this specification, in other embodiments, may be described as being split into multiple steps; while various steps described in this specification may be combined into a single step in other embodiments.
In this specification, each embodiment is described in a progressive manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for a system or system embodiment, since it is substantially similar to a method embodiment, the description is relatively simple, with reference to the description of the method embodiment being made in part. The system and system embodiments described above are merely illustrative, and some or all of the modules may be selected according to actual needs to achieve the objectives of the present embodiment. Those of ordinary skill in the art will understand and implement the present invention without undue burden.
Claims (8)
1. A multiplex E1 data transmission system based on ethernet PHY chips, comprising at least two identical first and second devices for interconnecting the transmission of ethernet signals and E1 signals, each of said first and second devices comprising at least a circuit board, characterized in that,
the circuit board at least comprises a logic control circuit module, an E1 circuit module, an Ethernet circuit module, a PHY chip module and a data transceiver module, wherein the E1 circuit module, the Ethernet circuit module and the PHY chip module are respectively coupled with the logic control circuit module;
two ends of the E1 circuit module are respectively coupled with an external E1 interface and a logic control circuit module and are used for single-double conversion or double-single conversion of E1 signals;
the two ends of the Ethernet circuit module are respectively coupled with an external Ethernet and a logic control circuit module and are used for converting serial and parallel signals of the Ethernet signals;
the logic control circuit module at least comprises an E1 multiplexing unit, an E1 tapping unit, a total data multiplexing unit and a total data tapping unit,
the output ends of the E1 multiplexing unit and the Ethernet circuit module are coupled with the total data multiplexing unit, and the E1 multiplexing unit is used for multiplexing the received E1 signals into a plurality of groups of E2 data streams and outputting the groups of E2 data streams to the total data multiplexing unit;
the input ends of the E1 tapping unit and the Ethernet circuit module are coupled with the total data tapping unit, and the E1 tapping unit is used for tapping the E2 data stream received from the total data tapping unit into a plurality of paths of E1 signals to the E1 circuit module;
the data output end of the total data multiplexing unit and the data input end of the total data tapping unit are respectively coupled with the PHY chip module,
the PHY chip module at least comprises a PHY chip, and the clock frequency of the PHY chip is calculated and set based on the bandwidth of Ethernet signal transmission and the bandwidth of data stream multiplexed by E1 data signals;
the PHY chip module is used for outputting the total data stream received by the data receiving and transmitting module to the total data tapping unit, or receiving the total data stream output by the total data multiplexing unit and outputting the total data stream to the receiving and transmitting module;
the total data multiplexing unit is used for multiplexing the E1 signal output by the E1 multiplexing unit and the Ethernet signal output by the Ethernet circuit module into a total data stream;
the total data tapping unit is used for tapping the received total data stream into an E1 signal and an Ethernet signal, outputting the E1 signal to the E1 tapping unit and outputting the Ethernet signal to the Ethernet module.
2. The ethernet PHY chip-based multiplexed E1 data transmission system of claim 1 wherein the data transceiver module is a fiber optic module.
3. The multi-path E1 data transmission method based on an ethernet PHY chip, applied to the multi-path E1 data transmission system based on an ethernet PHY chip as set forth in claim 1 or 2, includes a transmission method in which a first device receives an external E1 signal and an ethernet signal and forwards the external E1 signal to a second device, and is characterized in that the method specifically includes:
the first equipment receives external multipath E1 signals and respectively carries out single-double conversion;
the first equipment receives an external Ethernet signal to perform serial-parallel signal conversion, and converts the external Ethernet signal into parallel MII interface transmission Ethernet data;
multiplexing the multi-path E1 signals subjected to single-double conversion into N groups of E2 data streams, wherein each E2 data stream comprises N paths of E1 signals;
the method comprises the steps of time division multiplexing each group of E2 data streams and Ethernet data into total data streams and sending the total data streams to an Ethernet PHY chip of first equipment, wherein the clock frequency of the Ethernet PHY chip is calculated and set based on the bandwidth of Ethernet signal transmission and the bandwidth of the E2 data streams;
the ethernet PHY chip transmits the total data stream to a second device in the multi-way E1 data transmission system.
4. The method for multiplexed E1 data transmission based on an ethernet PHY chip of claim 3 further comprising a data transmission method for receiving, by the first device, a total data stream of the second device, specifically comprising:
the second device receives the total data stream transmitted by the first device and forwards the total data stream through an Ethernet PHY chip of the second device, wherein the clock frequency of the Ethernet PHY chip of the second device is equal to the clock frequency of the Ethernet PHY chip of the first device;
the total data stream forwarded by the Ethernet PHY chip is demultiplexed and multiplexed into an E2 data stream and Ethernet data;
the E2 data stream is divided into multiple paths of E1 data, and then double single conversion transmission is carried out to the outside;
the Ethernet data is converted into serial Ethernet data and then transmitted to the outside.
5. The method for multiplexed E1 data transmission based on an ethernet PHY chip according to claim 3 or claim 4, wherein the clock frequency of the ethernet PHY chip is calculated based on a bandwidth of ethernet signal transmission and a bandwidth of an E2 data stream, and specifically includes:
the duration of each transmission frame period of the total data stream is T, the frame frequency is F, the duration of the E2 data stream occupies each transmission frame period is T1, the bandwidth is BW1, the duration of the Ethernet data occupies each transmission frame period is T2, the bandwidth is BW2,
the bandwidth of the E2 data stream is BW1 xf, the bandwidth of the ethernet transmission BW2 xf, and the clock frequency of the total data stream is set to > BW1 xf+bw 2 xf > the transmission bandwidth required by the ethernet standard.
6. The method for multi-path E1 data transmission based on an ethernet PHY chip of claim 5 wherein the clock frequency of the total data stream transmitted is set to a multiple of BW1 xf.
7. The method of claim 5, wherein each transmission frame of the total data stream transmission includes at least each group of E2 data streams and ethernet data.
8. The method for multiplexed E1 data transmission based on an ethernet PHY chip of claim 7 wherein each of the transmission frames further includes control data.
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