CN116345878A - Dead time control circuit - Google Patents
Dead time control circuit Download PDFInfo
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- CN116345878A CN116345878A CN202310546876.5A CN202310546876A CN116345878A CN 116345878 A CN116345878 A CN 116345878A CN 202310546876 A CN202310546876 A CN 202310546876A CN 116345878 A CN116345878 A CN 116345878A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/38—Means for preventing simultaneous conduction of switches
- H02M1/385—Means for preventing simultaneous conduction of switches with means for correcting output voltage deviations introduced by the dead time
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0048—Circuits or arrangements for reducing losses
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/157—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/28—Modifications for introducing a time delay before switching
- H03K17/284—Modifications for introducing a time delay before switching in field effect transistor switches
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Inverter Devices (AREA)
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Abstract
A dead time control circuit comprises a detection control module, a driving module and a power device module; the power device module comprises an upper arm power transistor Q1 and a lower arm power transistor Q2; the driving module comprises an upper arm power transistor driving inverter group and a lower arm power transistor driving inverter group; the detection control module comprises a first logic combination unit for starting and stopping the upper arm power transistor Q1 and a second logic combination unit for starting and stopping the lower arm power transistor Q2. The invention is used for avoiding the phenomenon that the chip is penetrated between the power supply voltage and the ground wire in the power supply voltage conversion process, and can reduce the loss in the dead time of the chip.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, and relates to a dead time control circuit.
Background
The buck driving circuit is a module in the buck conversion chip, and in order to avoid the punch-through phenomenon from the power supply voltage to the ground wire in the power supply voltage conversion process of the chip, a dead time control circuit is generated, and is commonly used for executing a protection control circuit of the buck conversion chip in normal operation.
The dead time control circuit typically includes a buck drive circuit. Referring to fig. 1, fig. 1 is a schematic diagram of a prior art step-down driving circuit. As shown in fig. 1, the circuit includes a driving unit and a power transistor. Wherein the driving unit comprises a plurality of inverters, and the closer to the inverter of the power transistor, the larger the size. The power transistors include a power transistor Q1 and a power transistor Q2.
When the clock signal CLK is shifted in high-low level, the power transistor Q1 and the power transistor Q2 are also shifted in high-low level, and during the shifting of the power transistor Q1 and the power transistor Q2, the power transistor Q1 and the power transistor Q2 are turned on briefly at the same time, so that a current from the power source VIN to the ground GND, called a punch-through current, is generated.
Referring to fig. 2, fig. 2 is a waveform diagram of a prior art step-down driving circuit. As shown in fig. 2, the current IQ1 and the current IQ2 are punch-through currents, and the presence of the punch-through currents IQ1 and IQ2 may bring about two hazards:
(1) the conversion efficiency of the buck chip can be reduced;
(2) the excessive through current can cause the chip to burn out.
Referring to fig. 3, fig. 3 is a schematic diagram of another prior art step-down driving control circuit for avoiding punch-through current. As shown in fig. 3, the circuit comprises a detection control unit, a driving unit and a power device unit. The detection control unit comprises a detection delay unit 1, a detection delay unit 2 and a logic combination unit. The power interfaces of all logic units in the detection control unit are connected with the power VIN signal, and the ground interface is grounded to the ground end GND. Wherein, the detection delay unit 1 and the detection delay unit 2,
the detection delay unit 1 may include an inverter circuit and a delay capacitor C1; it is used to detect whether the gate signal LG of the lower arm power transistor Q2 reaches a sufficiently low potential to turn off the lower arm power transistor Q2.
The detection delay unit 2 may include an inverter circuit and a delay capacitor C2; it is used to detect whether the gate signal UG of the upper arm power transistor Q1 reaches a certain potential to turn off the upper arm power transistor Q1.
The high level of the logic combination unit is connected with the VIN signal, the low level is connected with the GND signal, and the output signals of the logic combination unit are respectively supplied to the driving units. The logic combination unit may include an and circuit and an or circuit, where the and circuit is connected to the output signal of the detection delay unit 1 and an original driving switch signal CLK, respectively; the or circuit is respectively connected with the output signal of the detection delay unit 2 and an original driving switch signal CLK.
The driving unit may include a plurality of inverter units.
The power transistor unit may include an upper arm power transistor Q1 and a lower arm power transistor Q2; wherein the drains of power transistor Q1 and power transistor Q2 are connected together.
Referring to fig. 4, fig. 4 is a schematic waveform diagram of the step-down driving circuit in fig. 3. As shown in fig. 4, when the detection delay unit 1 detects that the lower arm power transistor Q1 is turned off, a high level delay signal is generated; the original driving switch signal CLK is conducted by an AND gate X1 and is conducted by an upper arm power transistor controlled by a plurality of inverter modules; since the lower arm power transistor Q2 is already completely turned off at this time, no punch-through current is generated.
When the detection delay unit 2 detects that the upper arm power transistor Q1 is closed, a low-level delay signal is generated; the original driving switch signal CLK passes through the OR gate X2 and controls the conduction of the lower arm power transistor Q2 through a plurality of inverter modules; since the upper arm power transistor Q1 is already completely turned off at this time, no punch-through current is generated any more; the time when the upper arm power transistor Q1 and the lower arm power transistor Q2 are simultaneously turned off is referred to as dead time (dead time).
However, the above-mentioned prior art has the following problems:
the drive control circuit for avoiding the punch-through current generally has less accurate control over the dead time, because the detection level for detecting whether the power transistor Q1 and the power transistor Q2 are turned off in the detection delay unit may vary with the deviation of the process and the variation of the power supply VIN.
In addition, the delay unit also changes along with the deviation of the process and the change of the power supply VIN; the dead time deviation produced under different process batches is large, and the efficiency of the buck chip under heavy load is reduced due to the large dead time design; the small dead time design also causes the reduction of the chip conversion efficiency of the buck chip due to the poor through current inhibition effect; and the existence of the delay capacitor also increases the chip design area.
Disclosure of Invention
In order to solve the above technical problems, the present invention provides a dead time control circuit for avoiding a punch-through phenomenon from a power supply voltage to a ground line in a power supply voltage conversion process of a chip, and reducing a loss in the dead time of the chip.
In order to achieve the above purpose, the technical scheme of the invention is as follows:
a dead time control circuit comprises a detection control module, a driving module and a power device module; and
the power device module comprises an upper arm power transistor Q1 and a lower arm power transistor Q2; the drains of the upper arm power transistor Q1 and the lower arm power transistor Q2 are connected together; the source electrode of the upper arm power transistor Q1 is connected with a power supply VIN, and the source electrode of the lower arm power transistor Q2 is connected with a ground end GND;
the driving module comprises an upper arm power transistor driving inverter group and a lower arm power transistor driving inverter group, wherein the upper arm power transistor driving inverter group is formed by cascading a plurality of inverters; the lower arm power transistor driving inverter group is formed by cascading a plurality of inverters; the inverter is powered by the power source VIN;
the detection control module comprises:
the first logic combination unit is connected with a power source VIN at a power source port, and connected with a grid signal of a power transistor Q2 at a low-level grounding end; the first logic combination unit outputs a fixed high-level signal to turn off the upper arm power transistor Q1 when the grid level of the lower arm power transistor Q2 is high; when the grid level of the lower arm power transistor Q2 is low, transmitting an original driving switch signal CLK to the upper arm power transistor driving inverter group of the driving module, and starting the upper arm power transistor Q1;
the power supply port of the second logic combination unit is connected with the gate signal of the power transistor Q1, and the low-level grounding end of the second logic combination unit is connected with the ground end GND; the second logic combination unit outputs a fixed low-level signal to turn off the lower arm power transistor Q2 when the grid level of the upper arm power transistor Q1 is low; when the gate level of the upper arm power transistor Q1 is high, an original driving switching signal CLK is transmitted to the lower arm driving inverter group of the driving module, and the lower arm power transistor Q2 is turned on.
Further, the first and second logic combination units are one of nor gate XNOR1, inverter XINV1, and nand gate XNAND.
Further, the dead time control circuit is characterized by further comprising a third logic combination unit, wherein the power port power VIN of the third logic combination unit is connected with the ground GND; the third logic combination unit includes an inverter INV3 and an inverter INV4; the input end of the inverter INV3 is connected with the gate signal of the power transistor Q2, and the output end of the inverter INV3 is connected with the first logic unit; the input end of the inverter INV4 is connected with the gate of the power transistor Q1, and the output end is connected with the second logic combination unit.
Further, the dead time control circuit is characterized by further comprising a fourth logic combination unit, wherein the power supply VIN of the fourth logic combination unit is connected with the ground GND through a low-level ground terminal; the fourth logic combination unit comprises an inverter INVE1 and an inverter INVE2; the input end of the inverter INVE1 is connected with an enabling signal ENX, and the output end of the inverter INVE1 is connected with the first logic unit; the input end of the inverter INVE2 is connected with the output end of the inverter INVE1, and the output signal is connected with the second logic combination unit.
According to the technical scheme, the dead time control circuit in the embodiment of the invention has the advantages that the delay control circuit is reduced, the independent tube control circuit is added, the punch-through protection can be effectively improved under the normal working condition of the chip, and meanwhile, the loss in the dead time of the chip is reduced, so that the working efficiency of the chip is improved.
Drawings
FIG. 1 is a schematic diagram of a prior art buck driving circuit
FIG. 2 is a schematic waveform diagram of a prior art step-down driving circuit
FIG. 3 is a schematic diagram of a prior art step-down drive control circuit for avoiding punch-through current
Fig. 4 is a waveform diagram of the step-down driving circuit in fig. 3. As shown in figure four
FIG. 5 is a schematic diagram of a dead time control circuit according to a preferred embodiment of the present invention
FIG. 6 is a schematic diagram of a dead time control circuit according to another preferred embodiment of the present invention
FIG. 7 is a schematic diagram of a dead time control circuit according to another embodiment of the present invention
Detailed Description
Embodiments of the present invention will now be described in further detail with reference to FIGS. 5-7.
It should be noted that, the present invention is different from the prior art in the following points: in the dead time control circuit, the detection delay unit 1 and the detection delay unit 2 in the prior art are replaced by adding the detection control circuit module, so that the problem that the dead time is usually not accurately controlled by a drive control circuit of the through current is solved, namely, the dead time is greatly reduced while the through current is avoided, and the conversion efficiency of a buck chip is improved.
The dead time control circuit of the present invention is described in detail below by way of three specific embodiments.
Example 1
Referring to fig. 5, fig. 5 is a schematic diagram of a dead time control circuit according to a preferred embodiment of the invention. As shown in fig. 5, the dead time control circuit includes a detection control module, a driving module and a power device module.
As in the prior art, the power device module may include an upper arm power transistor Q1 and a lower arm power transistor Q2; the drains of the upper arm power transistor Q1 and the lower arm power transistor Q2 are connected together; the source of the upper arm power transistor Q1 is connected to the power source VIN, and the source of the lower arm power transistor Q2 is connected to the ground GND.
The driving module can comprise an upper arm power transistor driving inverter group and a lower arm power transistor driving inverter group, wherein the upper arm power transistor driving inverter group is formed by cascading a plurality of inverters; the lower arm power transistor driving inverter group is formed by cascading a plurality of inverters; the inverter is powered by the power source VIN.
That is, the power device module and the driving module employed in the related art may be employed by the embodiment of the present invention.
Unlike the prior art, in the embodiment of the present invention, the added detection control module may include a first logic combination unit and a second logic combination unit.
The first logic combination unit is connected with a power source VIN at a power source port, and connected with a grid signal of a power transistor Q2 at a low-level grounding end; the first logic combination unit outputs a fixed high-level signal to turn off the upper arm power transistor Q1 when the grid level of the lower arm power transistor Q2 is high; when the grid level of the lower arm power transistor Q2 is low, transmitting an original driving switch signal CLK to the upper arm power transistor driving inverter group of the driving module, and starting the upper arm power transistor Q1;
the power supply port of the second logic combination unit is connected with the gate signal of the power transistor Q1, and the low-level grounding end of the second logic combination unit is connected with the ground end GND; the second logic combination unit outputs a fixed low-level signal to turn off the lower arm power transistor Q2 when the grid level of the upper arm power transistor Q1 is low; when the gate level of the upper arm power transistor Q1 is high, an original driving switching signal CLK is transmitted to the lower arm driving inverter group of the driving module, and the lower arm power transistor Q2 is turned on.
The first and second logic combination units are one of a nor gate XNOR, an inverter XINV, and a nand gate xnnand. As shown in fig. 5, the first logic combination unit and the second logic combination unit are an upper arm power switch detection inverter XINV1 and a lower arm power switch detection inverter XINV2, respectively.
The working principle is as follows:
when the gate level of the lower arm power transistor Q2 is still a high level signal, the ground port of the low level of the first logic combination unit is also a high level, and the output of the first logic combination unit is a high level potential, so that the upper arm power transistor Q1 is turned off by the driving unit; when the gate level of the lower arm power transistor Q2 is lowered to a certain degree to turn off the lower arm power transistor Q2, the ground port of the first logic combination unit also becomes low level because of its low level, so that the original driving switching signal CLK is transmitted to the upper arm power transistor inverter through the first logic combination unit, so that the upper arm power transistor Q1 is turned on.
And (3) the same principle: when the grid level of the upper arm power transistor Q1 is still a low level signal, the second logic combination unit is also low level because the power port of the second logic combination unit is also low level, and the output of the second logic combination unit is low level potential, so that the lower arm power transistor Q2 is turned off through the driving unit; when the gate level of the upper arm power transistor Q1 rises to a certain degree to turn off the upper arm power transistor Q1, the second logic combination unit also rises to a high level potential because the power port of the second logic combination unit, so that the original driving switch signal CLK is transmitted to the lower arm power transistor inverter through the second logic combination unit, and the lower arm power transistor Q2 is turned on; thus, the punch-through current caused by the simultaneous conduction of the two power transistors can be perfectly avoided; dead time can also be greatly reduced.
Example 2
Fig. 6 is a schematic diagram of another embodiment of the dead time control circuit according to the present invention. As shown in fig. 6, the dead time control circuit includes a detection control unit, a driving unit and a power device unit.
As in the prior art, the power device module may include an upper arm power transistor Q1 and a lower arm power transistor Q2; the drains of the upper arm power transistor Q1 and the lower arm power transistor Q2 are connected together; the source of the upper arm power transistor Q1 is connected to the power source VIN, and the source of the lower arm power transistor Q2 is connected to the ground GND.
The driving module can comprise an upper arm power transistor driving inverter group and a lower arm power transistor driving inverter group, wherein the upper arm power transistor driving inverter group is formed by cascading a plurality of inverters; the lower arm power transistor driving inverter group is formed by cascading a plurality of inverters; the inverter is powered by the power source VIN.
That is, the power device module and the driving module employed in the related art may be employed by the embodiment of the present invention.
Unlike the prior art, in the embodiment of the present invention, the added detection control module may include a first logic combination unit, a second logic combination unit, and a third logic combination unit.
The first logic combination unit is connected with a power source VIN at a power source port, and connected with a grid signal of a power transistor Q2 at a low-level grounding end; the first logic combination unit outputs a fixed high-level signal to turn off the upper arm power transistor Q1 when the grid level of the lower arm power transistor Q2 is high; when the gate level of the lower arm power transistor Q2 is low, the original driving switch signal CLK is transmitted to the upper arm power transistor driving inverter group of the driving module, and the upper arm power transistor Q1 is turned on.
The power supply port of the second logic combination unit is connected with the gate signal of the power transistor Q1, and the low-level grounding end of the second logic combination unit is connected with the ground end GND; the second logic combination unit outputs a fixed low-level signal to turn off the lower arm power transistor Q2 when the grid level of the upper arm power transistor Q1 is low; when the gate level of the upper arm power transistor Q1 is high, an original driving switching signal CLK is transmitted to the lower arm driving inverter group of the driving module, and the lower arm power transistor Q2 is turned on.
In addition, the first and second logic combination units are one of a nor gate XNOR, an inverter XINV, and a nand gate xnnand. As shown in fig. 6, the first and second logic combination units are nand gate XNAND1 and nor gate XNOR1, respectively.
The working principle is as follows:
when the gate level of the lower arm power transistor Q2 is still a high level signal, the ground port of the low level of the first logic combination unit is also a high level, and the output of the first logic combination unit is a high level potential, so that the upper arm power transistor Q1 is turned off by the driving unit; when the gate level of the lower arm power transistor Q2 is lowered to a certain degree to turn off the lower arm power transistor Q2, the ground port of the first logic combination unit also becomes low level because of its low level, so that the original driving switching signal CLK is transmitted to the upper arm power transistor inverter through the first logic combination unit, so that the upper arm power transistor Q1 is turned on.
Similarly, when the gate level of the upper arm power transistor Q1 is still a low level signal, the power port of the second logic combination unit is also low level, and the output of the second logic combination unit is low level, so that the lower arm power transistor Q2 is turned off by the driving unit; when the gate level of the upper arm power transistor Q1 rises to a certain degree to turn off the upper arm power transistor Q1, the second logic combination unit also rises to a high level potential because of its power port, so that the original driving switch signal CLK is transmitted to the lower arm power transistor inverter through the second logic combination unit, so that the lower arm power transistor Q2 is turned on.
As shown in fig. 6, the third logic combination unit has a power supply port VIN, and a low-level ground terminal connected to the ground terminal GND; the third logic combination unit includes an inverter INV3 and an inverter INV4; the input end of the inverter INV3 is connected with the gate signal of the power transistor Q2, and the output end of the inverter INV3 is connected with the first logic unit; the input end of the inverter INV4 is connected with the gate of the upper arm power transistor Q1, and the output end is connected with the second logic combination unit.
When the gate level of the upper arm power transistor Q1 is still a low level signal, the inverter INV4 outputs a high level signal, and the high level signal may make the output of the second logic combination unit be a low level, so that the upper arm power transistor Q2 is turned off by the driving module; thus, the punch-through current caused by the simultaneous conduction of the two power transistors can be perfectly avoided, and the dead time can be greatly reduced.
Example 3
Referring to fig. 7, fig. 7 is a schematic diagram of a dead time control circuit according to another preferred embodiment of the invention. As shown in fig. 7, the dead time control circuit includes a detection control module, a driving module and a power device module.
As in the prior art, the power device module may include an upper arm power transistor Q1 and a lower arm power transistor Q2; the drains of the upper arm power transistor Q1 and the lower arm power transistor Q2 are connected together; the source of the upper arm power transistor Q1 is connected to the power source VIN, and the source of the lower arm power transistor Q2 is connected to the ground GND.
The driving module can comprise an upper arm power transistor driving inverter group and a lower arm power transistor driving inverter group, wherein the upper arm power transistor driving inverter group is formed by cascading a plurality of inverters; the lower arm power transistor driving inverter group is formed by cascading a plurality of inverters; the inverter is powered by the power source VIN.
That is, the power device module and the driving module employed in the related art may be employed by the embodiment of the present invention.
Unlike the prior art, in the embodiment of the present invention, the added detection control module may include a first logic combination unit, a second logic combination unit, and a fourth logic combination unit.
The first logic combination unit is connected with a power source VIN at a power source port, and connected with a grid signal of a power transistor Q2 at a low-level grounding end; the first logic combination unit outputs a fixed high-level signal to turn off the upper arm power transistor Q1 when the grid level of the lower arm power transistor Q2 is high; when the gate level of the lower arm power transistor Q2 is low, the original driving switch signal CLK is transmitted to the upper arm power transistor driving inverter group of the driving module, and the upper arm power transistor Q1 is turned on.
The power supply port of the second logic combination unit is connected with the gate signal of the power transistor Q1, and the low-level grounding end of the second logic combination unit is connected with the ground end GND; the second logic combination unit outputs a fixed low-level signal to turn off the lower arm power transistor Q2 when the grid level of the upper arm power transistor Q1 is low; when the gate level of the upper arm power transistor Q1 is high, an original driving switching signal CLK is transmitted to the lower arm driving inverter group of the driving module, and the lower arm power transistor Q2 is turned on.
The first and second logic combination units are one of a nor gate XNOR, an inverter XINV, and a nand gate xnnand. As shown in fig. 7, the first and second logic combination units are nand gate XNAND2 and nor gate XNOR2, respectively.
The working principle is as follows:
when the gate level of the lower arm power transistor Q2 is still a high level signal, the ground port of the low level of the first logic combination unit is also a high level, and the output of the first logic combination unit is a high level potential, so that the upper arm power transistor Q1 is turned off by the driving unit; when the gate level of the lower arm power transistor Q2 is reduced to a certain degree to turn off the lower arm power transistor Q2, the ground port of the first logic combination unit also becomes low level because of its low level, so that the original driving switch signal CLK is transmitted to the upper arm power transistor inverter through the first logic combination unit, so that the upper arm power transistor Q1 is turned on.
Similarly, when the gate level of the upper arm power transistor Q1 is still a low level signal, the power port of the second logic combination unit is also low level, and the output of the second logic combination unit is low level, so that the lower arm power transistor Q2 is turned off by the driving unit; when the gate level of the upper arm power transistor Q1 rises to a certain degree to turn off the upper arm power transistor Q1, the second logic combination unit also rises to a high level potential because of its power port, so that the original driving switch signal CLK is transmitted to the lower arm power transistor inverter through the second logic combination unit, so that the lower arm power transistor Q2 is turned on.
As shown in fig. 7, the power source VIN of the fourth logic combination unit has a low-level ground terminal connected to the ground terminal GND; the fourth logic combination unit comprises an inverter INVE1 and an inverter INVE2; the input end of the inverter INVE1 is connected with an enabling signal ENX, and the output end of the inverter INVE1 is connected with the first logic unit; the input end of the inverter INVE2 is connected with the output end of the inverter INVE1, and the output signal is connected with the second logic combination unit.
When the ENX signal is high, the inverter INVE1 is output low and the inverter INVE2 is output high. This forces the first logic cell output high and the second logic cell output low, so that transistors Q1 and Q2 of the upper and lower arms can be turned off simultaneously. Therefore, the dead time is greatly reduced, and the power upper arm power transistor Q1 and the power lower arm power transistor Q2 are turned off at the same time when the chip works abnormally, so that the chip is prevented from being burnt.
The foregoing description is only of the preferred embodiments of the present invention, and the embodiments are not intended to limit the scope of the invention, so that all changes made in the equivalent structures of the present invention described in the specification and the drawings are included in the scope of the invention.
Claims (4)
1. The dead time control circuit is characterized by comprising a detection control module, a driving module and a power device module; and
the power device module comprises an upper arm power transistor Q1 and a lower arm power transistor Q2; the drains of the upper arm power transistor Q1 and the lower arm power transistor Q2 are connected together; the source electrode of the upper arm power transistor Q1 is connected with a power supply VIN, and the source electrode of the lower arm power transistor Q2 is connected with a ground end GND;
the driving module comprises an upper arm power transistor driving inverter group and a lower arm power transistor driving inverter group, wherein the upper arm power transistor driving inverter group is formed by cascading a plurality of inverters; the lower arm power transistor driving inverter group is formed by cascading a plurality of inverters; the inverter is powered by the power source VIN;
the detection control module comprises:
the first logic combination unit is connected with a power source VIN at a power source port, and connected with a grid signal of a power transistor Q2 at a low-level grounding end; the first logic combination unit outputs a fixed high-level signal to turn off the upper arm power transistor Q1 when the grid level of the lower arm power transistor Q2 is high; when the grid level of the lower arm power transistor Q2 is low, transmitting an original driving switch signal CLK to the upper arm power transistor driving inverter group of the driving module, and starting the upper arm power transistor Q1;
the power supply port of the second logic combination unit is connected with the gate signal of the power transistor Q1, and the low-level grounding end of the second logic combination unit is connected with the ground end GND; the second logic combination unit outputs a fixed low-level signal to turn off the lower arm power transistor Q2 when the grid level of the upper arm power transistor Q1 is low; when the gate level of the upper arm power transistor Q1 is high, an original driving switching signal CLK is transmitted to the lower arm driving inverter group of the driving module, and the lower arm power transistor Q2 is turned on.
2. The dead time control circuit of claim 1 wherein the first and second logic combination units are one of nor gate XNOR1, inverter XINV1, and nand gate XNAND.
3. The dead time control circuit according to claim 1 or2, further comprising a third logic combination unit having a power supply port power VIN, a low-level ground terminal connected to the ground terminal GND; the third logic combination unit includes an inverter INV3 and an inverter INV4; the input end of the inverter INV3 is connected with the gate signal of the power transistor Q2, and the output end of the inverter INV3 is connected with the first logic unit; the input end of the inverter INV4 is connected with the gate of the power transistor Q1, and the output end is connected with the second logic combination unit.
4. The dead time control circuit according to claim 1 or2, further comprising a fourth logic combination unit having a power supply VIN, a low-level ground terminal connected to the ground terminal GND; the fourth logic combination unit comprises an inverter INVE1 and an inverter INVE2; the input end of the inverter INVE1 is connected with an enabling signal ENX, and the output end of the inverter INVE1 is connected with the first logic unit; the input end of the inverter INVE2 is connected with the output end of the inverter INVE1, and the output signal is connected with the second logic combination unit.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310546876.5A CN116345878A (en) | 2023-05-15 | 2023-05-15 | Dead time control circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310546876.5A CN116345878A (en) | 2023-05-15 | 2023-05-15 | Dead time control circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117439398A (en) * | 2023-12-20 | 2024-01-23 | 成都市易冲半导体有限公司 | Dead time optimization circuit and method, control circuit thereof and push-pull output circuit |
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- 2023-05-15 CN CN202310546876.5A patent/CN116345878A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117439398A (en) * | 2023-12-20 | 2024-01-23 | 成都市易冲半导体有限公司 | Dead time optimization circuit and method, control circuit thereof and push-pull output circuit |
| CN117439398B (en) * | 2023-12-20 | 2024-03-01 | 成都市易冲半导体有限公司 | Dead time optimization circuit and method, control circuit thereof and push-pull output circuit |
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