CN116344622A - SGT MOSFET device with low output capacitance and manufacturing method - Google Patents

SGT MOSFET device with low output capacitance and manufacturing method Download PDF

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CN116344622A
CN116344622A CN202310596206.4A CN202310596206A CN116344622A CN 116344622 A CN116344622 A CN 116344622A CN 202310596206 A CN202310596206 A CN 202310596206A CN 116344622 A CN116344622 A CN 116344622A
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type
region
control gate
polysilicon
polycrystalline silicon
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王志明
张鹏
宋文龙
杨珏琳
许志峰
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Jiangsu Jilai Microelectronics Co ltd
Chengdu Jilaixin Technology Co ltd
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Jiangsu Jilai Microelectronics Co ltd
Chengdu Jilaixin Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

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Abstract

The invention discloses an SGT MOSFET device with low output capacitance and a manufacturing method thereof, and relates to the technical field of electronic devices.

Description

SGT MOSFET device with low output capacitance and manufacturing method
Technical Field
The invention relates to the technical field of electronic devices, in particular to an SGT MOSFET device with low output capacitance and a manufacturing method thereof.
Background
Power semiconductor devices are mainly used for power supplies and driving loads of various devices. All electronic systems require both a power supply to power them and a push load (motor, relay, etc.) to perform the process results, so power devices are essential to any electronic system. The application of the power device is spread throughout various industries, and with the update of the power device, a new type of power device represented by a MOSFET (Metal Oxide Semiconductor Field Effect Transistor ) has been dominant, except that the application field of the super power is still dominant by a thyristor. To overcome the problem of excessive miller capacitance of the Trench-MOSFET (Trench MOSFET), SGT MOSFETs (Shield Gate Trench MOSFET, shielded gate MOSFETs) were proposed around 2000.
As shown in fig. 4, which is a basic structure diagram of the SGT MOSFET, a second N-type epitaxial layer 104 is grown on a second N-type substrate 105, a source polysilicon 111 and a second control gate polysilicon 109 are formed after trench etching and filling, and a second P-type body region 103, a second heavily doped p+ region 101 and a second n+ source region 102 are formed by implantation annealing, and a second gate oxide layer 112, a third insulating dielectric layer 110 and a fourth insulating dielectric layer 108 between the second P-type body region 103 and the second control gate polysilicon 109 are oxide layers. The structure employs a double layer polysilicon structure, with the lower source polysilicon 111 connected to the device second source metal electrode 107 and the upper second control gate polysilicon 109 connected to the device gate. The source polysilicon 111 is between the second control gate polysilicon 109 and the second drain metal electrode 106, shielding the coupling between the gate and drain to a maximum extent, reducing the miller capacitance of the device.
However, at the same time, the output capacitance CDS of the power device is increased, and the switching speed is affected, so that the problem of the increase of the output capacitance of the structure is solved.
Disclosure of Invention
The invention aims to provide an SGT MOSFET device with low output capacitance and a manufacturing method thereof, which solve the problems in the prior art.
The invention is realized by the following technical scheme:
in a first aspect, the present invention provides a low output capacitance SGT MOSFET device comprising a first drain metal electrode, a first source metal electrode, and a gate structure; the first drain metal electrode is arranged on the bottom surface of the grid structure, and the first source metal electrode is arranged on the top surface of the grid structure;
the grid structure comprises a first heavily doped P+ region, a first N+ source region, a first P type body region, a first N type epitaxial layer, a first N type substrate, a first insulating medium layer, first control grid polysilicon, a second insulating medium layer, a first grid oxide layer and a polysilicon diode;
one surface of the first N-type substrate is arranged on the top surface of the first drain metal electrode, the first N-type epitaxial layer is arranged on the other surface of the first N-type substrate, a groove is formed in the first N-type epitaxial layer, the polycrystalline diode is arranged in the groove, two first P-type body regions are arranged on the first N-type epitaxial layer, the two first P-type body regions are positioned on two sides of the groove, first control gate polycrystalline silicon is arranged between the two first P-type body regions, a first heavily doped P+ region and a first N+ source region which are connected with each other are arranged on each first P-type body region, and one surface, far away from the first N-type epitaxial layer, of the first heavily doped P+ region and one surface, which is in contact with the first heavily doped P+ region, of the first N+ source region are connected with the first source metal electrode;
a first gate oxide layer is arranged between the first P-type body region and the first control gate polysilicon, a second insulating medium layer is arranged between the first control gate polysilicon and the polycrystalline diode, a second insulating medium layer is arranged between the polycrystalline diode and the inner wall of the groove of the first N-type epitaxial layer, and a first insulating medium layer is arranged between one surface, close to the first source metal electrode, of the first N+ source region and the first control gate polysilicon and the first source metal electrode.
In one possible implementation manner, the polycrystalline diode includes P-type polycrystalline silicon and N-type polycrystalline silicon, the P-type polycrystalline silicon and the N-type polycrystalline silicon are connected with each other, the P-type polycrystalline silicon and the N-type polycrystalline silicon are disposed in the trench of the first N-type epitaxial layer, the P-type polycrystalline silicon is disposed close to the first control gate polycrystalline silicon, and the N-type polycrystalline silicon is disposed far away from the first control gate polycrystalline silicon.
In one possible embodiment, the number of the first control gate polysilicon is set to 1 or 2;
when the number of the first control gate polysilicon is set to be 1, the first control gate polysilicon is arranged between the two first P-type body regions, the polycrystalline diode is arranged in the groove, and the polycrystalline diode is positioned below the first control gate polysilicon;
when the number of the first control gate polysilicon is set to 2, the two first control gate polysilicon are arranged between the two first P-type body regions according to the same height, the polycrystalline diode is arranged in the groove, and the top of the polycrystalline diode is positioned between the two first control gate polysilicon.
In a second aspect, the present invention provides a method for fabricating a low output capacitance SGT MOSFET device, comprising:
growing a first N-type epitaxial layer on a first N-type substrate, and etching a groove on the first N-type epitaxial layer through dry etching and wet etching;
forming an oxide layer on the inner wall of the groove of the first N-type epitaxial layer through a dry-wet dry oxidation process;
depositing N-type polycrystalline silicon with the thickness above a set value, etching to a position below the surface of silicon by a dry etching process, and reserving the N-type polycrystalline silicon with the thickness above the set value; the silicon surface is used for representing the top surface of the first N-type epitaxial layer;
depositing P-type polycrystalline silicon with set thickness, etching to below the surface of silicon by a dry etching process, and reserving the P-type polycrystalline silicon with set thickness;
etching the field oxide layer to a position below the top surface of the P-type polysilicon through a wet etching process;
adopting HDP to deposit an oxide layer on the top surface of the P-type polycrystalline silicon and in a gap between the P-type polycrystalline silicon and the first N-type epitaxial layer to form a second insulating medium layer;
forming gate oxide on the top surface of the first N-type epitaxial layer and the side wall of the groove of the non-precipitated oxide layer through a wet oxygen process to form a first gate oxide layer;
depositing N-type polycrystalline silicon with the thickness above a set value, etching to the lower part of the silicon surface through a dry etching process, and reserving first control gate polycrystalline silicon with the set thickness;
forming a first P-type body region on the top of two sides of the groove on the first N-type epitaxial layer through three times of boron injection;
implanting arsenic impurity into the first P-type body region, and forming a first N+ source region through annealing;
etching the lead hole to the lower part of the silicon surface, and injecting boron into the lead hole to form a hole injection region, doping boron into the hole injection region, and forming a first heavily doped P+ region;
etching a set pattern after depositing TEOS to form a first insulating medium layer;
depositing metal from the front surface and etching to form a first source metal electrode; the front surface is used for representing one surface of the first heavily doped P+ region, which is far away from the first P-type body region, and one surface of the first insulating medium layer, which is far away from the first control gate polysilicon;
forming a first drain metal electrode from the back surface by evaporation or sputtering; the back surface is used for representing one surface, far away from the first N-type epitaxial layer, of the first N-type substrate.
In one possible embodiment, the first P-type body region is annealed and a push junction is performed after the boron implantation is completed.
In one possible implementation manner, the depth of the groove is 5.5-6.5 μm, and the depth-to-width ratio is 5:1, a step of;
the temperature of the dry-wet dry oxidation process is 1000-1150 ℃, and the thickness of the oxide layer on the inner wall of the groove is 6000- Ǻ;
the set thickness of the N-type polycrystalline silicon is 2.0-3.0 mu m, the temperature of the corresponding dry etching process of the N-type polycrystalline silicon is 580 ℃, the N-type polycrystalline silicon is doped with phosphorus, and the concentration is 1e 16 ~2e 16 cm -3 ；
The set thickness of the P-type polysilicon is 2.0-3.0 mu m, the temperature of the corresponding dry etching process of the P-type polysilicon is 580 ℃, the P-type polysilicon is doped with boron, and the concentration is 1e 19 ~2e 19 cm -3 。
In one possible implementation, the field oxide layer is etched to a position 3000 Ǻ below the top surface of the P-type polysilicon by a wet etching process;
the thickness of an oxide layer deposited in a gap between the P-type polycrystalline silicon and the first N-type epitaxial layer is 6000 Ǻ;
the thickness of the gate oxide is 500 Ǻ, and the temperature of the wet oxygen process corresponding to the gate oxide is 1000-1100 ℃.
In one possible implementation manner, etching is performed to a position of 0.1 μm below the silicon surface through a dry etching process, and the set thickness of the first control gate polysilicon is 1.0-1.5 μm;
the temperature of the dry etching process corresponding to the first control gate polysilicon is 580 ℃, the first control gate polysilicon is doped with phosphorus, and the concentration is 1e 19 ~2e 19 cm -3 。
In one possible embodiment, the implanting conditions of the triple implant boron include:
the first implantation condition is energy of 120keV, boron doping, and dose of 1e 13 cm -2 ；
The second implantation condition is energy of 90keV, doped with boron, and dosage of 1e 12 cm -2 ；
The third implantation condition is energy of 40keV, doped with boron, and dosage of 4e 12 cm -2 ；
The annealing temperature of the first P-type body region is 1050 ℃, and the process time is 60min;
the implantation energy of the impurity arsenic corresponding to the first N+ source region is 30keV, and the implantation dosage is 1e 16 cm -2 。
In one possible embodiment, the wire holes are etched to a position of 0.4 μm below the silicon surface, and the wire holes have a width of 0.3 μm;
the energy corresponding to the boron doped in the first heavily doped P+ region is 20keV, and the dosage is 1e 14 cm -2 The method comprises the steps of carrying out a first treatment on the surface of the The first heavily doped P+ region is obtained by a rapid thermal annealing process, the time of the rapid thermal annealing process is 15s, and the temperature is 1000 ℃;
the thickness of the first source metal electrode is 4 μm, and the thickness of the first drain metal electrode is 2 μm.
According to the SGT MOSFET device with low output capacitance and the manufacturing method, the polycrystalline diode composed of the P-type polycrystalline silicon and the N-type polycrystalline silicon is arranged, the new variable capacitance Cdiode, namely the capacitance of the P-type polycrystalline silicon and the capacitance of the N-type polycrystalline silicon, is added, the size of the Cdiode is controlled through doping, the overall output capacitance of the device is reduced, and the switching speed is improved.
Drawings
In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the drawings that are needed in the examples will be briefly described below, it being understood that the following drawings only illustrate some examples of the present invention and therefore should not be considered as limiting the scope, and that other related drawings may be obtained from these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a low output capacitance SGT MOSFET device according to the present invention;
FIG. 2 is a schematic diagram of the capacitance of a low output capacitance SGT MOSFET device according to the present invention;
FIG. 3 is a simplified capacitance equivalent circuit diagram of a low output capacitance SGT MOSFET device according to the present invention;
FIG. 4 is a schematic diagram of a prior art structure provided by the present invention;
FIG. 5 is a schematic diagram of a prior art capacitor according to the present invention;
FIG. 6 is a simplified capacitive equivalent circuit diagram of the prior art provided by the present invention;
FIG. 7 is a schematic diagram of another structure of a low output capacitance SGT MOSFET device according to the present invention;
fig. 8 is a process flow diagram of a method for fabricating a SGT MOSFET device with low output capacitance according to the present invention.
In the drawings, the reference numerals and corresponding part names:
201-first heavily doped P+ region, 202-first N+ source region, 203-first P type body region, 204-first N type epitaxial layer, 205-first N type substrate, 206-first drain metal electrode, 207-first source metal electrode, 208-first insulating dielectric layer, 209-first control gate polysilicon, 210-second insulating dielectric layer, 211-P type polysilicon, 212-first gate oxide layer and 213-N type polysilicon;
101-second heavily doped P+ region, 102-second N+ source region, 103-second P type body region, 104-second N type epitaxial layer, 105-second N type substrate, 106-second drain metal electrode, 107-second source metal electrode, 108-fourth insulating dielectric layer, 109-second control gate polysilicon, 110-third insulating dielectric layer, 111-source polysilicon and 112-second gate oxide layer.
Description of the embodiments
For the purpose of making apparent the objects, technical solutions and advantages of the present invention, the present invention will be further described in detail with reference to the following examples and the accompanying drawings, wherein the exemplary embodiments of the present invention and the descriptions thereof are for illustrating the present invention only and are not to be construed as limiting the present invention.
Example 1
As shown in FIG. 1, the present invention provides a low output capacitance SGT MOSFET device including a first drain metal electrode 206, a first source metal electrode 207 and a gate structure. The first drain metal electrode 206 is disposed on the bottom surface of the gate structure, and the first source metal electrode 207 is disposed on the top surface of the gate structure.
The gate structure includes a first heavily doped p+ region 201, a first n+ source region 202, a first P-type body region 203, a first N-type epitaxial layer 204, a first N-type substrate 205, a first insulating dielectric layer 208, a first control gate polysilicon 209, a second insulating dielectric layer 210, a first gate oxide layer 212, and a polysilicon diode.
One surface of the first N-type substrate 205 is disposed on the top surface of the first drain metal electrode 206, the first N-type epitaxial layer 204 is disposed on the other surface of the first N-type substrate 205, a trench is formed in the first N-type epitaxial layer 204, the polycrystalline diode is disposed in the trench, two first P-type body regions 203 are disposed on the first N-type epitaxial layer 204, the two first P-type body regions 203 are disposed on two sides of the trench, a first control gate polysilicon 209 is disposed between the two first P-type body regions 203, a first heavily doped p+ region 201 and a first n+ source region 202 which are connected with each other are disposed on each first P-type body region 203, and one surface, far away from the first N-type epitaxial layer 204, of the first heavily doped p+ region 201 and one surface, which contacts the first heavily doped p+ region 201, of the first n+ source region 202 are connected with the first source metal electrode 207. The first P-type body region 203, the first heavily doped p+ region 201, and the first n+ source region 202 are connected to form a cohesive structure.
A first gate oxide layer 212 is disposed between the first P-type body region 203 and the first control gate polysilicon 209, a second insulating dielectric layer 210 is disposed between the first control gate polysilicon 209 and the polycrystalline diode, a second insulating dielectric layer 210 is disposed between the polycrystalline diode and the inner wall of the trench of the first N-type epitaxial layer 204, and a first insulating dielectric layer 208 is disposed between one surface of the first n+ source region 202 and the first control gate polysilicon 209, which is close to the first source metal electrode 207, and the first source metal electrode 207. The depth value of the first n+ source region 202 is greater than the depth value of the first heavily doped p+ region 201.
In this embodiment, the thickness of the first control gate polysilicon 209 is 1-1.5 μm. The thickness of the P-type polysilicon 211 and the N-type polysilicon 213 is 2-3 μm. The depth of the trench on the first N-type epitaxial layer 204 is 5.5-6.5 μm, and the aspect ratio is 5:1.
in comparison with fig. 1 and fig. 4, the first N-type substrate 205 is taken as a reference, and the first N-type epitaxial layer 204 is added on the first N-type substrate 205, and after the trench etching and filling, source polysilicon and first control gate polysilicon 209 should be formed, but for the purposes of reducing the output capacitance CDS of the device and improving the switching speed, the original single source polysilicon is replaced with a polysilicon diode composed of P-type polysilicon 211 and N-type polysilicon 213. The first P-type body region 203, the first heavily doped p+ region 201 and the first n+ source region 202 are formed on the surface of the chip by etching the lead-out port and interconnecting with the first source metal electrode 207, and then the first gate oxide layer 212 and the insulating medium layer between the first P-type body region 203 and the first control gate polysilicon 209 are oxide layers. The poly diode is connected to a first source metal electrode 207, a first control gate poly 209 is connected to the gate of the device, and P-type poly 211 and N-type poly 213 are disposed between the first control gate poly 209 and the first source metal electrode 207.
Comparing fig. 1 and fig. 4, it can be seen that the most intuitive difference point of the present invention is that the original single source polysilicon is replaced by a polysilicon diode, and the capacitance conditions of the corresponding devices are also different when the devices work.
As shown in fig. 5 and 6, the existing MOSFET base structure is generally an N-channel. A capacitance CGS1 corresponding between the second control gate polysilicon 109 and the second source metal electrode 107, and a capacitance CGS2 corresponding between the second control gate polysilicon 109 and the source polysilicon 111. A capacitance CGD corresponding to the second control gate polysilicon 109 and the second drain metal electrode 106, a capacitance CDS1 corresponding to the second source metal electrode 107 and the second drain metal electrode 106, and a capacitance CDS2 corresponding to the source polysilicon 111 and the second drain metal electrode 106. Capacitor CGS1 and capacitor CGS2 are connected in parallel to form a gate-source capacitance in the conventional sense, and capacitor CDS1 and capacitor CDS2 are connected in parallel to form a drain-source capacitance in the conventional sense. The feedback capacitance CRSS is the gate-drain capacitance CGD, and the capacitance between the drain and the gate is measured to be equal to the feedback capacitance with the source grounded. The input capacitance CISS is equal to the sum of the gate-drain capacitance CGD and the gate-source capacitance CGS, the drain and source are shorted at this time, the drain-source capacitance CDS is shorted, and the capacitance between the gate and the source is measured as the input capacitance by an ac signal. The output capacitance COSS is equal to the sum of the drain-source capacitance CDS and the gate-drain capacitance CGD, at which time the gate is shorted, and the capacitance between the drain and the source is measured as the output capacitance using an ac signal.
As shown in fig. 2 and 3, the source polysilicon 111 is replaced with a polysilicon diode on the existing MOSFET infrastructure, the polysilicon diode including P-type polysilicon 211 and N-type polysilicon 213. The other capacitance is unchanged, and the CDS corresponding to the original source polysilicon 111 and the first drain metal electrode 206 becomes three new capacitances: a capacitance CDP between the P-type polysilicon 211 and the first drain metal electrode 206, a capacitance CDN between the N-type polysilicon 213 and the drain metal electrode, and a capacitance Cdiode between the P-type polysilicon 211 and the N-type polysilicon 213. The capacitance Cdiode between the P-type polysilicon 211 and the N-type polysilicon 213 is connected in series with the capacitance CDN between the N-type polysilicon 213 and the drain metal electrode, so as to obtain an overall capacitance, and the final drain-source capacitance CDS is obtained by connecting the overall capacitance and the capacitance CDP between the P-type polysilicon 211 and the first drain metal electrode 206 in parallel. Depending on the characteristics of the parallel circuit, the output capacitance COSS is reduced as a whole by the reduction of the drain-source capacitance CDS, with other conditions unchanged. The capacitance CDP corresponding to the P-type polysilicon 211 and the first drain metal electrode 206 corresponds to the original CDS1, the capacitance CDN corresponding to the N-type polysilicon 213 and the drain metal electrode, and the capacitance Cdiode corresponding to the P-type polysilicon 211 and the N-type polysilicon 213 corresponds to the original capacitance CDS2, and the size of Cdiode corresponding to the polysilicon diode is controlled by doping, so that the improved capacitance CDS2 is smaller than the original value, and the overall output capacitance COSS of the device is reduced, thereby achieving the purposes of low output capacitance and high switching speed.
As shown in fig. 7, another embodiment of the present invention is provided, which is the biggest difference only in that the original integrated control gate polysilicon is divided into two pieces and symmetrically disposed at two sides of the polysilicon diode, i.e. the MOSFET base structure of the original upper-lower structure is changed into the MOSFET base structure of the left-right structure. The polycrystalline diode comprises P-type polycrystalline silicon 211 and N-type polycrystalline silicon 213, the P-type polycrystalline silicon 211 and the N-type polycrystalline silicon 213 are connected with each other, the P-type polycrystalline silicon 211 and the N-type polycrystalline silicon 213 are arranged in the groove of the first N-type epitaxial layer 204, the P-type polycrystalline silicon 211 is close to the first control gate polycrystalline silicon 209, and the N-type polycrystalline silicon 213 is far away from the first control gate polycrystalline silicon 209.
In one possible implementation, the number of the first control gate polysilicon 209 is set to 1 or 2.
When the number of the first control gate polysilicon 209 is set to 1, the first control gate polysilicon 209 is disposed between the two first P-type body regions 203, the polycrystalline diode is disposed in the trench, and the polycrystalline diode is located below the first control gate polysilicon 209.
When the number of the first control gate polysilicon 209 is set to 2, two first control gate polysilicon 209 are disposed between two first P-type body regions 203 at the same height, the polycrystalline diode is disposed in the trench, and the top of the polycrystalline diode is located between two first control gate polysilicon 209.
Example 2
As shown in FIG. 8, the invention provides a method for manufacturing an SGT MOSFET device with low output capacitance, which comprises the following steps:
step a, a first N-type epitaxial layer 204 is grown on a first N-type substrate 205, and a trench is etched on the first N-type epitaxial layer 204 by dry etching and wet etching.
More specifically, the first N-type epitaxial layer 204 is masked with a hard mask, and trenches with corresponding shapes are etched by dry etching and wet etching. The depth of the groove is 5.5-6.5 mu m, and the depth-to-width ratio is 5:1.
and b, forming an oxide layer with the thickness of 6000 and Ǻ on the inner wall of the groove of the first N-type epitaxial layer 204 through a dry-wet dry oxidation process. It should be noted that the thickness of 6000, 6000 Ǻ in the present embodiment is only a preferable value, and the thickness may be changed. For example, a thickness range is set, and the thickness of the oxide layer is ensured to be within the thickness range.
Optionally, the temperature of the dry-wet dry oxidation process is 1000-1150 ℃.
And c, depositing N-type polycrystalline silicon 213 with the thickness above a set value, etching to the position below the silicon surface through a dry etching process, and retaining the N-type polycrystalline silicon 213 with the set thickness. Wherein the silicon surface is used to characterize the top surface of the first N-type epitaxial layer 204, i.e., the side remote from the first N-type substrate 205.
Optionally, the set thickness of the N-type polysilicon 213 is 2.0-3.0 μm, the temperature of the corresponding dry etching process of the N-type polysilicon 213 is 580 ℃, the N-type polysilicon 213 is doped with phosphorus, and the concentration is 1e 16 ~2e 16 cm -3 。
And d, depositing the P-type polycrystalline silicon 211 with the set thickness, etching to the position below the silicon surface through a dry etching process, and retaining the P-type polycrystalline silicon 211 with the set thickness.
Optionally, the set thickness of the P-type polysilicon 211 is 2.0-3.0 μm, the temperature of the corresponding dry etching process of the P-type polysilicon 211 is 580 ℃, boron is doped, and the concentration is 1e 19 ~2e 19 cm -3 。
And e, etching the field oxide layer to a position 3000 Ǻ below the top surface of the P-type polysilicon 211 through a wet etching process.
Step f, depositing 6000 Ǻ thick oxide layer on the top surface of the P-type polysilicon 211 and in the gap between the P-type polysilicon 211 and the first N-type epitaxial layer 204 by using HDP (High Density Plasma ) to make the second insulating dielectric layer 210 have good trench filling capability.
It should be noted that the thickness of 6000, 6000 Ǻ in the present embodiment is only a preferable value, and the thickness may be changed. For example, a thickness range is set, and the thickness of the oxide layer is ensured to be within the thickness range.
In step g, a gate oxide is formed on the top surface of the first N-type epitaxial layer 204 and the sidewall of the trench where the oxide is not deposited by a wet oxygen process, thereby forming a first gate oxide 212.
Optionally, the thickness of the gate oxide is 500 Ǻ, and the temperature of the wet oxygen process corresponding to the gate oxide is 1000-1100 ℃. It is noted that the thickness of the gate oxide may also vary.
And step h, depositing N-type polycrystalline silicon with the thickness above a set value, etching to the lower part of the silicon surface through a dry etching process, and retaining the first control gate polycrystalline silicon 209 with the set thickness.
Optionally, the first control gate polysilicon 209 is etched to a position of 0.1 μm below the silicon surface by a dry etching process, and the set thickness of the first control gate polysilicon 209 is 1.0-1.5 μm.
The temperature of the dry etching process corresponding to the first control gate polysilicon 209 is 580 ℃, the doping is phosphorus, and the concentration is 1e 19 ~2e 19 cm -3 。
In step i, boron is implanted three times to form a first P-type body region 203 on the first N-type epitaxial layer 204 on top of both sides of the trench.
In one possible embodiment, after the boron implantation is completed, the first P-type body region 203 is annealed to push the junction.
Optionally, the three-time boron implantation conditions include:
the first implantation condition is energy 120keV, doped with boron, dose 1e 13 cm -2 。
The second implantation condition is energy of 90keV, doped with boron, and dosage of 1e 12 cm -2 。
The third implantation condition is energy of 40keV, doped with boron, and dosage of 4e 12 cm -2 。
The annealing temperature of the first P-type body region 203 is 1050 ℃, and the process time is 60min.
Step j, implanting arsenic impurity into the first P-type body region 203, and forming a first n+ source region 202 by annealing.
Optionally, the implantation energy of the impurity arsenic corresponding to the first n+ source region 202 is 30keV, and the implantation dose is 1e 16 cm -2 。
Step k, etching the lead hole to 0.4 μm below the surface of the silicon, and implanting boron into the lead hole to form a hole implantation region, doping the hole implantation region with boron, thereby forming a first heavily doped P+ region 201.
Optionally, the energy corresponding to the boron doped in the first heavily doped p+ region 201 is 20keV, and the dose is 1e 14 cm -2 . The first heavily doped p+ region 201 is obtained by a rapid thermal annealing process, and the time of the rapid thermal annealing process is 15s, and the temperature is 1000 ℃.
Step l, after depositing TEOS (Tetraethyl orthosilicate, tetraethoxysilane), etching the set pattern to form the first insulating dielectric layer 208.
Step m, depositing metal from the front side and etching to form the first source metal electrode 207. The front surface is used to characterize a surface of the first heavily doped p+ region 201 away from the first P-type body region 203 and a surface of the first insulating dielectric layer 208 away from the first control gate polysilicon 209.
Step n, the first drain metal electrode 206 is formed by evaporation or sputtering from the back surface. Wherein the back surface is used to characterize a side of the first N-type substrate 205 remote from the first N-type epitaxial layer 204.
Alternatively, the thickness of the first source metal electrode 207 is 4 μm, and the thickness of the first drain metal electrode 206 is 2 μm.
It should be noted that: the HDP process in the step f can be replaced by other process methods, and the thickness of the deposited oxide layer is ensured to be the same. Step j and step i are not separated in sequence, that is, the manufacturing sequence of the source region and the body region is not strictly required. The insulating medium layer in all steps is not limited to silicon dioxide materials, and materials with corresponding effects can be replaced.
The dry etching process, wet etching process, dry wet oxidation process, wet etching process, HDP process, wet oxygen process, annealing process and the like involved in the steps are all prior art means, and are not described in detail.
Similarly, in one embodiment of the present invention, the source polysilicon 111 is replaced by a polysilicon diode, and it is extended that the source polysilicon 111 is replaced by a polysilicon transistor or even other multipole transistors, so that the size of the output capacitor can be effectively reduced.
The foregoing description of the embodiments has been provided for the purpose of illustrating the general principles of the invention, and is not meant to limit the scope of the invention, but to limit the invention to the particular embodiments, and any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the invention are intended to be included within the scope of the invention.

Claims (10)

1. A low output capacitance SGT MOSFET device comprising a first drain metal electrode (206), a first source metal electrode (207), and a gate structure; the first drain metal electrode (206) is arranged on the bottom surface of the grid structure, and the first source metal electrode (207) is arranged on the top surface of the grid structure;
the grid structure comprises a first heavily doped P+ region (201), a first N+ source region (202), a first P type body region (203), a first N type epitaxial layer (204), a first N type substrate (205), a first insulating medium layer (208), a first control grid polysilicon (209), a second insulating medium layer (210), a first grid oxide layer (212) and a polycrystalline diode;
one surface of the first N-type substrate (205) is arranged on the top surface of the first drain metal electrode (206), the first N-type epitaxial layer (204) is arranged on the other surface of the first N-type substrate (205), a groove is formed in the first N-type epitaxial layer (204), the polycrystalline diode is arranged in the groove, two first P-type body regions (203) are arranged on the first N-type epitaxial layer (204), the two first P-type body regions (203) are positioned on two sides of the groove, first control gate polycrystalline silicon (209) is arranged between the two first P-type body regions (203), a first heavily doped P+ region (201) and a first N+ source region (202) which are connected with each other are arranged on each first P-type body region (203), and one surface of the first heavily doped P+ region (201) far away from the first N-type epitaxial layer (204) and one surface of the first N+ source region (202) which is contacted with the first heavily doped P+ region (201) are connected with the first metal electrode (207);
a first gate oxide layer (212) is arranged between the first P-type body region (203) and the first control gate polysilicon (209), a second insulating dielectric layer (210) is arranged between the first control gate polysilicon (209) and the polycrystalline diode, a second insulating dielectric layer (210) is arranged between the polycrystalline diode and the inner wall of the groove of the first N-type epitaxial layer (204), and a first insulating dielectric layer (208) is arranged between one surface, close to the first source metal electrode (207), of the first N+ source region (202) and the first control gate polysilicon (209).
2. The low output capacitance SGT MOSFET device of claim 1, wherein the poly diode comprises a P-type poly (211) and an N-type poly (213), the P-type poly (211) and the N-type poly (213) are connected to each other, the P-type poly (211) and the N-type poly (213) are disposed in a trench of the first N-type epitaxial layer (204), and the P-type poly (211) is disposed proximate to the first control gate poly (209), and the N-type poly (213) is disposed distal to the first control gate poly (209).
3. The low output capacitance SGT MOSFET device of claim 1, wherein the number of first control gate polysilicon (209) is set to 1 or 2;
when the number of the first control gate polysilicon (209) is set to be 1, the first control gate polysilicon (209) is arranged between the two first P-type body regions (203), the polycrystalline diode is arranged in the groove, and the polycrystalline diode is positioned below the first control gate polysilicon (209);
when the number of the first control gate polysilicon (209) is set to 2, the two first control gate polysilicon (209) are arranged between the two first P-type body regions (203) at the same height, the polycrystalline diode is arranged in the groove, and the top of the polycrystalline diode is positioned between the two first control gate polysilicon (209).
4. A method of fabricating a SGT MOSFET device based on the low output capacitance of any one of claims 1-3, comprising:
growing a first N-type epitaxial layer (204) on a first N-type substrate (205), and etching a groove on the first N-type epitaxial layer (204) through dry etching and wet etching;
forming an oxide layer on the inner wall of the groove of the first N-type epitaxial layer (204) through a dry-wet-dry oxidation process;
depositing N-type polycrystalline silicon (213) with the thickness above a set value, etching to the position below the silicon surface through a dry etching process, and reserving the N-type polycrystalline silicon (213) with the thickness above the set value; wherein the silicon surface is used to characterize the top surface of the first N-type epitaxial layer (204);
depositing P-type polycrystalline silicon (211) with set thickness, etching to the position below the surface of silicon by a dry etching process, and reserving the P-type polycrystalline silicon (211) with set thickness;
etching the field oxide layer to a position below the top surface of the P-type polysilicon (211) through a wet etching process;
depositing an oxide layer in the top surface of the P-type polycrystalline silicon (211) and a gap between the P-type polycrystalline silicon (211) and the first N-type epitaxial layer (204) by adopting HDP to form a second insulating medium layer (210);
forming gate oxide on the top surface of the first N-type epitaxial layer (204) and the side wall of the groove without the precipitated oxide layer by a wet oxygen process to form a first gate oxide layer (212);
depositing N-type polycrystalline silicon with the thickness being more than a set thickness, etching to the lower part of the silicon surface through a dry etching process, and reserving first control gate polycrystalline silicon with the set thickness (209);
forming a first P-type body region (203) on the top of the two sides of the groove on the first N-type epitaxial layer (204) through three boron implantation;
implanting arsenic impurity in the first P-type body region (203), and forming a first n+ source region (202) by annealing;
etching the lead hole to the lower part of the silicon surface, and injecting boron into the lead hole to form a hole injection region, doping the hole injection region with boron, so as to form a first heavily doped P+ region (201);
etching a set pattern after depositing TEOS to form a first insulating dielectric layer (208);
depositing metal from the front side and etching to form a first source metal electrode (207); the front surface is used for representing one surface of the first heavily doped P+ region (201) far from the first P-type body region (203) and one surface of the first insulating medium layer (208) far from the first control gate polysilicon (209);
forming a first drain metal electrode (206) by evaporation or sputtering from the back surface; wherein the back surface is used to characterize a side of the first N-type substrate (205) remote from the first N-type epitaxial layer (204).
5. The method of claim 4, wherein the first P-type body region (203) is annealed and a push-junction is performed after the boron implantation is completed.
6. The method of claim 4, wherein the trench has a depth of 5.5-6.5 μm and an aspect ratio of 5:1, a step of;
the temperature of the dry-wet dry oxidation process is 1000-1150 ℃, and the thickness of the oxide layer on the inner wall of the groove is 6000- Ǻ;
the set thickness of the N-type polycrystalline silicon (213) is 2.0-3.0 mu m, the temperature of the corresponding dry etching process of the N-type polycrystalline silicon (213) is 580 ℃, the N-type polycrystalline silicon is doped with phosphorus, and the concentration is 1e 16 ~2e 16 cm -3 ；
The set thickness of the P-type polycrystalline silicon (211) is 2.0-3.0 mu m, the temperature of the corresponding dry etching process of the P-type polycrystalline silicon (211) is 580 ℃, the P-type polycrystalline silicon is doped with boron, and the concentration is 1e 19 ~2e 19 cm -3 。
7. The method of claim 4, wherein the field oxide is etched to a position below 3000 a top surface Ǻ of the P-type polysilicon (211) by a wet etching process;
the thickness of the oxide layer deposited on the top surface of the P-type polycrystalline silicon (211) and in the gap between the P-type polycrystalline silicon (211) and the first N-type epitaxial layer (204) is 6000 Ǻ;
the thickness of the gate oxide is 500 Ǻ, and the temperature of the wet oxygen process corresponding to the gate oxide is 1000-1100 ℃.
8. The method according to claim 4, wherein the first control gate polysilicon (209) is etched to a position of 0.1 μm below the silicon surface by a dry etching process, and has a set thickness of 1.0 to 1.5 μm;
the temperature of the dry etching process corresponding to the first control gate polysilicon (209) is 580 ℃, the doping is phosphorus, and the concentration is 1e 19 ~2e 19 cm -3 。
9. The method of claim 5, wherein the three boron implants comprise:
the first implantation condition is energy of 120keV, boron doping, and dose of 1e 13 cm -2 ；
The second implantation condition is energy of 90keV, doped with boron, and dosage of 1e 12 cm -2 ；
The third implantation condition is energy of 40keV, doped with boron, and dosage of 4e 12 cm -2 ；
The annealing temperature of the first P-type body region (203) is 1050 ℃, and the process time is 60min;
the implantation energy of the impurity arsenic corresponding to the first N+ source region (202) is 30keV, and the implantation dosage is 1e 16 cm -2 。
10. The method of claim 4, wherein the wire holes are etched to a position of 0.4 μm below the silicon surface and the wire holes have a width of 0.3 μm;
the energy corresponding to the boron doped in the first heavily doped P+ region (201) is 20keV, and the dosage is 1e 14 cm -2 The method comprises the steps of carrying out a first treatment on the surface of the The first heavily doped P+ region (201) is obtained by a rapid thermal annealing process, the time of the rapid thermal annealing process is 15s, and the temperature is 1000 ℃;
the thickness of the first source metal electrode (207) is 4 μm, and the thickness of the first drain metal electrode (206) is 2 μm.
CN202310596206.4A 2023-05-25 2023-05-25 SGT MOSFET device with low output capacitance and manufacturing method Pending CN116344622A (en)

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