CN116344345A - Ferroelectric field effect transistor, preparation method thereof and ferroelectric memory - Google Patents

Ferroelectric field effect transistor, preparation method thereof and ferroelectric memory Download PDF

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CN116344345A
CN116344345A CN202310219281.9A CN202310219281A CN116344345A CN 116344345 A CN116344345 A CN 116344345A CN 202310219281 A CN202310219281 A CN 202310219281A CN 116344345 A CN116344345 A CN 116344345A
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ferroelectric
layer
effect transistor
field effect
region
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林高波
玉虓
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Zhejiang Lab
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Zhejiang Lab
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Abstract

The invention relates to a ferroelectric field effect transistor, a preparation method thereof and a ferroelectric memory. The preparation method of the ferroelectric field effect transistor comprises the following steps: forming an oxide semiconductor layer on a substrate, wherein the oxide semiconductor layer comprises a channel region, and a source region and a drain region which are positioned at two sides of the channel region; forming a ferroelectric material layer on the channel region, and forming a top gate on the ferroelectric material layer; forming a metal reaction layer to cover the source region, the drain region and the top gate; annealing at 300-600 ℃ in an oxidizing atmosphere to induce the ferroelectric material layer to form a ferroelectric phase to obtain a ferroelectric medium layer, and enabling oxygen elements of the source region and the drain region to be extracted by the metal reaction layer to obtain a conductive source region and a conductive drain region; and the metal reaction layer is spontaneously oxidized to obtain a passivation layer; source and drain electrodes are formed in the passivation layer. The method realizes the functions of inducing the ferroelectric material layer to form ferroelectric phase, promoting the conductor of the source/drain region and depositing the passivation layer by one-time annealing, and the device with high performance and high durability is manufactured.

Description

Ferroelectric field effect transistor, preparation method thereof and ferroelectric memory
Technical Field
The invention relates to the technical field of memories, in particular to a ferroelectric field effect transistor, a preparation method thereof and a ferroelectric memory.
Background
The ferroelectric field effect transistor (Ferroelectric Field-Effect Transistor, feFET) is a single transistor memory using ferroelectric film as gate dielectric layer, and its working principle is to utilize different residual polarization states of ferroelectric film under applied voltage to regulate semiconductor surface state so as to change conduction state between source and drain to distinguish two logic states of "0" and "1" and implement information storage function in nonvolatile mode.
FeFET has the advantages of simple structure, low power consumption, non-destructive readout, easy compatibility with complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) process, realization of integrated circuit process and the like, and has very wide application prospect in the next generation of high density memory technology. In the past few years, fefets based on oxide semiconductor channel layers have made tremendous progress, but there are still problems of low device performance and poor endurance, limiting commercial applications of fefets.
Disclosure of Invention
Based on this, there is a need to provide a ferroelectric field effect transistor having high device performance and good durability, a method of manufacturing the same, and a ferroelectric memory.
The above object of the present invention is achieved by the following technical solutions:
in a first aspect of the present invention, a method for manufacturing a ferroelectric field effect transistor is provided, comprising the steps of:
forming an oxide semiconductor layer on a substrate, wherein the oxide semiconductor layer comprises a channel region, and a source region and a drain region which are positioned at two sides of the channel region;
forming a ferroelectric material layer on the channel region, and forming a top gate on the ferroelectric material layer;
forming a metal reaction layer to cover the source region, the drain region and the top gate;
annealing at 300-600 ℃ in an oxidizing atmosphere to induce the ferroelectric material layer to form a ferroelectric phase to obtain a ferroelectric medium layer, and enabling oxygen elements of the source region and the drain region to be extracted by the metal reaction layer to obtain a conductive source region and a conductive drain region, and enabling the metal reaction layer to be spontaneously oxidized to obtain a passivation layer;
and forming a source electrode and a drain electrode in the passivation layer.
In one embodiment, the oxidizing atmosphere comprises one or more of oxygen, air, and ozone.
In one embodiment, the oxidizing atmosphere satisfies one or more of the following conditions:
1) The volume fraction of the oxygen is more than or equal to 10%;
2) The volume fraction of the ozone is more than or equal to 0.02%;
3) The pressure of the oxidizing atmosphere is 0.1atm to 1atm.
In one embodiment, the annealing satisfies one or more of the following conditions:
1) The annealing time is 20 s-600 s;
2) The heating rate is 10 ℃/s to 30 ℃/s;
3) The cooling rate is 1 ℃/s to 10 ℃/s.
In one embodiment, the oxide semiconductor layer satisfies one or more of the following conditions:
1) The oxide semiconductor layer is an indium-based oxide semiconductor layer;
2) The thickness of the oxide semiconductor layer is 5 nm-50 nm.
In one embodiment, the metal reaction layer satisfies one or more of the following conditions:
1) The metal reaction layer is a titanium reaction layer and/or an aluminum reaction layer;
2) The thickness of the metal reaction layer is 2 nm-10 nm.
In one embodiment, the ferroelectric material layer satisfies one or more of the following conditions:
1) The ferroelectric material comprises one or more of doped hafnium oxide, strontium bismuth tantalate, lead zirconate titanate, barium titanate, bismuth ferrite, cadmium pyroniobate and zinc metastannite;
2) The thickness of the ferroelectric material layer is 3 nm-50 nm.
In one embodiment, the ferroelectric field effect transistor satisfies one or more of the following conditions:
1) Materials of the top gate, the source and the drain include one or more of tungsten, titanium, copper, aluminum, platinum, nickel, molybdenum, titanium nitride, tungsten nitride, tantalum nitride, titanium aluminum nitride, titanium carbide, tungsten disilicide, indium tin oxide, and molybdenum titanium alloy;
2) The thicknesses of the top grid electrode, the source electrode and the drain electrode are 20 nm-100 nm.
In a second aspect of the present invention, a ferroelectric field effect transistor is provided, which is manufactured by the above-mentioned manufacturing method of a ferroelectric field effect transistor.
In a third aspect of the present invention, there is provided a ferroelectric memory comprising a ferroelectric field effect transistor as described above.
The ferroelectric field effect transistor prepared by the invention adopts a top grid self-aligned structure, the top grid is positioned above the channel region of the oxide semiconductor layer, the channel region can be effectively protected as a mask, the channel region is prevented from being damaged by etching in different process procedures, and no overlap exists between the top grid and the source electrode as well as between the top grid and the drain electrode, thereby avoiding the generation of parasitic capacitance and the interference to the performance of the device, and further improving the reliability and the durability of the device. Further, annealing is carried out at 300-600 ℃ in an oxidizing atmosphere, so that the ferroelectric material layer can be promoted to undergo phase inversion under the action of high temperature and the mechanical clamping action of the top grid electrode and the oxide semiconductor layer, and the formation of ferroelectricity is promoted, thereby obtaining the ferroelectric medium layer with ferroelectric property. Meanwhile, oxygen elements in the source region and the drain region can be abstracted by the metal reaction layer to form oxygen vacancies in the source region and the drain region, so that carrier concentration of the source region and the drain region is improved, and a conductive source region and a conductive drain region are obtained, ohmic contacts are formed between the source region and the conductive source region and between the drain region and the conductive drain region, and the ferroelectric field effect transistor has higher carrier mobility and lower operating voltage. And the metal reaction layer can be spontaneously oxidized to form a metal oxide film, so that a passivation layer with good water and oxygen blocking effect is obtained, and the reliability and the durability of the device are improved. Therefore, the ferroelectric field effect transistor with high device performance and good durability can be prepared by simultaneously realizing three functions of inducing the ferroelectric material layer to form a ferroelectric phase, promoting the source region and the drain region to generate conductor and depositing the passivation layer through one-time annealing, and has the advantages of simple process, easiness in realization and lower cost.
Drawings
FIG. 1 is a flow chart of a method for manufacturing a ferroelectric field effect transistor according to an embodiment;
FIG. 2 is a schematic diagram of a device after step S2 is completed in an embodiment;
FIG. 3 is a schematic diagram of a device after step S3 is completed in an embodiment;
FIG. 4 is a schematic diagram of a device after step S4 is completed in an embodiment;
FIG. 5 is a schematic diagram of a device after step S5 is completed in an embodiment;
FIG. 6 is a schematic diagram of a device after step S6 is completed in an embodiment;
fig. 7 is a schematic diagram illustrating an operation principle of a ferroelectric field effect transistor according to an embodiment.
Reference numerals: the semiconductor device comprises a substrate 10, a buffer layer 20, an oxide semiconductor layer 30, a channel region 31, a source region 32, a drain region 33, a conductive source region 34, a conductive drain region 35, a ferroelectric material layer 41, a ferroelectric dielectric layer 42, a top gate 51, a metal reaction layer 61, a passivation layer 62, a source 71 and a drain 72.
Detailed Description
In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to the appended drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The present invention may be embodied in many other forms than described herein and similarly modified by those skilled in the art without departing from the spirit of the invention, whereby the invention is not limited to the specific embodiments disclosed below.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
Oxide semiconductors are a class of oxides formed from metal and oxygen that have semiconductor properties. For the FeFET based on the oxide semiconductor layer, the gate voltage induced current value, the field effect mobility and the switching characteristics are all affected by the source/drain contact characteristics. Therefore, selecting an appropriate source/drain contact material, or obtaining a good bonding state between the oxide semiconductor layer and the source/drain is very important for obtaining a high-performance FeFET device. At present, a Schottky barrier exists between an oxide semiconductor layer and a source/drain electrode of the FeFET device, so that the contact resistance is high, and the performance of the FeFET device is reduced.
In a conventional thin film transistor (Thin Film Transistor, TFT) device, in order to improve the bonding state between the source/drain electrodes and the oxide semiconductor layer, a hydrogen element doping method, an ion implantation method, an aluminum reaction method, a plasma method, and other conductive processes may be generally used to improve the conductivity of the oxide semiconductor layer. However, when the hydrogen element doping method or the ion implantation method is used, doping elements such As H, B, P and As are easily diffused in the oxide semiconductor layer, and thus the region which should not be conductive is also conductive to different degrees, and the uniformity of the width of the channel region is reduced, thereby causing instability in the device performance. The aluminum reaction method does not cause diffusion of the conductive region, but when applied to a FeFET device, it is subjected to two anneals, one of which is annealing for causing reaction between the aluminum film and the oxide semiconductor layer, and one of which is rapid annealing for inducing the ferroelectric material layer to form a ferroelectric phase, and the conditions of the two anneals are greatly different, and the oxide semiconductor layer and the ferroelectric material layer are affected to different extents, resulting in degradation of device performance. For the plasma method, after the conductive process, not only a rapid annealing is needed to induce the formation of a ferroelectric phase, but also a passivation layer isolating water and oxygen must be deposited, for example, a silicon nitride passivation layer or a silicon oxynitride passivation layer is formed by adopting a plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) method, but the diffusion of hydrogen element in an oxide semiconductor layer is also induced in the growth process of the passivation layers, which not only affects the electrical characteristics of the device, but also increases the process complexity and the production cost of the whole device.
Based on this, the first aspect of the present invention provides a method for manufacturing a ferroelectric field effect transistor, comprising the steps of:
forming an oxide semiconductor layer on a substrate, wherein the oxide semiconductor layer comprises a channel region, and a source region and a drain region which are positioned at two sides of the channel region;
forming a ferroelectric material layer on the channel region, and forming a top gate on the ferroelectric material layer;
forming a metal reaction layer to cover the source region, the drain region and the top gate;
in an oxidizing atmosphere, rapidly annealing at 300-600 ℃ to induce the ferroelectric material layer to form a ferroelectric phase to obtain a ferroelectric medium layer, and enabling oxygen elements of the source region and the drain region to be extracted by the metal reaction layer to obtain a conductive source region and a conductive drain region, and enabling the metal reaction layer to be spontaneously oxidized to obtain a passivation layer;
and forming a source electrode and a drain electrode in the passivation layer.
It will be appreciated that the ferroelectric material layer is not ferroelectric and the ferroelectric dielectric layer is ferroelectric.
The ferroelectric field effect transistor prepared by the invention adopts a top grid self-aligned structure, the top grid is positioned above the channel region of the oxide semiconductor layer, the channel region can be effectively protected as a mask, the channel region is prevented from being damaged by etching in different process procedures, and no overlap exists between the top grid and the source electrode as well as between the top grid and the drain electrode, thereby avoiding the generation of parasitic capacitance and the interference to the performance of the device, and further improving the reliability and the durability of the device. Further, annealing is carried out at 300-600 ℃ in an oxidizing atmosphere, so that the ferroelectric material layer can be promoted to undergo phase inversion under the action of high temperature and the mechanical clamping action of the top grid electrode and the oxide semiconductor layer, and the formation of ferroelectricity is promoted, thereby obtaining the ferroelectric medium layer with ferroelectric property. Meanwhile, oxygen elements in the source region and the drain region can be abstracted by the metal reaction layer to form oxygen vacancies in the source region and the drain region, so that carrier concentration of the source region and the drain region is improved, and a conductive source region and a conductive drain region are obtained, ohmic contacts are formed between the source region and the conductive source region and between the drain region and the conductive drain region, and the ferroelectric field effect transistor has higher carrier mobility and lower operating voltage. And the metal reaction layer can be spontaneously oxidized to form a metal oxide film, so that a passivation layer with good water and oxygen blocking effect is obtained, and the reliability and the durability of the device are improved. Therefore, the ferroelectric field effect transistor with high device performance and good durability can be prepared by simultaneously realizing three functions of inducing the ferroelectric material layer to form a ferroelectric phase, promoting the source region and the drain region to generate conductor and depositing the passivation layer through one-time annealing, and has the advantages of simple process, easiness in realization and lower cost.
Referring to fig. 1, a flowchart of a method for manufacturing a ferroelectric field effect transistor according to an embodiment includes the following steps:
s1: a substrate is provided.
In some embodiments, the base includes a substrate and a buffer layer on the substrate.
A buffer layer is formed between the substrate and the oxide semiconductor layer, so that lattice mismatch between the substrate and the oxide semiconductor layer can be prevented, and the growth quality of the oxide semiconductor film can be improved.
In some embodiments, the substrate meets one or more of the following conditions:
1) The substrate is one or more of a silicon substrate, a glass substrate, a metal substrate and a polymer substrate;
2) The buffer layer is a silicon dioxide buffer layer and/or an alumina buffer layer;
3) The thickness of the buffer layer is 1 nm-300 nm.
It is understood that the silicon substrate may be an undoped silicon substrate, a p-type doped silicon substrate, or an n-type doped silicon substrate; the glass substrate may be a quartz glass substrate, a borosilicate glass substrate, a soda glass substrate, a potassium glass substrate, a lead glass substrate, or an aluminum magnesium glass substrate; the metal substrate may be a copper foil substrate or an aluminum foil substrate; the polymer substrate may be a Polyimide (PI) substrate, a polyethylene terephthalate (Polyethylene Terephthalate, PET) substrate, a Polycarbonate (PC) substrate, or a polymethyl methacrylate (Polymethyl Methacrylate, PMMA) substrate.
In some more preferred embodiments, the substrate is an n-doped silicon substrate.
In some embodiments, the method of forming the buffer layer includes the steps of: a silicon dioxide buffer layer with the thickness of 1 nm-300 nm is formed on a substrate by a thermal growth oxidation method or a PECVD method.
In some embodiments, the method of forming the buffer layer includes the steps of: and (3) depositing an alumina film on the substrate by an atomic layer deposition (Atomic Layer Deposition, ALD) method, and then introducing ozone to oxidize for 20min to obtain the alumina buffer layer with the thickness of 1-5 nm.
S2: an oxide semiconductor layer is formed on the substrate, the oxide semiconductor layer including a channel region and source and drain regions located on both sides of the channel region.
Referring to fig. 2, a schematic structure of the device after step S2 is completed in an embodiment is shown, from bottom to top, including a substrate 10, a buffer layer 20 and an oxide semiconductor layer 30, wherein the oxide semiconductor layer 30 is defined as a channel region 31 and source and drain regions 32 and 33 located at two sides of the channel region 31.
In some embodiments, the oxide semiconductor layer 30 satisfies one or more of the following conditions:
1) The oxide semiconductor layer 30 is an indium-based oxide semiconductor layer;
2) The thickness of the oxide semiconductor layer 30 is 5nm to 50nm.
The indium-based oxide has the advantages of good electrical property, high light transmittance, good large-area uniformity and the like, and no interface layer with low dielectric constant is formed between the indium-based oxide material and the ferroelectric layer, so that the indium-based oxide has few interface charge trapping, the performance of the ferroelectric field effect transistor can be obviously improved, the power consumption is reduced, and the process complexity is reduced.
In some more preferred embodiments, the indium-based oxide includes one or more of Indium Tin Oxide (ITO), indium Zinc Oxide (IZO), indium Gallium Zinc Oxide (IGZO), indium Gallium Tin Oxide (IGTO), indium Zinc Tin Oxide (IZTO), indium Gallium Zinc Tin Oxide (IGZTO).
It is to be understood that the oxide semiconductor layer 30 may be a single-layer film made of one of ITO, IZO, IGZO, IGTO, IZTO and IGZTO indium-based oxide materials, or may be a composite film obtained by laminating a plurality of single-layer films.
In some specific embodiments, the method of forming the oxide semiconductor layer 30 includes the steps of: arranging an IGZO target and a substrate in a reaction cavity of a magnetron sputtering instrument, and vacuumizing; after oxygen and argon are introduced into the reaction cavity, magnetron sputtering is carried out at room temperature, and an IGZO semiconductor layer with the thickness of 5-50 nm is deposited on the substrate; an oxide semiconductor layer pattern of a single device is defined using a photolithography process. Wherein, the molar ratio of indium, gallium and zinc of the IGZO target is 1:1:1; the flow ratio of oxygen to argon is 1 (1-9).
S3: a ferroelectric material layer is formed on the channel region, and a top gate is formed on the ferroelectric material layer.
Referring to fig. 3, a schematic structure of the device after step S3 is completed in an embodiment is shown, and a ferroelectric material layer 41 is located between the channel region 31 and the top gate 51.
In some embodiments, ferroelectric material layer 41 satisfies one or more of the following conditions:
1) The ferroelectric material comprises doped hafnium oxide, strontium Bismuth Tantalate (SBT), lead zirconate titanate (PZT),Barium titanate (BaTiO) 3 ) Bismuth ferrite (BiFeO) 3 ) Cadmium pyroniobate (Cd) 2 Nb 2 O 7 ) And zinc metastanniate (ZnSnO) 3 ) One or more of (a) and (b);
2) The thickness of the ferroelectric material layer 41 is 3nm to 50nm.
It is understood that doped hafnium oxide is a hafnium oxide based material containing a doping element; wherein the doping element includes one or more of carbon (C), nitrogen (N), silicon (Si), magnesium (Mg), aluminum (Al), zirconium (Zr), yttrium (Y), germanium (Ge), tin (Sn), strontium (Sr), lead (Pb), calcium (Ca), barium (Ba), titanium (Ti), gadolinium (Gd), and lanthanum (La).
In some more preferred embodiments, ferroelectric material layer 41 is a doped hafnium oxide layer.
The doped hafnium oxide can still keep good ferroelectric property under the condition of very thin thickness (about 10 nm), and the good compatibility of the hafnium oxide and the CMOS process is continued, so that the miniaturization of the device is realized.
In some more preferred embodiments, the ferroelectric material layer 41 is hafnium zirconium oxide (HfZrO x ) A material layer.
In some embodiments, the HfZrO x The forming method of the material layer comprises the following steps: with hafnium tetrachloride (HfCl) 4 ) Or tetra (methyl ethyl amino) hafnium (TEMAHf) as a precursor hafnium source, tetra (methyl ethyl amino) zirconium (TEMAZr) or tetra (dimethylamino) zirconium (TDMAZr) as a precursor zirconium source, water or ozone as a precursor oxygen source, nitrogen as a purge gas, and performing Atomic Layer Deposition (ALD) at a temperature of 250-400 ℃ to deposit HfZrO with a thickness of 3-50 nm on the oxide semiconductor layer 30 x A film; protecting HfZrO on channel region 31 using a reticle x Thin film and selectively etch off HfZrO over source region 32 and drain region 33 x Thin film to obtain HfZrO x A material layer.
In some embodiments, the top gate 51 satisfies one or more of the following conditions:
1) The material of the top gate 51 includes tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), platinum (Pt), nickel (Ni), molybdenum (Mo), titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum nitride (AlTiN), tungsten nitride (W) 2 N) and molybdenum titanium alloy (MoTi);
2) The thickness of the top gate 51 is 20-100 nm.
In some more preferred embodiments, top gate 51 is a TiN top gate or a TaN top gate.
In some embodiments, the method of forming a TiN top gate includes the steps of: taking a Ti target as a sputtering target material, vacuumizing, introducing nitrogen and argon with flow ratio of 1:4 into a reaction cavity, keeping the cavity pressure of the reaction cavity at 0.1 Pa-1.0 Pa, performing magnetron sputtering at room temperature, and depositing a TiN film with thickness of 20 nm-200 nm on the ferroelectric material layer 41; protection of ferroelectric material layer 41 and TiN film on channel region 31 using a reticle, using carbon tetrafluoride (CF 4 ) And carbon trifluoride (CHF) 3 ) The TiN film over the source region 32 and the drain region 33 is selectively etched away, thereby manufacturing a TiN top gate.
In some embodiments, the method for forming the TaN top gate includes the steps of: taking a Ta target as a sputtering target material, vacuumizing, introducing nitrogen and argon with flow ratio of 1:4 into a reaction cavity, keeping the cavity pressure of the reaction cavity at 0.1 Pa-1.0 Pa, performing magnetron sputtering at room temperature, and depositing a TaN film with thickness of 20 nm-200 nm on a ferroelectric material layer 41; protection of ferroelectric material layer 41 and TaN film on channel region 31 using a reticle, using chlorine (Cl) 2 ) And boron trichloride (BCl) 3 ) Or carbon tetrafluoride (CF) 4 ) And carbon trifluoride (CHF) 3 ) The TaN thin film over the source region 32 and the drain region 33 is selectively etched away, thereby manufacturing a TaN top gate.
In some specific embodiments, the method of forming the ferroelectric material layer 41 and the top gate 51 on the channel region 31 includes the steps of: forming a ferroelectric thin film on the oxide semiconductor layer 30 using an ALD method; forming a gate film on the ferroelectric film by using a magnetron sputtering method; the ferroelectric thin film and the gate thin film on the channel region 31 are protected using a mask, and the ferroelectric thin film and the electrode thin film over the source region 32 and the drain region 33 are selectively etched away, thereby forming the ferroelectric material layer 41 and the top gate 51 on the channel region 31.
S4: a metal reaction layer is formed to cover the source region, the drain region and the top gate electrode.
Please refer to fig. 4, which is a schematic diagram illustrating a structure of the device after step S4 is completed in an embodiment.
In some embodiments, metal reaction layer 61 satisfies one or more of the following conditions:
1) The metal reaction layer 61 is a titanium reaction layer and/or an aluminum reaction layer;
2) The thickness of the metal reaction layer 61 is 2nm to 10nm.
The two metal simple substances of Ti and Al not only can abstract oxygen elements of the source region 32 and the drain region 33, improve the carrier concentration of the two metal simple substances and reduce the resistivity of the two metal simple substances to obtain the conductive source region 34 and the conductive drain region 35, but also can spontaneously oxidize the two metal simple substances in the rapid annealing process to form a titanium dioxide or aluminum oxide passivation layer with good water-blocking oxygen effect, so that good ohmic contact is obtained among the source/drain electrode, the passivation layer and the conductive source/drain region, and the diffusion of the conductive region is avoided without introducing hydrogen elements, thereby avoiding the non-uniformity of the electrical characteristics of the device.
In some more preferred embodiments, the metal reaction layer 61 is an aluminum reaction layer.
In some specific embodiments, the method of forming the metal reaction layer 61 includes the steps of: taking an Al target as a sputtering target material, vacuumizing, introducing argon into the reaction cavity, performing magnetron sputtering at room temperature, and depositing on the source region 32, the drain region 33 and the top grid electrode 51 to obtain an Al reaction layer with the thickness of 2-10 nm.
S5: annealing at 300-600 ℃ in oxidizing atmosphere to induce ferroelectric material layer to form ferroelectric phase to obtain ferroelectric medium layer, and capturing oxygen element in source region and drain region by metal reaction layer to obtain conductive source region and conductive drain region, and spontaneously oxidizing metal reaction layer to obtain passivation layer.
Please refer to fig. 5, which is a schematic diagram illustrating a structure of the device after step S5 is completed in an embodiment. The ferroelectric material layer 41 on the channel region 31 is induced to form a ferroelectric layer 42 having ferroelectric properties; the resistivity of the source region 32 and the drain region 33 decreases after the oxygen is extracted, and the source region and the drain region are converted into a conductive source region 34 and a conductive drain region 35; the metal reaction layer 61 spontaneously oxidizes to form a passivation layer 62.
It is understood that the oxidizing atmosphere is an atmosphere having oxidizing ability, which may be pure oxygen, ozone, and a mixed gas containing oxygen and/or ozone. The mixed gas containing oxygen and/or ozone refers to a gas obtained by mixing at least one of oxygen and ozone with at least one of nitrogen, carbon dioxide, helium, neon, argon, and krypton, for example, air, dry Air (CDA), a mixed gas of oxygen and nitrogen, a mixed gas of oxygen and argon, a mixed gas of ozone and nitrogen, and a mixed gas of oxygen, ozone, and nitrogen.
In some embodiments, the oxidizing atmosphere comprises one or more of oxygen, ozone, and air.
In some embodiments, the oxidizing atmosphere satisfies one or more of the following conditions:
1) The volume fraction of oxygen is more than or equal to 10%;
2) The volume fraction of ozone is more than or equal to 0.02%;
3) The pressure of the oxidizing atmosphere is 0.1atm to 1atm.
In the oxidizing atmosphere, the volume fraction of oxygen is 4% -5% of that of a common oxidizing atmosphere, and the volume fraction of oxygen is >5% of that of a strong oxidizing atmosphere. In the rapid annealing process, the volume fraction of oxygen or ozone is increased, so that the oxidizing atmosphere has strong oxidizing capability, and the rapid annealing time is shortened. The pressure of the oxidizing atmosphere is 0.1atm to 1atm, so that the oxygen and/or ozone can be ensured to have higher reaction concentration, the reaction rate is further accelerated, and the rapid annealing process is shortened.
In some embodiments, the annealing meets one or more of the following conditions:
1) The annealing time is 20 s-600 s;
2) The heating rate is 10 ℃/s to 30 ℃/s;
3) The cooling rate is 1 ℃/s to 10 ℃/s.
In the conventional technology, the resistivity of the source region and the drain region can be improved by annealing after covering an Al film on the IGZO semiconductor layer, but the annealing atmosphere is usually pure nitrogen atmosphere, the annealing temperature is not more than 300 ℃, the annealing time is at least 1h, and three functions of conducting the source region and the drain region, inducing phase inversion of the ferroelectric material layer and spontaneous oxidation of the metal reaction layer can not be simultaneously realized in a very short time by only one annealing. In contrast, the annealing conditions such as annealing temperature, heat preservation time, heating rate and cooling time are regulated and controlled, and rapid annealing is performed in an oxidizing atmosphere, so that the ferroelectric material layer 41 can be promoted to rapidly undergo phase inversion, the ferroelectric dielectric layer 42 with good ferroelectricity is obtained, meanwhile, the source region 32 and the drain region 33 are ensured to be fully conductive, the metal reaction layer 61 can be completely oxidized into the passivation layer 62, and the internal defects are eliminated, the quality of each layer of film is improved, and the degradation of the device performance is effectively avoided.
S6: source and drain electrodes are formed in the passivation layer.
Please refer to fig. 6, which is a schematic diagram illustrating a structure of the device after step S6 is completed in an embodiment.
In some embodiments, the method of forming the source electrode 71 and the drain electrode 72 in the passivation layer 62 includes the steps of: by photolithography process, chlorine (Cl) 2 ) And boron trichloride (BCl) 3 ) Selectively etching the passivation layer 62, forming a source via in the passivation layer 62 over the conductive source region 34, and forming a drain via in the passivation layer 62 over the conductive drain region 35; the source electrode 71 is formed in the source via hole and the drain electrode 72 is formed in the drain via hole by a magnetron sputtering method or an electron beam evaporation and Lift-off (Lift-off) method.
In some embodiments, the source 71 and drain 72 satisfy one or more of the following conditions:
1) The material of the source electrode 71 and the drain electrode 72 includes tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), platinum (Pt), nickel (Ni), molybdenum (Mo), titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum nitride (AlTiN), tungsten nitride (W) 2 N), titanium carbide (TiC), tungsten disilicide (WSi) 2 ) And one or more of Indium Tin Oxide (ITO);
2) The thickness of the source electrode 71 and the drain electrode 72 is 20nm to 100nm.
After forming the source 71 and drain 72 in the passivation layer 62 using the above materials, an ohmic contact junction may be formed between the source (drain) electrode/passivation layer/conductive source (drain) region. On the basis, the thickness of the oxide semiconductor layer 30 is changed, so that the electric characteristics of the device can be greatly regulated and controlled, the contact resistance of the ohmic contact junction is obviously reduced, and the capability of injecting electrons into the oxide semiconductor layer 30 is improved, thereby preparing the high-performance FeFET device.
In some more preferred embodiments, the source 71 and drain 72 are Ni electrodes.
In some embodiments, the method of forming the source electrode 71 and the drain electrode 72 includes the steps of: a 30nm Ni electrode was formed in the passivation layer 62 using a Lift-off process.
In a second aspect of the present invention, a ferroelectric field effect transistor is provided, which is manufactured by the above-mentioned manufacturing method of a ferroelectric field effect transistor.
Fig. 7 is a schematic diagram illustrating an operation principle of a ferroelectric field effect transistor according to an embodiment. In fig. 7 (a), a positive voltage greater than the coercive field of the ferroelectric layer is applied to the top gate, the source and drain are simultaneously grounded, the ferroelectric layer produces positive polarization, the electric field direction is directed to the upper surface of the channel region, and negative compensation charges are attracted to the upper surface of the channel region, so that the channel region is in an accumulated state, and the device is in a low threshold voltage state, or in a logic state of "1". In fig. 7 (b), a reverse voltage greater than the coercive field of the ferroelectric layer is applied to the top gate, the ferroelectric layer produces negative polarization, the electric field direction is directed to the lower surface of the top gate, and positive compensation charge is attracted to the upper surface of the channel region, causing the channel region to assume a depleted state, when the device is in a high threshold voltage state, or a logic state of "0". By the rapid annealing process under the high temperature and oxygen-enriched atmosphere, the source region and the drain region are conducted by utilizing the metal reaction layer, so that the lap joint state between the source electrode, the drain electrode and the oxide semiconductor layer is improved, the contact resistance is obviously reduced, and the ferroelectric field effect transistor with low operation voltage and high carrier mobility is obtained.
In a third aspect of the present invention, there is provided a ferroelectric memory comprising a ferroelectric field effect transistor as described above.
It will be appreciated that although the various steps in the flowchart of fig. 1 are shown in turn as indicated by arrows, these steps are not necessarily performed in the order indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least a portion of the steps in fig. 1 may include a plurality of steps or stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of the steps or stages is not necessarily sequential, but may be performed in rotation or alternatively with at least a portion of the steps or stages in other steps or other steps.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the invention, which are described in detail and are not to be construed as limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. The scope of the invention is therefore intended to be covered by the appended claims, and the description and drawings may be interpreted in accordance with the contents of the claims.

Claims (10)

1. A method of fabricating a ferroelectric field effect transistor, comprising the steps of:
forming an oxide semiconductor layer on a substrate, wherein the oxide semiconductor layer comprises a channel region, and a source region and a drain region which are positioned at two sides of the channel region;
forming a ferroelectric material layer on the channel region, and forming a top gate on the ferroelectric material layer;
forming a metal reaction layer to cover the source region, the drain region and the top gate;
annealing at 300-600 ℃ in an oxidizing atmosphere to induce the ferroelectric material layer to form a ferroelectric phase to obtain a ferroelectric medium layer, and enabling oxygen elements of the source region and the drain region to be extracted by the metal reaction layer to obtain a conductive source region and a conductive drain region, and enabling the metal reaction layer to be spontaneously oxidized to obtain a passivation layer;
and forming a source electrode and a drain electrode in the passivation layer.
2. The method of manufacturing a ferroelectric field effect transistor according to claim 1, wherein the oxidizing atmosphere comprises one or more of oxygen, air, and ozone.
3. The method of manufacturing a ferroelectric field effect transistor according to claim 2, wherein the oxidizing atmosphere satisfies one or more of the following conditions:
1) The volume fraction of the oxygen is more than or equal to 10%;
2) The volume fraction of the ozone is more than or equal to 0.02%;
3) The pressure of the oxidizing atmosphere is 0.1atm to 1atm.
4. The method of manufacturing a ferroelectric field effect transistor according to claim 1, wherein the annealing satisfies one or more of the following conditions:
1) The annealing time is 20 s-600 s;
2) The heating rate is 10 ℃/s to 30 ℃/s;
3) The cooling rate is 1 ℃/s to 10 ℃/s.
5. The method of manufacturing a ferroelectric field effect transistor according to any one of claims 1 to 4, wherein the oxide semiconductor layer satisfies one or more of the following conditions:
1) The oxide semiconductor layer is an indium-based oxide semiconductor layer;
2) The thickness of the oxide semiconductor layer is 5 nm-50 nm.
6. The method of manufacturing a ferroelectric field effect transistor according to claim 5, wherein the metal reaction layer satisfies one or more of the following conditions:
1) The metal reaction layer is a titanium reaction layer and/or an aluminum reaction layer;
2) The thickness of the metal reaction layer is 2 nm-10 nm.
7. The method of manufacturing a ferroelectric field effect transistor according to any one of claims 1 to 4, wherein the ferroelectric material layer satisfies one or more of the following conditions:
1) The ferroelectric material comprises one or more of doped hafnium oxide, strontium bismuth tantalate, lead zirconate titanate, barium titanate, bismuth ferrite, cadmium pyroniobate and zinc metastannite;
2) The thickness of the ferroelectric material layer is 3 nm-50 nm.
8. The method of manufacturing a ferroelectric field effect transistor according to any one of claims 1 to 4, wherein the ferroelectric field effect transistor satisfies one or more of the following conditions:
1) Materials of the top gate, the source and the drain include one or more of tungsten, titanium, copper, aluminum, platinum, nickel, molybdenum, titanium nitride, tungsten nitride, tantalum nitride, titanium aluminum nitride, titanium carbide, tungsten disilicide, indium tin oxide, and molybdenum titanium alloy;
2) The thicknesses of the top grid electrode, the source electrode and the drain electrode are 20 nm-100 nm.
9. A ferroelectric field effect transistor manufactured by the manufacturing method of a ferroelectric field effect transistor according to any one of claims 1 to 8.
10. A ferroelectric memory comprising a ferroelectric field effect transistor according to claim 9.
CN202310219281.9A 2023-03-03 2023-03-03 Ferroelectric field effect transistor, preparation method thereof and ferroelectric memory Pending CN116344345A (en)

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