CN116319618A - Switch operation control method, device, system, equipment and storage medium - Google Patents
Switch operation control method, device, system, equipment and storage medium Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/35—Switches specially adapted for specific applications
- H04L49/351—Switches specially adapted for specific applications for local area network [LAN], e.g. Ethernet switches
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
- H04L12/40013—Details regarding a bus controller
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40169—Flexible bus arrangements
- H04L12/40176—Flexible bus arrangements involving redundancy
- H04L12/40189—Flexible bus arrangements involving redundancy by using a plurality of bus systems
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/55—Prevention, detection or correction of errors
- H04L49/557—Error correction, e.g. fault recovery or fault tolerance
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Abstract
The embodiment of the invention provides a method, a device, a system, equipment and a storage medium for controlling the operation of a switch, wherein the method comprises the following steps: obtaining the use right of the bus controller, entering a main CPU working state, and sending working signals to a second CPU in a slave CPU working state at regular time so that the second CPU monitors the first CPU working state according to the working signals; and receiving an abnormality indication signal sent by the second CPU to reset and restart, and entering the working state of the slave CPU from the working state of the master CPU. The dual-CPU switch system based on the bus controller enters the working state of the main CPU to be responsible for the operation of the switch, and enters the working state of the auxiliary CPU to be responsible for monitoring the working state of the main CPU, when the working state of the main CPU is abnormal, the working state of the main CPU and the auxiliary CPU are switched seamlessly, so that the reliability of the switch is ensured, the reliable operation of the switch is realized, and the stability of a data machine room network is improved.
Description
Technical Field
The present invention relates to the field of switch technologies, and in particular, to a method, an apparatus, a system, a device, and a storage medium for controlling switch operation.
Background
In some important database centers, the normal operation of equipment is required to be ensured, so that data service is continuously provided for the outside, wherein a switch is core equipment for providing data exchange service for the outside, and a large-scale Ethernet switch is strong in function, but the internal design is complex, and the switch generally comprises a CPLD (Complex Programmable Logic Device ) and an optical module, wherein the CPLD is used for expanding a general input/output port of a CPU (Central processing Unit) of the switch to realize the functions of resetting a chip of the whole board, detecting temperature and the like; the optical module is used for realizing photoelectric conversion and electro-optical conversion functions on the switch, so that the CPU of the switch can always monitor and control the working states of the operation modules including the CPLD and the optical module in the switch in order to ensure the stable operation of the switch.
However, when the switch CPU itself works abnormally, if the operation and maintenance personnel cannot maintain or replace the switch CPU in time, the switch CPU cannot continuously monitor and control the modules such as the CPLD and the optical module of the switch, and the optical module or other modules are abnormal, so that the problem of data link failure is caused, thereby affecting the normal operation of the switch and further affecting the stability of the data machine room network.
Disclosure of Invention
The embodiment of the invention aims to provide a method, a device, a system, equipment and a storage medium for controlling the operation of a switch, which solve the problem of data link failure caused by abnormal operation of a CPU of the switch so as to realize the reliable operation of the switch, and the specific technical scheme is as follows:
in a first aspect of the present invention, there is provided a method for controlling operation of a switch, applied to a first CPU of the switch, the switch further including a bus controller, and a second CPU communicatively connected to the first CPU, the method including:
obtaining the use right of the bus controller and entering the working state of the main CPU;
sending a working signal to the second CPU in a slave CPU working state at regular time so that the second CPU monitors the first CPU working state according to the working signal;
and receiving an abnormality indication signal sent by the second CPU to reset and restart, and entering the working state of the slave CPU from the working state of the master CPU.
Optionally, the sending, by the timing, an operation signal to the second CPU in a slave CPU operation state, so that after the second CPU monitors the first CPU operation state according to the operation signal, the method further includes:
Acquiring state data of an operation module in the switch, and synchronously transmitting the state data to the second CPU so that the second CPU can thermally back up the state data;
and regulating and controlling the operation module according to the state data and a preset regulation and control strategy.
In a second aspect of the present invention, there is also provided a method for controlling operation of a switch, applied to a second CPU of the switch, the switch further including a bus controller, and a first CPU communicatively connected to the second CPU, the method including:
under the condition that the first CPU is in a main CPU working state, entering a slave CPU working state;
receiving a working signal sent by the first CPU at fixed time, and monitoring the working state of the first CPU according to the working signal;
if the working state of the first CPU is monitored to be abnormal, an abnormality indication signal is sent to the first CPU;
and obtaining the use right of the bus controller, and entering the working state of the main CPU from the working state of the auxiliary CPU.
Optionally, the receiving the working signal sent by the first CPU at regular time, monitoring the working state of the first CPU according to the working signal, includes:
if the working signal sent by the first CPU is not received within the preset time, determining that the working state of the first CPU is abnormal;
And if the working signal sent by the first CPU is received within the preset time, analyzing the working signal, and determining whether the working state of the first CPU is abnormal.
Optionally, after receiving the working signal sent by the first CPU at regular time and monitoring the working state of the first CPU according to the working signal, the method further includes:
receiving state data of an operation module in the switch synchronously sent by the first CPU;
storing and backing up state data of the operation module;
and under the condition that the slave CPU working state is changed into the master CPU working state, regulating and controlling the operation module according to the stored backup state data and a preset regulating and controlling strategy.
In a third aspect of the present invention, there is also provided an operation control device for a switch, applied to a first CPU of the switch, the switch further including a bus controller, and a second CPU communicatively connected to the first CPU, the device including:
the first working module is used for obtaining the use right of the bus controller and entering the working state of the main CPU;
the first sending module is used for sending working signals to the second CPU in the working state of the slave CPU at regular time so that the second CPU monitors the working state of the first CPU according to the working signals;
The second working module is used for receiving the abnormal indication signal sent by the second CPU to reset and restart, and enters the working state of the slave CPU from the working state of the master CPU.
In a fourth aspect of the present invention, there is also provided an operation control device for a switch, applied to a second CPU of the switch, the switch further including a bus controller, and a first CPU communicatively connected to the second CPU, the device including:
the third working module is used for entering a working state of the slave CPU under the condition that the first CPU is in the working state of the master CPU;
the receiving module is used for receiving the working signal sent by the first CPU at fixed time and monitoring the working state of the first CPU according to the working signal;
the second sending module is used for sending an abnormality indication signal to the first CPU if the working state of the first CPU is monitored to be abnormal;
and the fourth working module is used for obtaining the use right of the bus controller and entering the working state of the main CPU from the working state of the auxiliary CPU.
In a fifth aspect of the present invention, there is also provided a switch operation control system applied to a switch, the switch including a first CPU, a second CPU, and a bus controller, wherein the first CPU is communicatively connected to the second CPU, the system including:
The first CPU is used for obtaining the use right of the bus controller, entering a main CPU working state, sending working signals to the second CPU in a slave CPU working state at regular time, so that the second CPU monitors the first CPU working state according to the working signals, receives an abnormality indication signal sent by the second CPU, resets and restarts, and enters the slave CPU working state from the main CPU working state;
the second CPU enters a slave CPU working state under the condition that the first CPU is in a master CPU working state, receives a working signal sent by the first CPU at fixed time, monitors the working state of the first CPU according to the working signal, and sends an abnormality indication signal to the first CPU to obtain the right of use of the bus controller if the first CPU working state is monitored to be abnormal, and enters the master CPU working state from the slave CPU working state;
and the bus controller is used for controlling the first CPU or the second CPU to enter the working state of the main CPU.
In yet another aspect of the present invention, there is also provided a communication apparatus including: a transceiver, a memory, a processor, and a program stored on the memory and executable on the processor;
The processor is configured to read the program in the memory to implement the switch operation control method according to any one of the above.
In yet another aspect of the present invention, there is also provided a computer readable storage medium having instructions stored therein, which when run on a computer, cause the computer to perform any of the above-described switch operation control methods.
According to the switch operation control method provided by the embodiment of the invention, the use right of the bus controller is obtained, the main CPU working state is entered, and the working signal is sent to the second CPU in the slave CPU working state at regular time, so that the second CPU monitors the first CPU working state according to the working signal; and receiving an abnormality indication signal sent by the second CPU to reset and restart, and entering the working state of the slave CPU from the working state of the master CPU. The embodiment of the invention designs a double-CPU switch system based on the bus controller, is responsible for controlling the switch to operate when entering the working state of the main CPU, is responsible for monitoring the working state of the main CPU when entering the working state of the auxiliary CPU, and seamlessly switches the working state of the main CPU and the auxiliary CPU when the working state of the main CPU is abnormal, thereby ensuring the stable operation of the switch, namely providing the software and hardware assurance for the reliable operation of the switch by controlling the switching of the working state of the double CPU, realizing the reliable operation of the switch and improving the stability of a data machine room network.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below.
Fig. 1 is one of the step flowcharts of a switch operation control method provided in an embodiment of the present invention;
fig. 2 is a second flowchart of a step of a method for controlling operation of a switch according to an embodiment of the present invention;
fig. 3 is one of the step flowcharts of another switch operation control method provided in the embodiment of the present invention;
FIG. 4 is a second flowchart illustrating steps of another method for controlling operation of a switch according to an embodiment of the present invention;
fig. 5 is a flowchart of a switch operation control method provided in an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a switch operation control device according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of another operation control device for a switch according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of a switch operation control system according to an embodiment of the present invention;
fig. 9 is a schematic structural diagram of a communication device according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the following detailed description of the embodiments of the present invention will be given with reference to the accompanying drawings. However, those of ordinary skill in the art will understand that in various embodiments of the present invention, numerous technical details have been set forth in order to provide a better understanding of the present application. However, the technical solutions claimed in the present application can be implemented without these technical details and with various changes and modifications based on the following embodiments. The following embodiments are divided for convenience of description, and should not be construed as limiting the specific implementation of the present invention, and the embodiments can be mutually combined and referred to without contradiction.
Referring to fig. 1, one of the step flowcharts of the switch operation control method provided by the embodiment of the present invention is shown and applied to a CPU0, a first CPU, of the switch operation control system shown in fig. 8, where the switch further includes a bus controller, and a second CPU communicatively connected to the first CPU, where the method may include:
and step 101, obtaining the use right of the bus controller and entering the working state of the main CPU.
In the embodiment of the invention, in order to solve the problem that the operation modules such as CPLD complex programmable logic devices, optical modules and the like cannot be subjected to strategy regulation and control when the CPU of the existing switch works abnormally, and the data link is abnormal when the optical modules or other hardware devices work abnormally, the bus controller PCA9641 is utilized to realize the real-time dual-CPU reliable switch operation control, the master-slave working state of the dual-CPU can be switched seamlessly according to the conditions, the operation modules of the switch can be regulated and controlled in the working state of the master CPU, the hot standby and the working state of the master CPU can be monitored in the working state of the slave CPU, and the software and hardware guarantees are provided for the reliable operation of the switch. In the embodiment, the reliable operation of the switch is realized through the double CPU switches, and the stability of the data machine room network is improved.
It should be noted that, the bus controller PCA9641 in this embodiment is an I2C controller with 2 options 1, and has an arbitration function, and can determine that the first CPU or the second CPU in the switch is used as the main CPU to monitor the CPLD and the real-time data of the optical module, and then the other CPU responds to the working state of the main CPU, enters the working state of the slave CPU, monitors the working state of the main CPU in real time, synchronously runs the state data of the module, obtains the control right of the PCA9641 in a short time when the main CPU is abnormal, enters the working state of the main CPU, and obtains and controls the policy of the optical module, so as to ensure the stable and reliable operation of the switch.
Specifically, in the embodiment of the present invention, the first CPU is communicatively connected to the second CPU, when the switch is powered on and started, the first CPU and the second CPU are powered on simultaneously, in this embodiment, the first CPU obtains the usage right of the PCA9641 by default, and enters the working state of the main CPU, that is, when the first CPU is used as the main CPU, the second CPU is used as the slave CPU, backs up data and monitors the working state of the first CPU, and it should be noted that the embodiment of the present invention does not specifically limit the first CPU and the second CPU, and either the first CPU or the second CPU obtains the usage right of the bus controller, and enters the working state of the main CPU, and the embodiment uses the first CPU to obtain the usage right of the bus controller, and enters the working state of the main CPU as an example.
Specifically, after the first CPU obtains the PCA9641 right of use and enters the master CPU operating state, the second CPU enters the slave CPU operating state in response to the operating state of the first CPU, and the first CPU periodically sends an operating signal to the second CPU in the slave CPU operating state, so that the second CPU determines whether the first CPU operating state is abnormal.
It should be noted that, in this embodiment, the first CPU may send the working signal to the second CPU in the working state of the slave CPU at regular time, which may be a time interval preset in the switch control program, and the first CPU is controlled by the script command to send the working signal to the second CPU at intervals of fixed time according to clock triggering, where the timing interval is not specifically limited, and may be set to 5s, which is of course only specific for illustration, and the time interval for sending the working signal in the actual use process may also be set according to the actual operation requirement of the switch, which is not described in detail herein.
In the embodiment of the invention, after the first CPU obtains the PCA9641 right to use and enters the working state of the main CPU, the second CPU responds to the working state of the first CPU and enters the working state of the auxiliary CPU, and is responsible for monitoring the working state of the first CPU so as to feed back the first CPU in time when the first CPU is abnormal or fails. Therefore, when the first CPU receives the abnormality indication signal sent by the second CPU, resetting and restarting are carried out, and after restarting, the first CPU enters into the working state of the slave CPU from the working state of the master CPU, and is responsible for monitoring the working state of the master CPU.
Specifically, the first CPU resets and restarts when receiving the abnormality indication signal sent by the second CPU, and after the first CPU is restarted, the first CPU is switched to a slave CPU working state, and the slave CPU monitors the current master CPU working state, namely, backs up the received CPLD and optical module data in real time, and prepares for switching to the master CPU working state next time and taking over the CPLD and the optical module in real time.
According to the switch operation control method provided by the embodiment of the invention, the use right of the bus controller is obtained, the main CPU working state is entered, and the working signal is sent to the second CPU in the slave CPU working state at regular time, so that the second CPU monitors the first CPU working state according to the working signal; and receiving an abnormality indication signal sent by the second CPU to reset and restart, and entering the working state of the slave CPU from the working state of the master CPU. The embodiment of the invention designs a double-CPU switch system based on the bus controller, is responsible for controlling the switch to operate when entering the working state of the main CPU, is responsible for monitoring the working state of the main CPU when entering the working state of the auxiliary CPU, and seamlessly switches the working state of the main CPU and the auxiliary CPU when the working state of the main CPU is abnormal, thereby ensuring the stable operation of the switch, namely providing the software and hardware assurance for the reliable operation of the switch by controlling the switching of the working state of the double CPU, realizing the reliable operation of the switch and improving the stability of a data machine room network.
Referring to fig. 2, a second step flowchart of a switch operation control method provided by an embodiment of the present invention is shown, where the method may include:
and step 101, obtaining the use right of the bus controller and entering the working state of the main CPU.
In the embodiment of the invention, the first CPU is responsible for regulating and controlling the CPLD and the optical module under the working state of the main CPU, and in order to ensure that the slave CPU applies for bus controller arbitration when the main CPU fails abnormally, obtains the use right to enter the working state of the main CPU, takes over the CPLD and the optical module, does not influence the normal operation of the switch, and the first CPU acquires the state data of the operation module in the switch under the working state of the main CPU and synchronously transmits the state data to the second CPU through network communication in real time so as to enable the second CPU to backup the state data and prepare for hot switching when the main CPU fails.
And 105, regulating and controlling the operation module according to the state data and a preset regulation and control strategy.
In the embodiment of the invention, the CPLD and the optical module are regulated and controlled according to the preset regulation and control strategy of the CPLD and the optical module, so that the CPLD and the optical module are ensured to work normally, and the stable operation of the switch is further realized. Specifically, the switch management plane provides network management personnel with TELNET, WEB, SSH, SNMP, RMON and other modes to manage equipment, and supports operation control of operation modules through preset regulation and control strategies including relevant parameters of various protocols in the control plane. The operation module of the switch includes a CPLD and an optical module, and preset regulation policies of the CPLD and the optical module are set according to actual functions or operation requirements of the switch, which are not limited in detail herein.
It should be noted that, the steps 101-103 are not repeated herein with reference to the foregoing discussion.
In this embodiment, the specific execution positions of steps 104 and 105 are not limited, and in this embodiment, steps 104 and 105 are executed as an example after step 102 and before step 103 for the sake of understanding. In actual use, steps 104 and 105 may also be performed as a step after step 102, and each case will not be described here in detail.
Compared with the prior art, the embodiment of the invention can acquire the state data of the operation module in the switch under the condition of the working state of the main CPU, synchronously send the state data to the second CPU so as to enable the second CPU to back up the state data and prepare for hot switching when the main CPU fails, so that the technical scheme provided by the embodiment of the invention can improve the switching speed when the CPU is abnormal, and ensure the stable operation of the switch by seamlessly switching the working states of the double CPUs. Further, the technical scheme provided by the embodiment can avoid the problem that when the CPU of the switch cannot be maintained or replaced in time due to abnormal work of the CPU of the switch, the system is seriously down or damaged.
Referring to fig. 3, which is one of the step flowcharts of another switch operation control method provided in the embodiment of the present invention, the method is applied to the CPU1 and the second CPU of the switch operation control system shown in fig. 8, where the switch further includes a bus controller, and a first CPU communicatively connected to the second CPU, and the method may include:
In the embodiment of the invention, after the first CPU obtains the PCA9641 right to use and enters the working state of the main CPU, the second CPU responds to the working state of the first CPU and enters the working state of the secondary CPU, and is responsible for monitoring the working state of the first CPU so as to feed back the first CPU in time when the first CPU is abnormal or fails.
In the embodiment of the present invention, the second CPU and the first CPU have the same function, and either party can enter the working state of the master CPU by obtaining the usage right of PCA9641, execute the function of the master CPU, and if one party obtains the usage right to enter the working state of the master CPU, the other party responds to the working state of the master CPU to enter the working state of the slave CPU.
Specifically, the first CPU is in communication connection with the second CPU, after the second CPU enters the working state of the slave CPU, the working signal sent by the first CPU at regular time is received, the working state of the first CPU is monitored according to the working signal, whether the first CPU works normally is judged, and if the working signal sent by the first CPU at regular time is not received within a certain time or abnormality is monitored according to the working signal, the working state of the first CPU is determined to be abnormal. If the first CPU works normally, the second CPU synchronizes data with the first CPU and judges whether the second CPU works normally or not.
Specifically, the step 202 of receiving the working signal sent by the first CPU at regular time, and monitoring the working state of the first CPU according to the working signal may include the following steps:
firstly, if a working signal sent by a first CPU is not received within preset time, determining that the working state of the first CPU is abnormal;
and secondly, if the working signal sent by the first CPU is received within the preset time, analyzing the working signal to determine whether the working state of the first CPU is abnormal.
In the embodiment of the invention, the first CPU is in communication connection with the second CPU, the second CPU analyzes and judges whether the working state of the first CPU is abnormal or not according to the received working signal sent by the first CPU at fixed time, and if the working state of the first CPU is monitored to be abnormal, an abnormal indication signal is sent to the first CPU and used for prompting the first CPU to restart due to the fault, and then the second CPU is timely subjected to hot switching to enter the working state of the main CPU.
In the embodiment of the invention, if the first CPU working state is monitored to be abnormal, the second CPU arbitrates and applies to the PCA9641 to obtain the use right of the bus controller, and the slave CPU working state enters the master CPU working state so as to be switched to the master CPU working state when the first CPU fails to be abnormal, and is responsible for carrying out strategy regulation and control on the optical module, realizing noninductive switching and ensuring the stable operation of the switch. And simultaneously, resetting and restarting the first CPU, entering the working state of the secondary CPU, switching the secondary CPU into the main CPU by the second CPU, controlling the CPLD and the optical module according to a preset regulation and control strategy, monitoring the working state, and sending state data to the secondary CPU.
According to the switch operation control method provided by the embodiment of the invention, the working state of the slave CPU is entered under the condition that the first CPU is in the working state of the master CPU; receiving a working signal sent by a first CPU at fixed time, and monitoring the working state of the first CPU according to the working signal; if the working state of the first CPU is monitored to be abnormal, an abnormality indication signal is sent to the first CPU; the use right of the bus controller is obtained, and the slave CPU working state enters the master CPU working state. The embodiment of the invention designs a double-CPU switch system based on the bus controller, is responsible for controlling the switch to operate when entering the working state of the main CPU, is responsible for monitoring the working state of the main CPU when entering the working state of the auxiliary CPU, and seamlessly switches the working state of the main CPU and the auxiliary CPU when the working state of the main CPU is abnormal, thereby ensuring the stable operation of the switch, namely providing the software and hardware assurance for the reliable operation of the switch by controlling the switching of the working state of the double CPU, realizing the reliable operation of the switch and improving the stability of a data machine room network.
Referring to fig. 4, a second step flowchart of another method for controlling operation of a switch according to an embodiment of the present invention is shown, where the method may include:
Specifically, the first CPU is responsible for regulating and controlling the CPLD and the optical module in the working state of the main CPU, and in order to ensure that when the main CPU fails abnormally, the slave CPU applies for bus controller arbitration, obtains the right of use to enter the working state of the main CPU, and takes over the CPLD and the optical module, thereby not affecting the normal operation of the switch. Therefore, the second CPU receives the state data of the operation module in the switch synchronously transmitted by the first CPU, stores the state data of the backup operation module, and prepares for hot switching when the main CPU fails.
In the embodiment of the invention, if the second CPU monitors that the working state of the first CPU is abnormal, the second CPU arbitrates and applies to the PCA9641 to obtain the use right of the bus controller, and after the working state of the slave CPU enters the working state of the master CPU, namely when the first CPU is abnormal, the working state of the slave CPU is switched to the working state of the master CPU, the second CPU is responsible for strategy regulation and control of the optical module, controls the CPLD and the optical module according to a preset regulation and control strategy, monitors the working state, sends state data to the slave CPU, realizes noninductive switching, and ensures the stable operation of the switch.
It should be noted that, the steps 201-204 are not repeated herein with reference to the foregoing.
In this embodiment, the specific execution positions of steps 205 and 206 are not limited, and in this embodiment, steps 205 and 206 are executed as an example after step 202 and before step 203 for the sake of understanding. In actual use, steps 205 and 206 may also be performed as a complete step, after step 203, and each case will not be described in detail herein.
Compared with the prior art, the embodiment of the invention can synchronously back up the state data of the operation module in the switch on the basis of the beneficial effects brought by the second embodiment, prepare for hot switching when the main CPU is in fault, and enable the second CPU to enter from the working state of the main CPU to the working state of the main CPU when the main CPU is abnormal, so that the technical scheme provided by the embodiment of the invention can improve the switching speed when the CPU is abnormal, thereby ensuring the stable work of the switch by seamlessly switching the working states of the double CPUs. Further, the technical scheme provided by the embodiment can avoid the problem that when the CPU of the switch cannot be maintained or replaced in time due to abnormal work of the CPU of the switch, the system is seriously down or damaged.
In order to enable those skilled in the art to more clearly understand the flow of the switch operation control method disclosed in the above embodiment of the present invention, referring to fig. 5, a flowchart of the switch operation control method provided in the embodiment of the present invention is applied to the switch operation control system shown in fig. 8, and is described as an example.
In step 301, cpu0 starts.
It should be noted that, in this embodiment, the switch operation control system includes two CPUs, and in this embodiment, CPU0 is used as a master CPU after the switch is powered on, and in step 307, CPU1 is used as a slave CPU while CPU0 is powered on, and is powered on.
In step 303, CPU0 transmits an operation signal to CPU 1.
Specifically, after the CPU0 obtains the PCA9641 right of use to enter the master CPU operating state, the CPU1 enters the slave CPU operating state in response to the operating state of the CPU0, and the CPU0 periodically transmits an operating signal to the CPU1 in the slave CPU operating state, so that the CPU1 determines whether or not there is an abnormality in the CPU0 operating state.
In the present embodiment, the CPU0 transmits the operation signal to the CPU1 in the slave CPU operation state at regular intervals of 5 s.
Specifically, when the CPU0 is used as a main CPU, the CPLD and the optical module are regulated and controlled according to a preset regulation and control strategy, so that the CPLD and the optical module are ensured to work normally, and the stable operation of the switch is further realized. Specifically, through a preset regulation strategy including relevant parameters of various protocols in a control plane, operation control of an operation module is supported.
Specifically, the CPU0 is responsible for regulating and controlling the CPLD and the optical module in the working state of the main CPU, and in order to ensure that when the CPU0 fails abnormally, the CPU1 obtains the right to use to enter the working state of the main CPU, takes over the CPLD and the optical module, does not affect the normal operation of the switch, and the CPU0 obtains the state data of the operation module in the switch in the working state of the main CPU, synchronously sends the state data to the CPU1 in real time through network communication, so that the CPU1 backs up the state data, and prepares for hot switching when the CPU0 fails.
When the CPU0 receives the abnormality indication signal sent by the CPU1, it resets and restarts, and after restarting, it enters from the master CPU operating state to the slave CPU operating state, and is responsible for monitoring the operating state of the master CPU 1.
In step 307, cpu1 starts.
Specifically, the CPU0 acquires state data of an operation module in the switch under the working state of the main CPU, synchronously transmits the state data to the CPU1 in real time through network communication, and the CPU1 receives the synchronous state data and backs up the state data to prepare for hot switching when the CPU0 fails.
Specifically, the CPU0 is communicatively connected to the CPU1, and after the CPU1 enters the slave CPU operating state, the CPU1 receives an operating signal sent by the CPU0 at regular time, monitors the operating state of the CPU0 according to the operating signal, and enters step 311 to determine whether the CPU0 is operating normally.
If the working signal sent by CPU0 at regular time is not received or if abnormality is monitored according to the working signal, the working state abnormality of CPU0 is determined. If CPU0 is operating normally, CPU1 goes to step 308 to synchronize data with the first CPU for the next round and to determine if the second CPU is operating normally.
Specifically, when the CPU1 is used as a main CPU, the CPLD and the optical module data are regulated and controlled according to the backup CPLD and the optical module data and a preset regulation and control strategy, so that the CPLD and the optical module can work normally, and the stable operation of the switch is further realized.
In the embodiment of the invention, a dual-CPU switch system is designed based on the bus controller, and is responsible for controlling the switch to operate when entering the working state of the main CPU, and is responsible for monitoring the working state of the main CPU when entering the working state of the auxiliary CPU, and when the working state of the main CPU is abnormal, the working state of the main CPU and the auxiliary CPU are seamlessly switched, so that the switch is ensured to operate stably, namely, the switching of the working state of the dual CPU is controlled, the software and hardware are ensured for the reliable operation of the switch, the reliable operation of the switch is realized, and the stability of a data computer room network is improved.
Referring to fig. 6, a schematic structural diagram of a switch operation control device provided by an embodiment of the present invention is applied to a first CPU of a switch, where the switch further includes a bus controller, and a second CPU communicatively connected to the first CPU, where the device may include:
the first working module 401 is configured to obtain a right of use of the bus controller, and enter a working state of the main CPU;
A first sending module 402, configured to send a working signal to the second CPU in a slave CPU working state at a fixed time, so that the second CPU monitors the first CPU working state according to the working signal;
and the second working module 403 is configured to receive the abnormality indication signal sent by the second CPU, reset and restart the second CPU, and enter the working state of the slave CPU from the working state of the master CPU. An information obtaining module 301, configured to obtain sensor temperature information and a timestamp, where the timestamp is a time when the BMC records the sensor temperature information;
further, the device further comprises:
the data acquisition module is used for acquiring the state data of the operation module in the switch and synchronously transmitting the state data to the second CPU so that the second CPU backs up the state data;
the first regulation and control module is used for regulating and controlling the operation module according to the state data and a preset regulation and control strategy.
The switch operation control device provided by the embodiment of the invention enters the working state of the main CPU by obtaining the use right of the bus controller, and sends working signals to the second CPU in the working state of the auxiliary CPU at regular time so that the second CPU monitors the working state of the first CPU according to the working signals; and receiving an abnormality indication signal sent by the second CPU to reset and restart, and entering the working state of the slave CPU from the working state of the master CPU. The embodiment of the invention designs a double-CPU switch system based on the bus controller, is responsible for controlling the switch to operate when entering the working state of the main CPU, is responsible for monitoring the working state of the main CPU when entering the working state of the auxiliary CPU, and seamlessly switches the working state of the main CPU and the auxiliary CPU when the working state of the main CPU is abnormal, thereby ensuring the stable operation of the switch, namely providing the software and hardware assurance for the reliable operation of the switch by controlling the switching of the working state of the double CPU, realizing the reliable operation of the switch and improving the stability of a data machine room network.
Referring to fig. 7, a schematic structural diagram of another switch operation control device provided by an embodiment of the present invention is applied to a second CPU of a switch, where the switch further includes a bus controller, and a first CPU communicatively connected to the second CPU, where the device may include:
a third working module 501, configured to enter a working state of a slave CPU when the first CPU is in a working state of the master CPU;
the receiving module 502 is configured to receive a working signal sent by the first CPU at regular time, and monitor a working state of the first CPU according to the working signal;
a second sending module 503, configured to send an abnormality indication signal to the first CPU if the first CPU is monitored to have an abnormal working state;
a fourth operation module 504, configured to obtain a right of use of the bus controller, and enter the master CPU operation state from the slave CPU operation state.
Further, the receiving module 502 includes:
the first determining submodule is used for determining that the working state of the first CPU is abnormal if the working signal sent by the first CPU is not received within preset time;
and the second determining submodule is used for analyzing the working signal if the working signal sent by the first CPU is received within the preset time, and determining whether the working state of the first CPU is abnormal or not.
Further, the device further comprises:
the storage backup module is used for receiving the state data of the operation module in the switch synchronously sent by the first CPU and storing and backing up the state data of the operation module;
the second regulation and control module is used for regulating and controlling the operation module according to the stored backup state data and a preset regulation and control strategy under the condition that the slave CPU working state is changed into the master CPU working state.
According to the switch operation control method provided by the embodiment of the invention, the working state of the slave CPU is entered under the condition that the first CPU is in the working state of the master CPU; receiving a working signal sent by a first CPU at fixed time, and monitoring the working state of the first CPU according to the working signal; if the working state of the first CPU is monitored to be abnormal, an abnormality indication signal is sent to the first CPU; the use right of the bus controller is obtained, and the slave CPU working state enters the master CPU working state. The embodiment of the invention designs a double-CPU switch system based on the bus controller, is responsible for controlling the switch to operate when entering the working state of the main CPU, is responsible for monitoring the working state of the main CPU when entering the working state of the auxiliary CPU, and seamlessly switches the working state of the main CPU and the auxiliary CPU when the working state of the main CPU is abnormal, thereby ensuring the stable operation of the switch, namely providing the software and hardware assurance for the reliable operation of the switch by controlling the switching of the working state of the double CPU, realizing the reliable operation of the switch and improving the stability of a data machine room network.
Referring to fig. 8, a schematic structural diagram of a switch operation control system provided by an embodiment of the present invention is shown, where the system may include: the system comprises a first CPU, a second CPU and a bus controller.
The first CPU is used for obtaining the use right of the bus controller, entering a main CPU working state, sending working signals to the second CPU in a slave CPU working state at regular time, so that the second CPU monitors the first CPU working state according to the working signals, receives an abnormality indication signal sent by the second CPU, resets and restarts, and enters the slave CPU working state from the main CPU working state;
the second CPU enters a slave CPU working state under the condition that the first CPU is in a master CPU working state, receives a working signal sent by the first CPU at fixed time, monitors the working state of the first CPU according to the working signal, and sends an abnormality indication signal to the first CPU to obtain the right of use of the bus controller if the first CPU working state is monitored to be abnormal, and enters the master CPU working state from the slave CPU working state;
and the bus controller is used for controlling the first CPU or the second CPU to enter the working state of the main CPU.
The switch operation control system in the embodiment of the invention designs a double-CPU switch system based on the bus controller, and is responsible for controlling the switch to operate when entering the working state of the master CPU or the second CPU, and for monitoring the working state of the master CPU when entering the working state of the slave CPU, and when the working state of the master CPU is abnormal, the master CPU and the slave CPU are switched in a seamless way to ensure the stable operation of the switch, namely, the switch of the working state of the double CPU is controlled to provide the software and hardware guarantee for the reliable operation of the switch, thereby realizing the reliable operation of the switch and improving the stability of a data computer room network.
The embodiment of the present invention also provides a communication device, as shown in fig. 9, including a processor 601, a communication interface 602, a memory 603, and a communication bus 604, where the processor 601, the communication interface 602, and the memory 603 perform communication with each other through the communication bus 604,
a memory 603 for storing a computer program;
the processor 601 is configured to execute the program stored in the memory 603, and implement the following steps:
obtaining the use right of the bus controller and entering the working state of the main CPU; sending a working signal to the second CPU in a slave CPU working state at regular time so that the second CPU monitors the first CPU working state according to the working signal; and receiving an abnormality indication signal sent by the second CPU to reset and restart, and entering the working state of the slave CPU from the working state of the master CPU.
Alternatively, the following steps are implemented:
under the condition that the first CPU is in a main CPU working state, entering a slave CPU working state; receiving a working signal sent by the first CPU at fixed time, and monitoring the working state of the first CPU according to the working signal; if the working state of the first CPU is monitored to be abnormal, an abnormality indication signal is sent to the first CPU; and obtaining the use right of the bus controller, and entering the working state of the main CPU from the working state of the auxiliary CPU.
The communication bus mentioned by the above terminal may be a peripheral component interconnect standard (Peripheral Component Interconnect, abbreviated as PCI) bus or an extended industry standard architecture (Extended Industry Standard Architecture, abbreviated as EISA) bus, etc. The communication bus may be classified as an address bus, a data bus, a control bus, or the like. For ease of illustration, the figures are shown with only one bold line, but not with only one bus or one type of bus.
The communication interface is used for communication between the terminal and other devices.
The memory may include random access memory (Random Access Memory, RAM) or non-volatile memory (non-volatile memory), such as at least one disk memory. Optionally, the memory may also be at least one memory device located remotely from the aforementioned processor.
The processor may be a general-purpose processor, including a central processing unit (Central Processing Unit, CPU for short), a network processor (Network Processor, NP for short), etc.; but also digital signal processors (Digital Signal Processing, DSP for short), application specific integrated circuits (Application Specific Integrated Circuit, ASIC for short), field-programmable gate arrays (Field-Programmable Gate Array, FPGA for short) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.
In yet another embodiment of the present invention, a computer readable storage medium is provided, in which instructions are stored, which when run on a computer, cause the computer to perform the switch operation control method according to any one of the above embodiments.
In yet another embodiment of the present invention, a computer program product containing instructions that, when run on a computer, cause the computer to perform the switch operation control method of any of the above embodiments is also provided.
In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, produces a flow or function in accordance with embodiments of the present invention, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in or transmitted from one computer-readable storage medium to another, for example, by wired (e.g., coaxial cable, optical fiber, digital Subscriber Line (DSL)), or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid state disk SolidStateDisk (SSD)), etc.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
In this specification, each embodiment is described in a related manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for system embodiments, since they are substantially similar to method embodiments, the description is relatively simple, as relevant to see a section of the description of method embodiments.
The foregoing description is only of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.
Claims (10)
1. A method of controlling operation of a switch, characterized by a first CPU applied to the switch, the switch further comprising a bus controller, and a second CPU communicatively coupled to the first CPU, the method comprising:
obtaining the use right of the bus controller and entering the working state of the main CPU;
sending a working signal to the second CPU in a slave CPU working state at regular time so that the second CPU monitors the first CPU working state according to the working signal;
and receiving an abnormality indication signal sent by the second CPU to reset and restart, and entering the working state of the slave CPU from the working state of the master CPU.
2. The method of claim 1, wherein the timing sends an operation signal to the second CPU in a slave CPU operation state to cause the second CPU to monitor the first CPU operation state based on the operation signal, further comprising:
acquiring state data of an operation module in the switch, and synchronously transmitting the state data to the second CPU so that the second CPU backs up the state data;
And regulating and controlling the operation module according to the state data and a preset regulation and control strategy.
3. A method of controlling operation of a switch, characterized by a second CPU applied to the switch, the switch further comprising a bus controller, and a first CPU communicatively coupled to the second CPU, the method comprising:
under the condition that the first CPU is in a main CPU working state, entering a slave CPU working state;
receiving a working signal sent by the first CPU at fixed time, and monitoring the working state of the first CPU according to the working signal;
if the working state of the first CPU is monitored to be abnormal, an abnormality indication signal is sent to the first CPU;
and obtaining the use right of the bus controller, and entering the working state of the main CPU from the working state of the auxiliary CPU.
4. The method of claim 1, wherein the receiving the working signal sent by the first CPU at regular time, and monitoring the working state of the first CPU according to the working signal, comprises:
if the working signal sent by the first CPU is not received within the preset time, determining that the working state of the first CPU is abnormal;
and if the working signal sent by the first CPU is received within the preset time, analyzing the working signal, and determining whether the working state of the first CPU is abnormal.
5. The method according to claim 1, wherein the receiving the working signal sent by the first CPU at regular time, and monitoring the working state of the first CPU according to the working signal, further comprises:
receiving state data of an operation module in the switch synchronously transmitted by the first CPU, and storing and backing up the state data of the operation module;
and under the condition that the slave CPU working state is changed into the master CPU working state, regulating and controlling the operation module according to the stored backup state data and a preset regulating and controlling strategy.
6. A switch operation control device, characterized by a first CPU applied to a switch, the switch further comprising a bus controller, and a second CPU communicatively connected to the first CPU, the device comprising:
the first working module is used for obtaining the use right of the bus controller and entering the working state of the main CPU;
the first sending module is used for sending working signals to the second CPU in the working state of the slave CPU at regular time so that the second CPU monitors the working state of the first CPU according to the working signals;
the second working module is used for receiving the abnormal indication signal sent by the second CPU to reset and restart, and enters the working state of the slave CPU from the working state of the master CPU.
7. A switch operation control device, characterized by a second CPU applied to a switch, the switch further comprising a bus controller, and a first CPU communicatively connected to the second CPU, the device comprising:
the third working module is used for entering a working state of the slave CPU under the condition that the first CPU is in the working state of the master CPU;
the receiving module is used for receiving the working signal sent by the first CPU at fixed time and monitoring the working state of the first CPU according to the working signal;
the second sending module is used for sending an abnormality indication signal to the first CPU if the working state of the first CPU is monitored to be abnormal;
and the fourth working module is used for obtaining the use right of the bus controller and entering the working state of the main CPU from the working state of the auxiliary CPU.
8. A switch operation control system, characterized by being applied to a switch, the switch including a first CPU, a second CPU, and a bus controller, wherein the first CPU is communicatively connected to the second CPU, the system comprising:
the first CPU is used for obtaining the use right of the bus controller, entering a main CPU working state, sending working signals to the second CPU in a slave CPU working state at regular time, so that the second CPU monitors the first CPU working state according to the working signals, receives an abnormality indication signal sent by the second CPU, resets and restarts, and enters the slave CPU working state from the main CPU working state;
The second CPU enters a slave CPU working state under the condition that the first CPU is in a master CPU working state, receives a working signal sent by the first CPU at fixed time, monitors the working state of the first CPU according to the working signal, and sends an abnormality indication signal to the first CPU to obtain the right of use of the bus controller if the first CPU working state is monitored to be abnormal, and enters the master CPU working state from the slave CPU working state;
and the bus controller is used for controlling the first CPU or the second CPU to enter the working state of the main CPU.
9. A communication device, comprising: a transceiver, a memory, a processor, and a program stored on the memory and executable on the processor;
the processor is configured to read a program in a memory to implement the steps in the switch operation control method according to any one of claims 1 to 2 or the steps in the switch operation control method according to any one of claims 3 to 5.
10. A readable storage medium storing a program, wherein the program when executed by a processor implements the steps of the switch operation control method according to any one of claims 1-2, or the steps of the switch operation control method according to any one of claims 3-5.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117472596A (en) * | 2023-12-27 | 2024-01-30 | 苏州元脑智能科技有限公司 | Distributed resource management method, device, system, equipment and storage medium |
| CN117544584A (en) * | 2024-01-09 | 2024-02-09 | 紫光恒越技术有限公司 | Control method, device, switch and medium based on double CPU architecture |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117472596A (en) * | 2023-12-27 | 2024-01-30 | 苏州元脑智能科技有限公司 | Distributed resource management method, device, system, equipment and storage medium |
| CN117472596B (en) * | 2023-12-27 | 2024-03-22 | 苏州元脑智能科技有限公司 | Distributed resource management method, device, system, equipment and storage medium |
| CN117544584A (en) * | 2024-01-09 | 2024-02-09 | 紫光恒越技术有限公司 | Control method, device, switch and medium based on double CPU architecture |
| CN117544584B (en) * | 2024-01-09 | 2024-04-16 | 紫光恒越技术有限公司 | Control method, device, switch and medium based on double CPU architecture |
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