CN116318412A - SerDes high-speed communication system based on domestic FPGA - Google Patents
SerDes high-speed communication system based on domestic FPGA Download PDFInfo
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Abstract
The invention relates to a SerDes high-speed communication system based on a domestic FPGA, belonging to the technical field of SerDes communication. The system of the invention comprises the following parts: the device comprises an FPGA logic design module, a sending module, a receiving module, a clock management module, a differential serial data interface and a differential clock interface. The FPGA logic design module, the sending module, the receiving module and the clock processing module are all realized by the FPGA. The technical scheme provided by the invention realizes high-speed SerDes data communication on a domestic FPGA platform, and meets the application requirement; compared with the 8B/10B coding scheme adopted in the prior art, the 64B/66B coding mode adopted in the invention can effectively improve the data transmission efficiency, and has more advantages in a high-speed data transmission application environment; the invention simplifies the 64B/66B coding design, realizes related functions by the IP core and the custom logic together, and effectively saves cost and development period.
Description
Technical Field
The invention belongs to the technical field of SerDes communication, and particularly relates to a SerDes high-speed communication system based on a domestic FPGA.
Background
With the continuous development of the fields of satellite-borne communication, radar test and the like, the requirements of high-speed data acquisition technology are continuously increased, and the problems of clock synchronization, line loss, signal crosstalk and the like of the traditional parallel interface design are difficult to meet the increasing data transmission rate. The high-speed serial transmission technology has the advantages of high bandwidth, low delay, good signal integrity, strong expandability and the like, and is widely applied to application scenes requiring high-speed intensive calculation, such as digital signal processing, high-speed data processing and the like. Wherein the typical implementation is a SerDes communication scheme. The advantage of SerDes is that it is very bandwidth, has a small pin count and supports a variety of mainstream interfaces, such as RapidIO, FC, PCIE, SATA, XAUI.
In SerDes data transmission applications, line coding is necessary. There are 8B/10B codes and 64B/66B codes in common use today. The 8B/10B coding can realize the functions of direct current balance, clock embedding, control symbol embedding and the like, but the bandwidth loss is larger; 64B/66B coding can overcome the defect of large bandwidth loss, and is suitable for higher-speed communication. Generally, the 64B/66B coding adopts a coding method based on a lookup table, and more FPGA logic resources are consumed.
The FPGA chip has the advantages of high development cycle end, high flexibility, high stability, low cost, high processing speed and the like in system design verification based on the FPGA, and the FPGA becomes an ideal connection platform for realizing serial interface application.
Disclosure of Invention
First, the technical problem to be solved
The technical problem to be solved by the invention is how to provide a SerDes high-speed communication system based on a domestic FPGA so as to solve the problem that the traditional parallel interface design is difficult to meet the increasing data transmission rate due to the problems of clock synchronization, line loss, signal crosstalk and the like.
(II) technical scheme
In order to solve the technical problems, the invention provides a SerDes high-speed communication system based on a domestic FPGA, which comprises an FPGA logic design module, a sending module, a receiving module, a clock management module, a differential serial data interface and a differential clock interface; the FPGA logic design module, the sending module, the receiving module and the clock processing module are all realized by the FPGA;
the differential serial data interface is an optical fiber interface based on SerDes, and is operated by serialized high-speed optical fiber data;
the clock management module is responsible for generating clock signals required by each module and managing the phase relation among the clocks;
the sending module and the receiving module are both composed of a PCS layer and a PMA layer;
in the transmitting module, the TX PCS layer includes: a coding module (TX Gecarbox Block), a phase compensation FIFO and a Polarity control module (TX Polarity) at the transmitting end; the TX PMA layer comprises: a parallel/serial conversion module (PISO), a transmit equalizer, and a transmitter;
the coding module provides effective combination of the synchronous head and the data for 64B/66B coding, and simultaneously finishes sending data scrambling codes;
the phase compensation FIFO is used for rate and phase matching between the parallel clock domains between the TX PMA and the transmit TX PCS;
the polarity control module of the transmitting end is an optional module and is used for driving to be high level from the structural user interface so as to reverse the data polarity;
the parallel/serial conversion module is responsible for converting parallel data in the FPGA into serial data of a SerDes interface;
the function of the transmit equalizer is to compensate for the non-ideal characteristics of the channel;
in the receiving module, the RX PCS layer includes: decoding module (RX Gecarbox Block), elastic buffer FIFO and Polarity control module (RX Polarity) of receiving end, RX PMA layer includes: a serial/parallel conversion module (SIPO), a clock data recovery module (CDR), a reception equalizer, and a receiver;
the receiving equalizer of the receiving module is responsible for equalizing channel loss;
the clock data recovery module (CDR) extracts clock and data from the data stream, captures the frequency of data edge jump when the data passes through so as to obtain clock frequency, and finds the optimal sampling point;
the serial/parallel conversion module is responsible for converting serial data of the SerDes interface into parallel data in the FPGA;
the polarity control module of the receiving end is an optional module and is used for driving to be high level from the structural user interface so as to reverse the data polarity;
there are two different clock domains at the receiving end: the elastic buffer FIFO is used for solving the difference of data of two different clock domains, matching the frequency and the phase between the two clock domains and completing clock correction and channel binding;
the decoding module performs effective separation of the synchronization header and the data for 64B/66B decoding, and simultaneously completes the descrambling of the transmitted data.
(III) beneficial effects
The invention provides a SerDes high-speed communication system based on a domestic FPGA, and the technical scheme provided by the invention realizes high-speed SerDes data communication on a domestic FPGA platform, thereby meeting the application requirements;
compared with the 8B/10B coding scheme adopted in the prior art, the 64B/66B coding mode adopted in the invention can effectively improve the data transmission efficiency, and has more advantages in a high-speed data transmission application environment;
the invention simplifies the 64B/66B coding design, realizes related functions by the IP core and the custom logic together, and effectively saves cost and development period.
Drawings
FIG. 1 is a diagram of a SerDes communication system architecture and data transceiving flow diagram according to the present invention;
FIG. 2 is a diagram illustrating a transmit data encoding process according to the present invention;
fig. 3 is a diagram illustrating a transmit data decoding process according to the present invention.
Detailed Description
To make the objects, contents and advantages of the present invention more apparent, the following detailed description of the present invention will be given with reference to the accompanying drawings and examples.
The invention aims to solve the technical problems that: how to design a SerDes high-speed communication system and method on a domestic platform.
The invention provides a SerDes high-speed communication system based on domestic FPGA, which is responsible for realizing data interaction between an interface and an internal data processing module of the FPGA.
The line coding mechanism selected by the invention is a 64B/66B coding and decoding protocol. The line coding mechanism converts the incoming raw data into a format that can be received by the receiver, provides a way to align the data to words, and ensures that there is sufficient high-low level switching to provide to the clock recovery circuit while maintaining good dc balance. The 64B/66B encoding and decoding technology is an encoding and decoding mode based on a scrambling mechanism, is a standard encoding mode of 10G communication recommended by IEEE, encodes 64-bit data or control information plus a 2-bit synchronous head into 66-bit block transmission, can ensure direct current balance, ensures correct recovery of clocks from data streams, can effectively reduce 8B/10B encoding cost, and is suitable for a higher-speed transmission environment. Besides the synchronous head, the data scrambling is needed before transmission, namely, the data is rearranged or encoded to optimize the data, so that 0 and 1 in the data are distributed randomly to the greatest extent, other sequences which have negative influence on the receiving capability of a receiver are eliminated, jitter inter-code crosstalk is further reduced, and the reliability of the data is improved.
Referring to fig. 1, the measuring system of the present invention mainly comprises the following parts: the device comprises an FPGA logic design module, a sending module, a receiving module, a clock management module, a differential serial data interface and a differential clock interface. The FPGA logic design module, the sending module, the receiving module and the clock processing module are all realized by the FPGA. The domestic FPGA platform selected in this embodiment is a double denier micro 7V690T series FPGA with 80 GTH high speed serial transceivers.
In the invention, the differential serial data interface is an optical fiber interface based on SerDes, and the serialized high-speed optical fiber data is operated.
In the invention, the clock management module is responsible for generating clock signals required by each module and managing the phase relation among the clocks. The clock source is from an externally supplied differential clock.
In the invention, the sending module and the receiving module are both composed of a PCS layer and a PMA layer, and the PCS layer has the following functions: parallel digital signal processing belongs to a logic layer and is mainly realized by FPGA logic. The PMA functions are: the serial-parallel conversion and simulation part belongs to a physical layer and is mainly realized by an FPGA built-in circuit.
As shown in fig. 1, in the transmitting module, the TX PCS layer includes: a coding module (TX gecarboxblock), a phase compensation FIFO, and a Polarity control module (TX Polarity) at the transmitting end. The TX PMA layer comprises: parallel/serial conversion module (PISO), transmit equalizer, and transmitter.
The encoding module provides an efficient combination of sync header and data for 64B/66B encoding while completing transmit data scrambling. The coding module comprises a transmission Gearbox (TX Gecarbox) and a Scrambler (Scrambler), wherein the Gecarbox is a Gearbox for realizing conversion between any data bit widths, and supports 2-byte, 4-byte and 8-byte interface definitions, and the transmission Gearbox (TX Gecarbox) in the embodiment realizes data bit width conversion from 8 bytes to 4 bytes, and the Scrambler (Scrambler) is completed by FPGA logic. The working process of the coding module in this embodiment is shown in fig. 2.
The phase compensation FIFO is used for rate and phase matching between the parallel clock domains between the TX PMA and the transmit TX PCS.
The polarity control module of the transmitting end is an optional module, and the function is driven to be high level from the structural user interface to reverse the data polarity. Some embodiments do not use the module.
The parallel/serial conversion module is responsible for converting parallel data inside the FPGA into serial data of the SerDes interface.
The purpose of the transmit equalizer is to compensate for the non-ideal characteristics of the channel, guarantee signal integrity, and thus support higher speed and longer range serial data transmission, including pre-equalizer (FFE-Forward Equalization), linear equalizer (linear equalizer), and decision feedback equalizer (Decision Feedback Equalizer, DFE). The transmission equalizer generally adopts an FFE structure and is responsible for compensating the damage of a channel to a signal.
As shown in fig. 1, in the receiving module, the RX PCS layer includes: decoding module (RX Gecarbox Block), elastic buffer FIFO and Polarity control module (RX Polarity) at receiving end. The RX PMA layer includes: serial/parallel conversion module (SIPO), clock data recovery module (CDR), receive equalizer and receiver.
The receiving equalizer of the receiving module adopts a DFE structure, is more suitable for the application scene of high-speed SerDes and is responsible for equalizing the channel loss.
The clock data recovery module (CDR) extracts clock and data from the data stream, captures the frequency of the data edge transitions as the data passes to obtain the clock frequency, and finds the optimal sampling point.
The serial/parallel conversion module is responsible for converting serial data of the SerDes interface into parallel data inside the FPGA.
The polarity control module of the receiving end is an optional module, and the function of the polarity control module is consistent with that of the sending end. This module is not used in this embodiment.
There are two different clock domains at the receiving end: a local clock domain and a clock domain recovered from the CDR. The elastic buffer FIFO is used for solving the difference of data of two different clock domains, matching the frequency and the phase between the two clock domains and completing clock correction and channel binding.
The decoding module performs effective separation of the synchronization header and the data for 64B/66B decoding, and simultaneously completes the descrambling of the transmitted data. The decoding module comprises a Descrambler (Descrambler) which is completed by FPGA logic and a receiving Gearbox (RX Gecarbox) which realizes data bit width conversion from 8 bytes to 4 bytes. The operation of the decoding module in this embodiment is shown in fig. 3.
In this embodiment, the user data bit width is set to 32 bits, the internal bit width is set to 32 bits, the transmission mode is small-end transmission, and polarity conversion is not required.
The characteristic polynomial of the scrambler for the 64B/66B codec of this embodiment is G (x) =x 58 +x 39 +1, the same polynomial is used for the descrambler. In this embodiment, in order to simplify the transmission and encoding process, the data packet does not include control information, and the synchronization header is generated according to whether the data is valid.
In this embodiment, a user-defined data format is adopted for transmission, and a data status flag txdatalink is set in user data, and in the data transmission process, if the data status is invalid (txdatalink=0), the part of data can be discarded, and the data is directly set to 32' hbbcbcbcbc without coding, so that the FPGA logic resource can be effectively saved. The synchronization header definition is shown in table 1:
TABLE 1
| TXDATAVALID | Sync | Data type | |
| 1 | 01 | Data valid | |
| 0 | 10 | Idle |
The coding and transmission process of the transmission data in this embodiment is as follows:
referring to fig. 1, the user interface data TXD is 32-bit custom fiber data, which is a data packet generated by the internal logic of the FPGA. Referring to fig. 2, two valid 32-bit interface DATA are encoded to obtain DATA D0-D7, the DATA D0-D7 are scrambled by a Scrambler (Scrambler) to obtain scrambled DATA S0-S7, a synchronization header (Sync header) is combined with the scrambled DATA to generate a 66-bit transmission block, the 66-bit transmission block is processed by a gecarbox to obtain 32-bit encoded DATA tx_data, the 32-bit encoded DATA tx_data is sent to an internal interface of a PCS layer of a transmitting module, and then, referring to fig. 1, the high-speed serial bit stream containing clock information is obtained by parallel-serial conversion after phase compensation FIFO, and is transmitted to an external SerDes interface by a transmitter after being transmitted to an equalizer.
The decoding and transmission process of the received data in this embodiment is as follows:
referring to fig. 1, a receiver receives a high-speed serial data stream of a SerDes interface, a clock data recovery module recovers effective data and a clock signal after the high-speed serial data stream passes through a receiving equalizer, the effective data and the clock signal are converted into 32-bit parallel data by a serial/parallel conversion module under the driving of the clock signal, the 32-bit parallel data are sent to a PCS layer internal interface of the receiving module through an elastic buffer FIFO, referring to fig. 3, the internal interface data and a synchronization header are subjected to data synchronization by a gecarbox, and then the data descrambling is performed through a descrambler (desrmbler), and 64B/66B decoding is performed, so that separated 32-bit user interface data and the synchronization header are obtained, and the separated 32-bit user interface data and the synchronization header are sent to an FPGA internal logic end for data processing and interaction.
The above embodiments only represent one implementation of the present invention, and the present invention is also applicable to other communication application scenarios based on the SerDes interface protocol and other data formats.
The technical scheme provided by the invention realizes high-speed SerDes data communication on a domestic FPGA platform, and meets the application requirement;
compared with the 8B/10B coding scheme adopted in the prior art, the 64B/66B coding mode adopted in the invention can effectively improve the data transmission efficiency, and has more advantages in a high-speed data transmission application environment;
the invention simplifies the 64B/66B coding design, realizes related functions by the IP core and the custom logic together, and effectively saves cost and development period.
The foregoing is merely a preferred embodiment of the present invention, and it should be noted that modifications and variations could be made by those skilled in the art without departing from the technical principles of the present invention, and such modifications and variations should also be regarded as being within the scope of the invention.
Claims (10)
1. A SerDes high-speed communication system based on domestic FPGA is characterized by comprising an FPGA logic design module, a sending module, a receiving module, a clock management module, a differential serial data interface and a differential clock interface; the FPGA logic design module, the sending module, the receiving module and the clock processing module are all realized by the FPGA;
the differential serial data interface is an optical fiber interface based on SerDes, and is operated by serialized high-speed optical fiber data;
the clock management module is responsible for generating clock signals required by each module and managing the phase relation among the clocks;
the sending module and the receiving module are both composed of a PCS layer and a PMA layer;
in the transmitting module, the TX PCS layer includes: a coding module (TX Gecarbox Block), a phase compensation FIFO and a Polarity control module (TX Polarity) at the transmitting end; the TX PMA layer comprises: a parallel/serial conversion module (PISO), a transmit equalizer, and a transmitter;
the coding module provides effective combination of the synchronous head and the data for 64B/66B coding, and simultaneously finishes sending data scrambling codes;
the phase compensation FIFO is used for rate and phase matching between the parallel clock domains between the TX PMA and the transmit TX PCS;
the polarity control module of the transmitting end is an optional module and is used for driving to be high level from the structural user interface so as to reverse the data polarity;
the parallel/serial conversion module is responsible for converting parallel data in the FPGA into serial data of a SerDes interface;
the function of the transmit equalizer is to compensate for the non-ideal characteristics of the channel;
in the receiving module, the RX PCS layer includes: decoding module (RX Gecarbox Block), elastic buffer FIFO and Polarity control module (RX Polarity) of receiving end, RX PMA layer includes: a serial/parallel conversion module (SIPO), a clock data recovery module (CDR), a reception equalizer, and a receiver;
the receiving equalizer of the receiving module is responsible for equalizing channel loss;
the clock data recovery module (CDR) extracts clock and data from the data stream, captures the frequency of data edge jump when the data passes through so as to obtain clock frequency, and finds the optimal sampling point;
the serial/parallel conversion module is responsible for converting serial data of the SerDes interface into parallel data in the FPGA;
the polarity control module of the receiving end is an optional module and is used for driving to be high level from the structural user interface so as to reverse the data polarity;
there are two different clock domains at the receiving end: the elastic buffer FIFO is used for solving the difference of data of two different clock domains, matching the frequency and the phase between the two clock domains and completing clock correction and channel binding;
the decoding module performs effective separation of the synchronization header and the data for 64B/66B decoding, and simultaneously completes the descrambling of the transmitted data.
2. The SerDes high-speed communication system based on a domestic FPGA of claim 1, wherein the PCS layer functions as: parallel digital signal processing belongs to a logic layer and is realized by FPGA logic.
3. The SerDes high-speed communication system based on a domestic FPGA of claim 1, wherein the PMA functions as: the serial-parallel conversion and simulation part belongs to a physical layer and is realized by an FPGA built-in circuit.
4. The SerDes high-speed communication system based on a domestic FPGA of claim 1, wherein the encoding module comprises a transmission Gearbox (TX gecarbox) that implements 8-byte to 4-byte data bit width conversion and a Scrambler (Scrambler) that is implemented by the FPGA logic.
5. The SerDes high-speed communication system based on domestic FPGA of claim 1, wherein the transmission equalizer adopts a pre-equalizer (Feed-Forward Equalization, FFE) structure in charge of compensating for channel impairments to signals.
6. The SerDes high-speed communication system based on domestic FPGA of claim 1, wherein a receiving equalizer of the receiving module adopts a decision feedback equalizer (Decision Feedback Equalizer, DFE) structure.
7. The SerDes high-speed communication system based on a domestic FPGA of claim 1, wherein the decoding module comprises a Descrambler (descaler) and a receiving Gearbox (RX gecarbox), the Descrambler (descaler) being implemented by FPGA logic, the receiving Gearbox (RX gecarbox) implementing a data bit width conversion of 8 bytes to 4 bytes.
8. The SerDes high-speed communication system based on domestic FPGA according to any of claims 1-7, wherein the encoding and transmission process of the transmission data is: the user interface data TXD is 32-bit custom optical fiber data and is a data packet generated by the internal logic of the FPGA; two effective 32-bit interface DATA are coded to obtain DATA D0-D7, the DATA D0-D7 are scrambled by a Scrambler (Scrambler) to obtain scrambled DATA S0-S7, a synchronization head (Sync header) is combined with the scrambled DATA to generate a 66-bit transmission block, the 66-bit transmission block is processed by a Gecarbox to obtain 32-bit coded DATA TX_DATA, the 32-bit coded DATA TX_DATA is sent to an internal interface of a PCS layer of a transmitting module, parallel-serial conversion is carried out after phase compensation FIFO to obtain a high-speed serial bit stream containing clock information, and the high-speed serial bit stream is transmitted to an external SerDes interface by a transmitter after a transmitting equalizer;
the decoding and transmission process of the received data is as follows: the receiver receives the high-speed serial data stream of the SerDes interface, the effective data and clock signals are recovered by the clock data recovery module after passing through the receiving equalizer, the data are converted into 32-bit parallel data by the serial/parallel conversion module under the drive of the clock signals, the 32-bit parallel data are sent to the PCS layer internal interface of the receiving module through the elastic buffer FIFO, the internal interface data and the synchronous head are subjected to data synchronization by the Gecarbox, then the data descrambling is carried out through the descrambler (Descrubler), the 64B/66B decoding is carried out, and the separated 32-bit user interface data and the synchronous head are obtained and sent to the FPGA internal logic end for data processing and interaction.
9. The SerDes high-speed communication system according to claim 8, wherein the characteristic polynomial of the scrambler of the 64B/66B codec is G (x) =x 58 +x 39 +1, the descrambler uses the same polynomial; the data packet does not contain control information, and the synchronization header is generated according to whether the data is valid or not.
10. The SerDes high-speed communication system based on domestic FPGA as claimed in claim 8, wherein the user data has a bit width of 32 bits, an internal bit width of 32 bits, is transmitted in a small-end manner, and does not need polarity conversion, a data status flag txdataalid is set in the user data, and during the data transmission process, if the data status is invalid, i.e. txdataalid=0, the part of data can be discarded, the coding is not performed, and the data is directly set as 32' hbbcbcbcbc.
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| CN117294751B (en) * | 2023-11-24 | 2024-02-06 | 浙江大学 | Transmission system, transmission method, communication equipment and medium of JESD204C interface compatible with SIP architecture |
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