CN116313854A - Chip packaging structure and preparation method thereof - Google Patents

Chip packaging structure and preparation method thereof Download PDF

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Publication number
CN116313854A
CN116313854A CN202310179258.1A CN202310179258A CN116313854A CN 116313854 A CN116313854 A CN 116313854A CN 202310179258 A CN202310179258 A CN 202310179258A CN 116313854 A CN116313854 A CN 116313854A
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chip
copper
substrate
interconnection layer
silver
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CN202310179258.1A
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Chinese (zh)
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刘旭
叶怀宇
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Nayu Semiconductor Materials Ningbo Co ltd
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Nayu Semiconductor Materials Ningbo Co ltd
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Priority to CN202310179258.1A priority Critical patent/CN116313854A/en
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    • H01L2224/45147—Copper (Cu) as principal constituent

Abstract

The invention relates to a chip packaging structure and a preparation method thereof; paving paste containing micro-nano metal particles on a specific position of a substrate to form a patch layer; mounting a chip on the patch layer, and interconnecting the chip and the substrate by adopting a sintering process; paving paste containing metal micro-nano particles on one surface of a chip far away from a substrate to form a pre-interconnection layer, and sintering the pre-interconnection layer by adopting a sintering process to ensure that the layer is interconnected with the chip; preparing a lead on the pre-interconnection layer to obtain a chip packaging structure; the technical problems that the chip is scrapped due to the fact that the chip is extremely easy to damage when copper wire bonding is directly carried out on the surface of the chip are solved through the improvement of the packaging structure, the heat conducting performance and the reliability of the existing aluminum wire are poor, the hardness of the existing copper wire is high, and the bonding pressure required during bonding is high.

Description

Chip packaging structure and preparation method thereof
Technical Field
The invention relates to the technical field of chip packaging structures, in particular to a chip packaging structure and a preparation method thereof.
Background
The main application of the semiconductor chip is a technology for converting input direct current or alternating current energy into a required electric energy form and outputting the electric energy, and a proper and non-interference environment is required as an important component of energy conversion. Therefore, there is a need for structures involving reasonable packaging to ensure power supply, signal distribution, good heat dissipation channels for the conductor chips, and reliable mechanical support and environmental protection.
The power supply and signal distribution of the chip are mainly realized through a Wire Bonding process, which is also called a Wire Bonding process (Wire Bonding), and refers to that when the semiconductor device is packaged and integrated into a circuit, the power supply and the input/output electrode of the signal of the chip are led out to a conductive substrate or a lead frame to realize electrical connection. At present, with the development of power electronic technology in the fields of new energy automobiles, high-speed rails, communication and the like, chips are developed to higher power density, switching frequency and chip size reduction, and higher requirements are put on packaging technology.
For the connection of the chip and the substrate, the metal copper has the advantages of higher electric conduction, heat conduction, good mechanical property and the like, and compared with chip interconnection materials such as gold, silver and the like, the copper resource is rich, and the cost is lower. Therefore, chip site sintering interconnection by micro-nano copper is currently considered as the best-looking chip interconnection technology according to the "size effect". For the connection between the chip and the lead frame, the overcurrent capability of the bonding wire is critical, and when the aluminum wire bonding is adopted, the overcurrent capability is relatively weak, and the risk of fusing the bonding wire due to overcurrent exists. Compared with the aluminum wire, the bonding copper wire has strong conductivity and high hardness, and is an ideal chip bonding material.
However, at present, since the surface of the power chip is generally treated by an aluminized layer, bonding is still generally realized by aluminum wires. Because the wire hardness of the aluminum wire is large, the bonding pressure required in bonding is large, and the chip is extremely easy to damage and scrap when copper wire bonding is directly performed on the surface of the chip.
Accordingly, there is an urgent need to provide a chip package structure and a method for manufacturing the same.
Disclosure of Invention
The invention aims to provide a packaging structure and a preparation method thereof, and solves the technical problems that the wire hardness of the existing aluminum wire is high, the bonding pressure required during bonding is high, and the chip is damaged easily when copper wire bonding is directly performed on the surface of the chip, so that the chip is scrapped.
The invention provides a preparation method of a chip packaging structure, which comprises the following preparation steps of
Paving paste containing micro-nano metal particles on a specific position of a substrate to form a patch layer;
mounting a chip on the patch layer, and interconnecting the chip and the substrate by adopting a sintering process;
paving paste containing micro-nano metal particles on one surface of a chip far away from a substrate to form a pre-interconnection layer, and sintering the pre-interconnection layer by adopting a sintering process to enable the pre-interconnection layer to be interconnected with the chip;
preparing a lead on the pre-interconnection layer to obtain a chip packaging structure;
or alternatively
Paving paste containing micro-nano metal particles on one surface of a chip to form a pre-interconnection layer, and sintering the pre-interconnection layer by adopting a sintering process to enable the pre-interconnection layer to be interconnected with the chip;
paving paste containing micro-nano metal particles on a specific position of a substrate to form a patch layer;
mounting the chip with the pre-interconnection layer on the patch layer, and interconnecting the chip with the pre-interconnection layer with the substrate by adopting a sintering process;
preparing a lead on the pre-interconnection layer to obtain a chip packaging structure;
or alternatively
Paving paste containing micro-nano metal particles on a specific position of a substrate to form a patch layer;
mounting a chip on the patch layer, paving paste containing micro-nano metal particles on one surface of the chip far away from the substrate to form a pre-interconnection layer, and sintering the pre-interconnection layer, the chip and the patch layer by adopting a sintering process to ensure that the chip is interconnected with the substrate;
and preparing a lead on the pre-interconnection layer to obtain the chip packaging structure.
Preferably, the paste containing micro-nano metal particles is a mixture of metal nano particles and an organic carrier; the organic carrier comprises resin, alcohol solvent, dispersant and surfactant.
Preferably, the alcohol solvent is at least one of terpineol, ethylene glycol, isopropanol, dipropylene glycol or n-butanol.
Preferably, the particle diameter (D) of the metal nanoparticles is 1 nm.ltoreq.D.ltoreq.100. Mu.m.
Preferably, the metal nanoparticles are at least one of copper, gold, palladium, silver, aluminum, silver-palladium alloy, gold-palladium alloy, copper-silver alloy, copper-indium alloy, copper-silver-nickel alloy, copper-silver-tin alloy, copper-silver-titanium alloy or copper-aluminum alloy, silver-coated copper, tin-coated copper, organic-coated copper or organic-coated silver particles.
Preferably, the metal nanoparticles are at least one of copper, copper-silver alloy or silver particles.
Preferably, the metal nanoparticles are at least one of spherical, spheroidal, platelet-shaped, dendritic, linear, triangular, or irregular in shape.
Preferably, the paste containing the micro-nano metal particles is laid on the substrate or the chip in a manner including one of screen printing, steel screen printing, coating, dispensing or spraying.
Preferably, the sintering process includes pre-sintering and formal sintering;
the presintering process is carried out in a vacuum or non-vacuum state, the temperature is 100-150 ℃, the heat preservation time is 30s-90min, and the gas in the non-vacuum state comprises at least one of air, nitrogen, hydrogen-argon mixed gas or formic acid atmosphere;
the formal sintering process is carried out in a vacuum or non-vacuum state, the temperature is 200-300 ℃, the heat preservation time is 30s-30min, the auxiliary pressure is 0MPa-30MPa, and the gas comprises at least one of air, nitrogen, argon, hydrogen-argon mixed gas or formic acid in the non-vacuum state;
preferably, the mode of preparing the lead wire is that an ultrasonic welding wire bonding machine is adopted for interconnection so as to realize ohmic connection of the chip and the substrate;
preferably, the lead is pure copper wire, pure copper strip, pure copper foil, copper electrode, silver-coated copper wire, aluminum copper-coated wire and aluminum wire 、 One of aluminum silicon wire, silver wire or gold wire;
preferably, the lead is one of pure copper wires, pure copper strips, pure copper foils, copper electrodes, silver-coated copper wires and aluminum-copper-coated wires;
preferably, the substrate comprises a pure copper substrate, a direct copper clad ceramic substrate DBC, an active metal braze clad copper substrate AMB, a copper lead frame material or an insulated metal substrate.
The invention also provides a chip packaging structure obtained based on the preparation method of the chip packaging structure, which comprises a substrate, wherein a patch layer is arranged on the substrate, a chip is arranged on the patch layer, a pre-interconnection layer is arranged on the chip, and a lead is arranged on the pre-interconnection layer;
the patch layer and the pre-interconnection layer are made of paste containing micro-nano metal particles.
Compared with the prior art, the chip packaging structure and the preparation method thereof provided by the invention have the following steps:
1. according to the preparation method of the chip packaging structure, the paste containing the micro-nano metal particles is applied to the substrate to form the patch layer, then the chip is attached, after sintering, interconnection between the chip and the substrate is realized, the paste containing the micro-nano metal particles is applied to the upper end face of the chip, after sintering, a pre-interconnection layer is formed, and then the lead wire and the chip are interconnected through a wire bonding process.
2. According to the preparation method of the chip packaging structure, the material of the patch layer and the material of the pre-interconnection layer are the same, and the expansion coefficients are the same, so that the packaging structure has higher stability.
3. According to the preparation method of the chip packaging structure, the micro-nano metal material sintering technology is adopted to realize the adhesion of the chip and the metal ceramic substrate, the bonding capacity is strong, and the layering phenomenon is not easy to occur during the high-low temperature cyclic operation.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a patch layer disposed on a substrate according to a first embodiment;
fig. 2 is a schematic structural diagram of a chip disposed on a patch layer according to the first embodiment;
FIG. 3 is a schematic diagram of a structure of a chip with a pre-interconnection layer according to the first embodiment;
FIG. 4 is a schematic structural diagram of a chip package structure according to a first embodiment;
FIG. 5 is a schematic diagram of a structure of a chip with a pre-interconnection layer according to a second embodiment;
fig. 6 is a schematic structural diagram of a patch layer disposed on a substrate in the second embodiment;
FIG. 7 is a schematic diagram of a chip and pre-interconnect layer together disposed on a patch layer according to the second embodiment;
fig. 8 is a schematic structural diagram of a chip package structure according to a second embodiment;
fig. 9 is a schematic structural diagram of a patch layer disposed on a substrate according to the third embodiment;
fig. 10 is a schematic structural diagram of a chip and a pre-interconnection layer sequentially disposed on the patch layer in the third embodiment;
fig. 11 is a schematic structural diagram of a chip package structure according to a third embodiment;
reference numerals illustrate:
example 1
101. A substrate; 102. a patch layer; 103. a chip; 104. a pre-interconnect layer; 105. a lead wire;
example two
201. A substrate; 202. a patch layer; 203. a chip; 204. a pre-interconnect layer; 205. a lead wire;
example III
301. A substrate; 302. a patch layer; 303. a chip; 304. a pre-interconnect layer; 305. a lead wire;
Detailed Description
The following description of the embodiments of the present invention will be made apparent and fully in view of the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Example 1
As shown in fig. 1, 2, 3 and 4, the method for manufacturing a chip package structure provided in this embodiment includes the following manufacturing steps:
s11) paving paste containing micro-nano metal particles on a specific position of a substrate to form a patch layer;
s12) mounting a chip on the patch layer, and interconnecting the chip and the substrate by adopting a sintering process;
s13) paving paste containing micro-nano metal particles on one surface of the chip far away from the substrate to form a pre-interconnection layer, and sintering the pre-interconnection layer by adopting a sintering process to enable the pre-interconnection layer to be interconnected with the chip;
s14) preparing leads on the pre-interconnection layer to obtain a chip package structure.
According to the invention, paste containing micro-nano metal particles is applied on a substrate to form a patch layer, then a chip is attached and sintered, interconnection between the chip and the substrate is realized, paste containing micro-nano metal particles is applied on the upper end surface of the chip, a pre-interconnection layer is formed after sintering, and then a lead wire is interconnected with the chip through a wire bonding process, so that the overcurrent capacity of bonding materials is greatly improved, and the reliability of a packaging structure is ensured; secondly, as the material of the patch layer and the material of the pre-interconnection layer are the same, the expansion coefficient is the same, so that the packaging structure has higher stability.
According to the preparation method of the chip packaging structure, the micro-nano metal material sintering technology is adopted to realize the adhesion of the chip and the metal ceramic substrate, the bonding capacity is strong, and the layering phenomenon is not easy to occur during the high-low temperature cyclic operation.
The paste containing micro-nano metal particles in the embodiment is a mixture of metal nano particles and an organic carrier; the organic carrier comprises resin, alcohol solvent, dispersant and surfactant.
Specifically, the alcohol solvent is at least one of terpineol, ethylene glycol, isopropanol, dipropylene glycol or n-butanol; the resin is at least one of ethyl cellulose, methyl cellulose or epoxy resin; the surfactant is at least one of citric acid or isopropanol; the dispersing agent is acacia.
In some embodiments, the organic vehicle specifically includes a solvent (terpineol 15%, ethylene glycol 3%, isopropanol 1% and dipropylene glycol 2%), a resin (methylcellulose 1.5%), a surfactant (citric acid 0.3% and isopropanol 0.2%), and a dispersant (acacia 0.5%) (each percentage described above is a mass content and is a percentage of the total mass of the paste material). In some embodiments, the organic vehicle specifically includes a solvent (terpineol 15%, ethylene glycol 3%, isopropanol 1%, dipropylene glycol 1%, n-butanol 1%), a resin (ethylcellulose 1.5%), a surfactant (citric acid 0.5%), and a dispersant (acacia 0.5%) (each percentage described above is a mass content and is a percentage of the total mass of the paste material).
The particle diameter (D) of the metal nanoparticles of this example was 1 nm.ltoreq.D.ltoreq.100. Mu.m.
The metal nano particles in this embodiment are at least one of copper, gold, palladium, silver, aluminum, silver-palladium alloy, gold-palladium alloy, copper-silver alloy, copper-indium alloy, copper-silver-nickel alloy, copper-silver-tin alloy, copper-silver-titanium alloy or copper-aluminum alloy, silver-coated copper, tin-coated copper, organic-coated copper or organic-coated silver particles.
Further, the metal nano-particles are at least one of copper, copper-silver alloy or silver particles.
Further, the metal nanoparticle is copper.
Further, the metal nano-particles are copper-silver alloy.
Further, the metal nanoparticles are copper and silver particles.
Further, the metal nanoparticles are at least one of spherical, spheroidal, platelet-shaped, dendritic, linear, triangular, or irregular in shape.
Further, the paste containing the micro-nano metal particles is laid on the substrate or the chip in a mode of one of screen printing, steel screen printing, coating, dispensing or spraying.
In some embodiments, screen printing is preferred.
Further, the sintering process includes pre-sintering and formal sintering; sintering treatment is carried out in a drying oven.
The presintering process is carried out in a vacuum or non-vacuum state, the temperature is 100-150 ℃, the heat preservation time is 30s-90min, and the gas in the non-vacuum state comprises at least one of air, nitrogen, hydrogen-argon mixed gas or formic acid atmosphere; the main sintering process is carried out in a vacuum or non-vacuum state, the temperature is 200-300 ℃, the heat preservation time is 30s-30min, the auxiliary pressure is 0MPa-30MPa, and the gas comprises at least one of air, nitrogen, argon, hydrogen-argon mixed gas or formic acid in the non-vacuum state.
In some embodiments, the pre-sintering process is performed under vacuum at a temperature of 120 ℃ for 80 minutes; the formal sintering process is carried out under vacuum at 250 ℃, the heat preservation time is 20min, and the auxiliary pressure is 15MPa.
In some embodiments, the pre-sintering process is performed in a non-vacuum state at a temperature of 120 ℃ for 80 minutes, wherein the gas comprises at least one of air, nitrogen, a hydrogen argon mixture, or a formic acid atmosphere; the main sintering process is carried out in a non-vacuum state, the temperature is 250 ℃, the heat preservation time is 20min, the auxiliary pressure is 15MPa, and the gas in the non-vacuum state comprises at least one of air, nitrogen, argon, hydrogen-argon mixed gas or formic acid.
Further, the mode of preparing the lead wire is that an ultrasonic welding wire bonding machine is adopted for interconnection so as to realize ohmic connection of the chip and the substrate;
further, the lead is one of pure copper wire, pure copper strip, pure copper foil, copper electrode, silver-coated copper wire, aluminum-copper coated wire, aluminum wire or aluminum-silicon wire.
In some embodiments, the further lead is preferably one of pure copper wire, pure copper tape, pure copper foil, copper electrode, silver coated copper wire.
Compared with the existing aluminum wire serving as a lead (poor in heat conduction performance and reliability), the lead adopts the copper-containing lead, so that the overcurrent capacity of bonding connection materials is greatly improved, and the reliability of a packaging structure is ensured.
Furthermore, due to the arrangement of the preset interconnection layer, the technical problem that the chip is scrapped due to the fact that copper wires are used as leads (the hardness of the copper wires is high) and the bonding pressure required during bonding is high can be avoided, and the chip is extremely easy to damage when the copper wire bonding is directly carried out on the surface of the chip. In addition, through using the sintering copper material below the chip, copper base plate, and the design of "all copper interconnection" of sintering copper material, copper lead wire on the chip upper surface simultaneously, the coefficient of thermal expansion mismatch degree in the packaging structure can be reduced to reduce the expend with heat and contract with cold and thermal stress in the chip course of working, finally promote overall packaging structure's reliability.
Further, the substrate includes a pure copper substrate, a direct copper clad ceramic substrate DBC, an active metal braze clad copper substrate AMB, a copper lead frame material, or an insulated metal substrate.
The chip packaging structure comprises a substrate, wherein a patch layer is arranged on the substrate, a chip is arranged on the patch layer, a pre-interconnection layer is arranged on the chip, and a lead is arranged on the pre-interconnection layer;
the patch layer and the pre-interconnection layer are made of paste containing micro-nano metal particles.
The chip of the embodiment is a power chip, for example, an uncontrollable device chip power rectifier diode, a schottky diode (SBD), a Fast Recovery Diode (FRD), a semi-controllable device chip thyristor (SCR), a bidirectional Thyristor (TRIAC) which are prepared by using silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN), silicon carbide (SiC), and zinc selenide (ZnSe) as raw materials; for another example, the fully controlled device chip is an Insulated Gate Bipolar Transistor (IGBT), a power field effect transistor (MOSFET), a gate turn-off thyristor (GTO), a power transistor (GTR), or a Bipolar Junction Transistor (BJT).
The chip packaging structure of the invention is characterized in that the whole preparation process can select the substrate, the patch layer, the chip, the pre-interconnection layer and the lead according to specific requirements, and the chip packaging structure is not limited to the selection of a specific material.
The invention is innovative in that the paste containing metal nano-particles is sintered after being covered, so as to provide high-strength connection, high electric conduction and heat conduction paths for chips, and can be used as a circuit layer for interconnecting active devices and passive devices; meanwhile, the paste expansion coefficients of the patch layer and the pre-interconnection layer which both adopt metal nano particles are the same, so that the packaging structure has higher stability.
Example two
The present embodiment is further improved based on the first embodiment, and the disclosure of the first embodiment is not repeated.
As shown in fig. 5, 6, 7 and 8, the steps are as follows:
s21) paving paste containing micro-nano metal particles on one surface of the chip 203 to form a pre-interconnection layer 204, and sintering the pre-interconnection layer by adopting a sintering process to enable the pre-interconnection layer 204 to be interconnected with the chip 203;
s22) paving paste containing micro-nano metal particles on a specific position of the substrate 201 to form a patch layer 202;
s23) mounting the chip 203 having the pre-interconnection layer 204 on the patch layer 202, and interconnecting the chip having the pre-interconnection layer with the substrate by a sintering process;
s24) preparing a lead 205 on the pre-interconnection layer 204, and obtaining a chip package structure.
Example III
The present embodiment is further improved based on the first embodiment, and the disclosure of the first embodiment is not repeated.
S31) paving paste containing micro-nano metal particles on a specific position of the substrate 301 to form a patch layer 302;
s32) mounting a chip 303 on the patch layer 302, paving paste containing micro-nano metal particles on one surface of the chip 303 far away from the substrate to form a pre-interconnection layer 304, and sintering the pre-interconnection layer 304, the chip 303 and the patch layer 302 by adopting a sintering process to ensure that the chip 303 is interconnected with the substrate 301;
s33) preparing the leads 305 on the pre-interconnection layer 304, and obtaining the chip package structure.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims (10)

1. A preparation method of a chip packaging structure is characterized by comprising the following steps: the manufacturing steps are as follows
Paving paste containing micro-nano metal particles on a specific position of a substrate to form a patch layer;
mounting a chip on the patch layer, and interconnecting the chip and the substrate by adopting a sintering process;
paving paste containing micro-nano metal particles on one surface of a chip far away from a substrate to form a pre-interconnection layer, and sintering the pre-interconnection layer by adopting a sintering process to enable the pre-interconnection layer to be interconnected with the chip;
preparing a lead on the pre-interconnection layer to obtain a chip packaging structure;
or alternatively
Paving paste containing micro-nano metal particles on one surface of a chip to form a pre-interconnection layer, and sintering the pre-interconnection layer by adopting a sintering process to enable the pre-interconnection layer to be interconnected with the chip;
paving paste containing micro-nano metal particles on a specific position of a substrate to form a patch layer;
mounting the chip with the pre-interconnection layer on the patch layer, and interconnecting the chip with the pre-interconnection layer with the substrate by adopting a sintering process;
preparing a lead on the pre-interconnection layer to obtain a chip packaging structure;
or alternatively
Paving paste containing micro-nano metal particles on a specific position of a substrate to form a patch layer;
mounting a chip on the patch layer, paving paste containing micro-nano metal particles on one surface of the chip far away from the substrate to form a pre-interconnection layer, and sintering the pre-interconnection layer, the chip and the patch layer by adopting a sintering process to ensure that the chip is interconnected with the substrate;
and preparing a lead on the pre-interconnection layer to obtain the chip packaging structure.
2. The method for manufacturing a chip package structure according to claim 1, wherein: the paste containing micro-nano metal particles is a mixture of metal nano particles and an organic carrier; the organic carrier comprises resin, alcohol solvent, dispersant and surfactant.
3. The method for manufacturing a chip package structure according to claim 2, wherein: the alcohol solvent is at least one of terpineol, ethylene glycol, isopropanol, dipropylene glycol or n-butanol.
4. The method for manufacturing a chip package structure according to claim 3, wherein: the particle diameter (D) of the metal nano particles is more than or equal to 1nm and less than or equal to 100 mu m.
5. The method for manufacturing a chip package structure according to claim 4, wherein: the metal nano particles are at least one of copper, gold, palladium, silver, aluminum, silver-palladium alloy, gold-palladium alloy, copper-silver alloy, copper-indium alloy, copper-silver-nickel alloy, copper-silver-tin alloy, copper-silver-titanium alloy or copper-aluminum alloy, silver-coated copper, tin-coated copper, organic-coated copper or organic-coated silver particles.
6. The method for manufacturing a chip package according to claim 5, wherein: the metal nano particles are at least one of copper, copper-silver alloy or silver particles.
7. The method for manufacturing a chip package according to claim 6, wherein: the metal nanoparticles are at least one of spherical, spheroidal, platelet-shaped, dendritic, linear, triangular, or irregular.
8. The method for manufacturing a chip package according to claim 7, wherein: the paste containing the micro-nano metal particles is paved on the substrate or the chip in a mode of one of screen printing, steel screen printing, coating, dispensing or spraying.
9. The method for manufacturing a chip package structure according to claim 8, wherein: the sintering process comprises pre-sintering and formal sintering;
the presintering process is carried out in a vacuum or non-vacuum state, the temperature is 100-150 ℃, the heat preservation time is 30s-90min, and the gas in the non-vacuum state comprises at least one of air, nitrogen, hydrogen-argon mixed gas or formic acid atmosphere;
the formal sintering process is carried out in a vacuum or non-vacuum state, the temperature is 200-300 ℃, the heat preservation time is 30s-30min, the auxiliary pressure is 0MPa-30MPa, and the gas comprises at least one of air, nitrogen, argon, hydrogen-argon mixed gas or formic acid in the non-vacuum state;
preferably, the mode of preparing the lead wire is that an ultrasonic welding wire bonding machine is adopted for interconnection so as to realize ohmic connection of the chip and the substrate;
preferably, the lead is pure copper wire, pure copper strip, pure copper foil, copper electrode, silver-coated copper wire, aluminum copper-coated wire and aluminum wire 、 One of aluminum silicon wire, silver wire or gold wire;
preferably, the lead is one of pure copper wires, pure copper strips, pure copper foils, copper electrodes, silver-coated copper wires and aluminum-copper-coated wires;
preferably, the substrate comprises a pure copper substrate, a direct copper clad ceramic substrate DBC, an active metal braze clad copper substrate AMB, a copper lead frame material or an insulated metal substrate.
10. A chip package structure obtained based on the method for manufacturing a chip package structure according to any one of claims 1 to 9, characterized in that: the chip is provided with a pre-interconnection layer, and leads are arranged on the pre-interconnection layer;
the patch layer and the pre-interconnection layer are made of paste containing micro-nano metal particles.
CN202310179258.1A 2023-02-20 2023-02-20 Chip packaging structure and preparation method thereof Withdrawn CN116313854A (en)

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CN111490027A (en) * 2020-03-19 2020-08-04 深圳第三代半导体研究院 Framework support metal film, preparation method and sintering method
CN111933603A (en) * 2020-06-28 2020-11-13 深圳第三代半导体研究院 Semiconductor chip packaging structure and preparation method thereof
CN114101661A (en) * 2021-11-25 2022-03-01 重庆大学 Preparation method of mixed slurry filled with micro-nano metal particles, product and application thereof

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CN111490027A (en) * 2020-03-19 2020-08-04 深圳第三代半导体研究院 Framework support metal film, preparation method and sintering method
CN111933603A (en) * 2020-06-28 2020-11-13 深圳第三代半导体研究院 Semiconductor chip packaging structure and preparation method thereof
CN114101661A (en) * 2021-11-25 2022-03-01 重庆大学 Preparation method of mixed slurry filled with micro-nano metal particles, product and application thereof

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Application publication date: 20230623