CN116313519A - Preparation method of internal electrode high-precision stacked chip type multilayer ceramic capacitor - Google Patents

Preparation method of internal electrode high-precision stacked chip type multilayer ceramic capacitor Download PDF

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Publication number
CN116313519A
CN116313519A CN202310121545.7A CN202310121545A CN116313519A CN 116313519 A CN116313519 A CN 116313519A CN 202310121545 A CN202310121545 A CN 202310121545A CN 116313519 A CN116313519 A CN 116313519A
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China
Prior art keywords
wall
layer
cutting
printed
ceramic capacitor
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CN202310121545.7A
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Chinese (zh)
Inventor
马艳红
孙健
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Chaozhou Three Circle Group Co Ltd
Nanchong Three Circle Electronics Co Ltd
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Chaozhou Three Circle Group Co Ltd
Nanchong Three Circle Electronics Co Ltd
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Priority to CN202310121545.7A priority Critical patent/CN116313519A/en
Publication of CN116313519A publication Critical patent/CN116313519A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/30—Stacked capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/005—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/018—Dielectrics
    • H01G4/06—Solid dielectrics
    • H01G4/08—Inorganic dielectrics
    • H01G4/12—Ceramic dielectrics
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
    • Y02E60/13—Energy storage using capacitors

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

The invention discloses a preparation method of a chip type multilayer ceramic capacitor with high-precision stacked internal electrodes, which comprises the following steps: the multilayer printed sheet printed with the internal electrodes and the dielectrics is peeled off from the PET film by utilizing the upper gold type; four inner walls and four outer walls are arranged around each layer of printing sheet inner electrode, an upper inner wall and a lower inner wall are arranged in parallel with the long axis direction of the inner electrode, an upper outer wall is arranged at a certain distance from the outer side of the upper inner wall, and a lower outer wall is arranged at a certain distance from the outer side of the lower inner wall; a left inner wall and a right inner wall are arranged in parallel with the short axis direction of the inner electrode, a left outer wall is arranged outside the left inner wall at a certain distance, and a right outer wall is arranged outside the right inner wall at a certain distance; the multi-layer printing sheets are staggered and stacked to cover the upper protective cover and the lower protective cover; carrying out isostatic pressing on the multilayer printing sheet covered with the upper protective cover and the lower protective cover; cutting at preset cutting points of the printed sheets to obtain stacked multilayer printed sheets, wherein the method can be widely applied to the field of chip multilayer ceramic capacitors.

Description

Preparation method of internal electrode high-precision stacked chip type multilayer ceramic capacitor
Technical Field
The invention relates to the technical field of chip multilayer ceramic capacitors, in particular to a preparation method of a chip multilayer ceramic capacitor with high-precision stacked internal electrodes.
Background
Chip multilayer ceramic capacitor (Multi-layer Ceramic Capacitor, MLCC for short) is one of the commonly used electronic components, plays an important role in blocking direct current, communicating with alternating current and storing energy in circuits, and is widely applied to household appliances, mobile phones, computers and other intelligent control circuits. In recent years, MLCCs are increasingly thinner and multilayered to meet technological development and market demands. One of the biggest problems encountered on the development roads of MLCC thinning and multilayering is the problem of stacking precision, for products with electrode layers more than or equal to 100 layers, stacking pressure is mainly concentrated on the part printed with an inner electrode because the electrode block is higher than the exposed dielectric by one layer of electrode thickness in the stacking process, the non-printed inner electrode part is not tightly pressed, the upper golden edge is not tightly pressed, and the phenomenon of folding is easily caused by lifting and turning over, so that bad occurrence is caused; in addition, because a certain thickness exists after the bar blocks of the product are stacked, a certain pressure exists on the side surface in the isostatic pressing process, and because the accumulated height of the stacked electrode blocks is larger than the exposed dielectric medium position, the stacked non-compact position is easy to shrink and deform to different degrees under the action of force in the hydrostatic pressure process, and the stacked non-compact position is reacted to the corner position of the chip type multilayer ceramic capacitor to distort and deform, so that the cutting qualification rate of the chip type multilayer ceramic capacitor is lower.
Disclosure of Invention
In view of this, the embodiment of the invention provides a method for manufacturing a chip type multilayer ceramic capacitor with high-precision stacked internal electrodes, so as to reduce the peeling failure rate of the chip type multilayer ceramic capacitor, avoid deformation in the stacking process, and improve the stacking precision of the chip type multilayer ceramic capacitor.
An aspect of an embodiment of the present invention provides a method for manufacturing a chip type multilayer ceramic capacitor having internal electrodes stacked with high accuracy, including:
the multilayer printed sheet printed with the internal electrodes and the dielectrics is peeled off from the PET film by utilizing the upper gold type;
four inner walls and four outer walls are arranged around each layer of printing sheet inner electrode, an upper inner wall and a lower inner wall are arranged in parallel with the long axis direction of the inner electrode, an upper outer wall is arranged at a certain distance from the outer side of the upper inner wall, and a lower outer wall is arranged at a certain distance from the outer side of the lower inner wall; a left inner wall and a right inner wall are arranged in parallel with the short axis direction of the inner electrode, a left outer wall is arranged outside the left inner wall at a certain distance, and a right outer wall is arranged outside the right inner wall at a certain distance; each outer wall and each inner wall are inner electrodes with specific dimensions;
stacking the multi-layer printing sheets on the lower protective cover in a staggered manner, and covering the upper protective cover on the uppermost printing sheet;
carrying out isostatic pressing on the multilayer printing sheet covered with the upper protective cover and the lower protective cover;
cutting at preset cutting points of the printing sheet to obtain a stacked multi-layer printing sheet.
Preferably, the dimensional relationship of the walls of each layer of printing sheet satisfies g+e=d, 0 is less than or equal to E < D, wherein the end distance of the inner electrode of each layer of printing sheet is D, the distance between the left inner wall and the left outer wall, or the distance between the right inner wall and the right outer wall is E, and the widths of the left inner wall and the right inner wall of each layer of printing sheet are G.
Preferably, the cutting at a preset cutting point of the printing sheet includes:
cutting printing sheets in parallel with the lower inner wall along the gap between the lower inner wall and the lower outer wall;
and cutting the printing sheet in parallel with the left inner wall from the first left blank center in the gap between the lower inner wall and the lower outer wall.
Preferably, the dimensional relationship of the walls of each layer of printed sheets satisfies a+b=c, 0 < B < C, wherein the width of the upper and lower inner walls of each layer of printed sheets is a, the distance between the upper inner wall and the upper outer wall, or the distance between the lower inner wall and the lower outer wall is B, and the sum of the widths of the inner electrode and the electrolyte is C.
Preferably, the cutting at a preset cutting point of the printing sheet includes:
cutting printing sheets in parallel with the left inner wall along the left-most white center of the lower outer wall;
and cutting the printing sheet in parallel with the lower inner wall along the gap between the lower inner wall and the lower outer wall.
Preferably, the width of the cutting groove of the printing sheet cut in the direction parallel to the lower inner wall is smaller than or equal to the gap width of the lower inner wall and the lower outer wall.
Preferably, the width of the cut groove of the printed sheet cut in the direction parallel to the left inner wall is smaller than or equal to the gap width between the inner electrode having a gap with the left inner wall and the left inner wall.
In another aspect of the embodiment of the present invention, there is provided a chip type multilayer ceramic capacitor having high-precision stacked internal electrodes, which is prepared by the above method for preparing a chip type multilayer ceramic capacitor having high-precision stacked internal electrodes, including:
and the multi-layer printing sheets are stacked in a staggered manner, wherein each layer of printing sheet is printed with an inner electrode and a dielectric medium, and the multi-layer printing sheets are obtained by stacking and cutting according to four inner walls and four outer walls which are arranged around the inner electrode of each layer of printing sheet.
Another aspect of the embodiment of the present invention also provides a device for manufacturing a chip type multilayer ceramic capacitor having internal electrodes stacked with high precision, including:
a peeling unit for peeling off the multilayer printed sheet printed with the internal electrode and the dielectric from the PET film by using an upper gold type;
four inner walls and four outer walls are arranged around each layer of printing sheet inner electrode, an upper inner wall and a lower inner wall are arranged in parallel with the long axis direction of the inner electrode, an upper outer wall is arranged at a certain distance from the outer side of the upper inner wall, and a lower outer wall is arranged at a certain distance from the outer side of the lower inner wall; a left inner wall and a right inner wall are arranged in parallel with the short axis direction of the inner electrode, a left outer wall is arranged outside the left inner wall at a certain distance, and a right outer wall is arranged outside the right inner wall at a certain distance; each outer wall and each inner wall are inner electrodes with specific dimensions;
a protective cover covering unit for stacking the multilayer printed sheets on the lower protective cover in a staggered manner, and covering the upper protective cover on the uppermost printed sheet;
the static pressure lamination unit is used for carrying out isostatic pressing on the multilayer printing sheet covered with the upper protective cover and the lower protective cover;
and the cutting unit is used for cutting at preset cutting points of the printing sheets to obtain stacked multi-layer printing sheets.
Another aspect of the embodiment of the invention also provides an electronic device, which includes a processor and a memory;
the memory is used for storing programs;
the processor executes the program to implement the method described above.
Another aspect of the embodiments of the present invention also provides a computer-readable storage medium storing a program that is executed by a processor to implement the above-described method.
Embodiments of the present invention also disclose a computer program product or computer program comprising computer instructions stored in a computer readable storage medium. The computer instructions may be read from a computer-readable storage medium by a processor of a computer device, and executed by the processor, cause the computer device to perform the method described above.
In the invention, the process of stripping the multilayer printed sheets printed with the internal electrodes and the dielectrics from the PET film is utilized, because four inner walls and four outer walls are designed at the edges of the internal electrode patterns of the printed sheets of each layer, the thickness break difference of the electrode blocks at the edge positions of the internal electrode patterns and the exposed internal electrodes alternately appears is basically eliminated due to the existence of the protective walls, and therefore, the edges of the electrode layers can be tightly attached to the gold-shaped surfaces during stripping, and the stripping yield is improved; meanwhile, the overlapping part has no height difference formed by the electrode blocks and the exposed dielectric medium in the stacking process, so that the overlapping part is completely compacted in the stacking process, and the four inner walls and the four outer walls firmly fix the periphery of the chip type multilayer ceramic capacitor and prevent the occurrence of folding failure caused by lifting the edge in the stacking process; in the isostatic pressing process, the protective wall increases the area for compacting the edge of the chip multilayer ceramic capacitor, can effectively resist the acting force from the side face, reduces the product deformation in the pressing process, and can improve the cutting qualification rate.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic flow chart of a method for manufacturing a chip multilayer ceramic capacitor with high-precision stacked internal electrodes according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a printed sheet formed of a dielectric layer with an internal electrode according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a printed sheet with four inner walls and four outer walls added according to an embodiment of the present invention;
FIG. 4 is a cross-sectional view of A-A of FIG. 3, in accordance with an embodiment of the present invention;
FIG. 5 is a diagram showing a specific example of peeling a printing sheet from a PET film according to an embodiment of the present invention;
fig. 6 is a diagram showing a specific example of stress of a chip multilayer ceramic capacitor according to an embodiment of the present invention;
FIG. 7 is a diagram illustrating a placement of a protection wall according to an embodiment of the present invention;
FIG. 8 is a diagram showing a specific example of a cutting slot point of a printing sheet according to an embodiment of the present invention;
FIG. 9 is a diagram of a specific example of long axis dislocation isostatic pressing provided by an embodiment of the invention;
FIG. 10 is a diagram of a specific example of short axis dislocation isostatic pressing provided by an embodiment of the invention;
FIG. 11 is a graph showing a comparative example of various indexes of a chip multi-layer ceramic capacitor according to an embodiment of the present invention, with or without the application of the method of the present invention;
fig. 12 is a block diagram of a device for manufacturing a chip multi-layer ceramic capacitor with high-precision stacked internal electrodes according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Referring to fig. 1, an embodiment of the present invention provides a method for manufacturing a chip type multilayer ceramic capacitor with high-precision stacked internal electrodes, comprising the following steps:
first, a printed sheet of each layer of the present invention will be described, and referring to fig. 2, an embodiment of the present invention provides a schematic diagram of a printed sheet formed of a dielectric layer printed with an internal electrode, where the printed sheet shown in fig. 2 has no protective wall. Wherein 1 is an electrode block, namely an inner electrode, 2 is an exposed dielectric, 3 is a black block for cutting marks on the long axis side of the parallel electrode, and 4 is a white block for cutting marks on the long axis side of the parallel electrode.
Referring to fig. 3, an embodiment of the present invention provides a schematic diagram of a printed sheet with four inner walls and four outer walls added. Wherein 5 is a protective wall a,6 is a protective wall b,7 is a protective wall c,8 is a protective wall d,9 is a cutting groove m,10 is a cutting groove n,5 and 7 are two inner walls respectively, and 6 and 8 are two outer walls respectively.
FIG. 4 is a cross-sectional view of A-A of FIG. 3; when the inner electrode is printed, the protective wall is printed on the dielectric layer, and the thickness of the protective wall is the same as that of the inner electrode.
Four inner walls and four outer walls are arranged around each layer of printing sheet inner electrode, an upper inner wall and a lower inner wall are arranged in parallel with the long axis direction of the inner electrode, an upper outer wall is arranged at a certain distance from the outer side of the upper inner wall, and a lower outer wall is arranged at a certain distance from the outer side of the lower inner wall; left and right inner walls are arranged in parallel with the short axis direction of the inner electrode, a left outer wall is arranged outside the left inner wall at a certain distance, and a right outer wall is arranged outside the right inner wall at a certain distance.
Step S100: the multilayer printed sheet with the internal electrodes and dielectric was peeled off from the PET film using gold plating.
In particular, referring to fig. 4, an exemplary illustration of the release of a printed sheet from a PET film is provided in accordance with an embodiment of the present invention.
The invention designs the number 5-8 protective walls a-d shown in figure 3 at the edge of the inner electrode pattern to basically eliminate the thickness break difference of the inner electrode alternately appearing in the dielectric medium exposed at the 1 electrode block and the 2 at the edge position of the inner electrode due to the existence of the protective walls, so that the edge of the electrode layer is tightly attached to the upper golden surface during stripping, and the stripping yield is improved.
Step S110: the multilayer printed sheets are stacked in alignment on the lower protective cover and the uppermost printed sheet covers the upper protective cover.
Specifically, in the stacking process after stripping, if the long axis direction is misplaced, the 5 protective wall a of the a 'layer and the 6 protective wall b of the b' layer are partially overlapped, wherein the a 'layer and the b' layer are two layers of printing sheets which are adjacent up and down; the 8 protective walls d of the a 'layer completely overlap with the 8 protective walls d of the b' layer. If the short axis direction is misplaced, the 6 protective wall b of the a 'layer is completely overlapped with the 6 protective wall b of the b' layer, and the 8 protective wall d of the a 'layer is partially overlapped with the 8 protective wall d of the b' layer. The overlapping portion is free of a height difference formed by the electrode block 1 and the exposed dielectric medium 2, so that the overlapping portion is completely compacted in the stacking process, and the periphery of the chip type multilayer ceramic capacitor is firmly fixed like four walls, so that the occurrence of folding failure caused by lifting the edges in the stacking process is prevented.
Step S120: and carrying out isostatic pressing on the multi-layer printing sheet covered with the upper protective cover and the lower protective cover.
Specifically, referring to fig. 6, the present invention provides a specific example diagram of stress of a chip type multilayer ceramic capacitor, in which 11 is an upper protective cover of the chip type multilayer ceramic capacitor, 12 is a lower protective cover of the chip type multilayer ceramic capacitor, 13 is a blank for cutting marks after stacking, and 14 is a carrier plate, in the isostatic pressing process, the side surface of the chip type multilayer ceramic capacitor is subjected to a certain pressure due to the stacking thickness.
Step S130: cutting at preset cutting points of the printing sheet to obtain a stacked multi-layer printing sheet.
In an optional implementation manner, the specific dimensions of the four inner walls and the four outer walls designed by the invention are as follows:
(1) In order to meet the requirement that the 5 protective walls a of the a 'layer and the 6 protective walls b of the b' layer are overlapped to the greatest extent after the long axis direction is misplaced in stacking, the size of the 5 protective walls a is required to meet G+E=D, E is not less than 0 and less than D, and when E=0, namely G=D, the 5 protective walls a and the 6 protective walls b can be taken as a whole. If e=d, i.e. g=0, there is no 5 protection wall a, after the stacking length axis direction is dislocated, the 5 protection wall a of the a 'layer and the 6 protection wall b of the b' layer have no overlapping portion, as shown in fig. 7, the embodiment of the invention provides a specific example diagram for placing protection walls, and the product deformation resisting capability is greatly reduced in the isostatic pressing process.
(2) In order to meet the requirement that the 7 protective wall C of the a 'layer and the 8 protective wall d of the B' layer overlap to the maximum extent after the short axis direction is misplaced in stacking, the size of the 7 protective wall C needs to meet the requirement that A+B=C, and 0 is smaller than B and smaller than C.
(3) To meet the visual recognition of the post-isostatic pressing cutter, referring to FIG. 8, an exemplary diagram of a printed sheet cut slot point is provided in which slot region 9 cut slot m and 10 cut slot n are designed.
(1) Referring to fig. 9, an exemplary diagram of a major axis misalignment isostatic pressing is provided in the embodiment of the present invention, after major axis misalignment isostatic pressing, 15 in fig. 9 is identified as a mark point for trimming, and trimming is performed along a trimming line which is in a white center of 15 and is parallel to 7 protection walls c; then 16 is used as a marking point for trimming, and a trimming line which is parallel to the 5 protective wall a and is in the 16 white center is used for trimming; after the cutting in the step is completed, four sides of the product are black-white alternate sides, and the product can be identified and cut by a visual system of a cutting machine. Wherein 15 is a post-stack cutting groove m;16 leave white blocks for parallel long axis side cut marks after stacking.
(2) Referring to fig. 10, an exemplary diagram of short axis offset isostatic pressing is provided in the embodiment of the present invention, after short axis offset isostatic pressing, 17 in fig. 10 is identified as a mark point to be trimmed, and trimming is performed along a trimming line which is leaving a white center of 17 and is parallel to 5 protection walls a; then 18 is used as a marking point for trimming, and a trimming line which is parallel to the 7 protective wall c and is in the center of 18 is left for trimming; after the cutting in the step is completed, four sides of the product are black-white alternate sides, and the product can be identified and cut by a visual system of a cutting machine. In order to ensure the trimming precision, the center line of the dimension B in the figure 8 is trimmed when trimming, and the dimension H of the 9 cutting groove m is required to meet H and is smaller than or equal to B; similarly, the dimension J of the 10 cutting groove n needs to meet J.ltoreq.K. Where 17 is a post-stack cut groove n.
Further, the embodiment of the invention also provides a chip type multilayer ceramic capacitor with high-precision stacked internal electrodes, which is prepared by the preparation method of the chip type multilayer ceramic capacitor with high-precision stacked internal electrodes, and comprises the following steps:
and the multi-layer printing sheets are orderly stacked, wherein each layer of printing sheets is printed with an inner electrode and a dielectric medium, and the multi-layer printing sheets are obtained by stacking and cutting according to four inner walls and four outer walls which are arranged around the inner electrode of each layer of printing sheets.
In order to describe the present invention in more detail, practical application of the present invention will be described in the following with specific examples.
Referring to fig. 11, the present invention provides a comparative example graph of various indexes of a chip type multi-layered ceramic capacitor with or without the application of the method of the present invention.
Specifically, preparing a dielectric film, printing inner electrode slurry on the dielectric film by adopting a screen printing mode according to the design of the method, and stacking the dielectric film, wherein an upper protective layer, a lower protective layer and an electrode layer are designed according to the specification, the capacitance and the like of the chip type multilayer ceramic capacitor; and carrying out isostatic pressing, cutting and adhesive discharging sintering treatment after staggered stacking to obtain the chip type multilayer ceramic capacitor. The chip type multilayer ceramic capacitor can be smoothly stacked, pressed and cut by printing and stacking according to the designed pattern.
Referring to fig. 12, an embodiment of the present invention provides a manufacturing apparatus of a chip type multilayer ceramic capacitor having internal electrodes stacked with high accuracy, including:
a peeling unit for peeling off the multilayer printed sheet printed with the internal electrode and the dielectric from the PET film by using an upper gold type;
four inner walls and four outer walls are arranged around each layer of printing sheet inner electrode, an upper inner wall and a lower inner wall are arranged in parallel with the long axis direction of the inner electrode, an upper outer wall is arranged at a certain distance from the outer side of the upper inner wall, and a lower outer wall is arranged at a certain distance from the outer side of the lower inner wall; a left inner wall and a right inner wall are arranged in parallel with the short axis direction of the inner electrode, a left outer wall is arranged outside the left inner wall at a certain distance, and a right outer wall is arranged outside the right inner wall at a certain distance; each outer wall and each inner wall are inner electrodes with specific dimensions;
a protective cover covering unit for stacking the multilayer printed sheets on the lower protective cover in a staggered manner, and covering the upper protective cover on the uppermost printed sheet;
the static pressure lamination unit is used for carrying out isostatic pressing on the multilayer printing sheet covered with the upper protective cover and the lower protective cover;
and the cutting unit is used for cutting at preset cutting points of the printing sheets to obtain stacked multi-layer printing sheets.
Embodiments of the present invention also disclose a computer program product or computer program comprising computer instructions stored in a computer readable storage medium. The computer instructions may be read from a computer-readable storage medium by a processor of a computer device, and executed by the processor, to cause the computer device to perform the method shown in fig. 1.
In some alternative embodiments, the functions/acts noted in the block diagrams may occur out of the order noted in the operational illustrations. For example, two blocks shown in succession may in fact be executed substantially concurrently or the blocks may sometimes be executed in the reverse order, depending upon the functionality/acts involved. Furthermore, the embodiments presented and described in the flowcharts of the present invention are provided by way of example in order to provide a more thorough understanding of the technology. The disclosed methods are not limited to the operations and logic flows presented herein. Alternative embodiments are contemplated in which the order of various operations is changed, and in which sub-operations described as part of a larger operation are performed independently.
Furthermore, while the invention is described in the context of functional modules, it should be appreciated that, unless otherwise indicated, one or more of the described functions and/or features may be integrated in a single physical device and/or software module or one or more functions and/or features may be implemented in separate physical devices or software modules. It will also be appreciated that a detailed discussion of the actual implementation of each module is not necessary to an understanding of the present invention. Rather, the actual implementation of the various functional modules in the apparatus disclosed herein will be apparent to those skilled in the art from consideration of their attributes, functions and internal relationships. Accordingly, one of ordinary skill in the art can implement the invention as set forth in the claims without undue experimentation. It is also to be understood that the specific concepts disclosed are merely illustrative and are not intended to be limiting upon the scope of the invention, which is to be defined in the appended claims and their full scope of equivalents.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
Logic and/or steps represented in the flowcharts or otherwise described herein, e.g., a ordered listing of executable instructions for implementing logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device.
More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). In addition, the computer readable medium may even be paper or other suitable medium on which the program is printed, as the program may be electronically captured, via, for instance, optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner, if necessary, and then stored in a computer memory.
It is to be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above-described embodiments, the various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, may be implemented using any one or combination of the following techniques, as is well known in the art: discrete logic circuits having logic gates for implementing logic functions on data signals, application specific integrated circuits having suitable combinational logic gates, programmable Gate Arrays (PGAs), field Programmable Gate Arrays (FPGAs), and the like.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
While embodiments of the present invention have been shown and described, it will be understood by those of ordinary skill in the art that: many changes, modifications, substitutions and variations may be made to the embodiments without departing from the spirit and principles of the invention, the scope of which is defined by the claims and their equivalents.
While the preferred embodiment of the present invention has been described in detail, the present invention is not limited to the embodiments described above, and those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention, and these equivalent modifications or substitutions are included in the scope of the present invention as defined in the appended claims.

Claims (10)

1. A method for manufacturing a chip multilayer ceramic capacitor having internal electrodes stacked with high accuracy, comprising:
the multilayer printed sheet printed with the internal electrodes and the dielectrics is peeled off from the PET film by utilizing the upper gold type;
four inner walls and four outer walls are arranged around each layer of printing sheet inner electrode, an upper inner wall and a lower inner wall are arranged in parallel with the long axis direction of the inner electrode, an upper outer wall is arranged at a certain distance from the outer side of the upper inner wall, and a lower outer wall is arranged at a certain distance from the outer side of the lower inner wall; a left inner wall and a right inner wall are arranged in parallel with the short axis direction of the inner electrode, a left outer wall is arranged outside the left inner wall at a certain distance, and a right outer wall is arranged outside the right inner wall at a certain distance; each outer wall and each inner wall are inner electrodes with specific dimensions;
stacking the multi-layer printing sheets on the lower protective cover in a staggered manner, and covering the upper protective cover on the uppermost printing sheet;
carrying out isostatic pressing on the multilayer printing sheet covered with the upper protective cover and the lower protective cover;
cutting at preset cutting points of the printing sheet to obtain a stacked multi-layer printing sheet.
2. The method for manufacturing a chip multi-layer ceramic capacitor with high-precision stacked internal electrodes according to claim 1, wherein the dimensional relationship of each of the walls of each layer of printed sheets satisfies g+e=d, 0.ltoreq.e < D, wherein the distance between the ends of the internal electrodes of each layer of printed sheets is D, the distance between the left internal wall and the left external wall, or the distance between the right internal wall and the right external wall is E, and the widths of the left and right internal walls of each layer of printed sheets are G.
3. The method for manufacturing a chip multi-layer ceramic capacitor having high-precision stacked internal electrodes as recited in claim 2, wherein the cutting at predetermined cutting points of the printed sheet comprises:
cutting printing sheets in parallel with the lower inner wall along the gap between the lower inner wall and the lower outer wall;
and cutting the printing sheet in parallel with the left inner wall from the first left blank center in the gap between the lower inner wall and the lower outer wall.
4. The method for manufacturing a chip multi-layer ceramic capacitor having high precision stacked internal electrodes according to claim 1, wherein the dimensional relationship of each of the streets of each layer of printed sheets satisfies a+b=c, 0 < B < C, wherein the widths of the upper and lower internal walls of each layer of printed sheets are a, the spacing between the upper internal wall and the upper external wall, or the spacing between the lower internal wall and the lower external wall is B, and the sum of the widths of the internal electrodes and the dielectric is C.
5. The method for manufacturing a chip multi-layer ceramic capacitor having high-precision stacked internal electrodes as recited in claim 4, wherein said cutting at predetermined cutting points of the printed sheet comprises:
cutting printing sheets in parallel with the left inner wall along the left-most white center of the lower outer wall;
and cutting the printing sheet in parallel with the lower inner wall along the gap between the lower inner wall and the lower outer wall.
6. The method for manufacturing a chip multi-layered ceramic capacitor having high-precision stacked internal electrodes as recited in any one of claims 1 to 5, wherein a width of a cut groove of the printed sheet cut in a direction parallel to the lower inner wall is smaller than or equal to a gap width between the lower inner wall and the lower outer wall.
7. The method for manufacturing a chip multi-layer ceramic capacitor having stacked internal electrodes with high accuracy according to any one of claims 1 to 5, wherein the width of the cut groove of the printed sheet cut in the direction parallel to the left internal wall is smaller than or equal to the gap width between the internal electrode having a gap with the left internal wall and the left internal wall.
8. A chip multilayer ceramic capacitor having high-precision stacked internal electrodes, characterized by being prepared by a method for preparing the chip multilayer ceramic capacitor having high-precision stacked internal electrodes as claimed in any one of claims 1 to 7, comprising:
and the multi-layer printing sheets are stacked in a staggered manner, wherein each layer of printing sheet is printed with an inner electrode and a dielectric medium, and the multi-layer printing sheets are obtained by stacking and cutting according to four inner walls and four outer walls which are arranged around the inner electrode of each layer of printing sheet.
9. A manufacturing apparatus of a chip type multilayer ceramic capacitor in which internal electrodes are stacked with high accuracy, comprising:
a peeling unit for peeling off the multilayer printed sheet printed with the internal electrode and the dielectric from the PET film by using an upper gold type;
four inner walls and four outer walls are arranged around each layer of printing sheet inner electrode, an upper inner wall and a lower inner wall are arranged in parallel with the long axis direction of the inner electrode, an upper outer wall is arranged at a certain distance from the outer side of the upper inner wall, and a lower outer wall is arranged at a certain distance from the outer side of the lower inner wall; a left inner wall and a right inner wall are arranged in parallel with the short axis direction of the inner electrode, a left outer wall is arranged outside the left inner wall at a certain distance, and a right outer wall is arranged outside the right inner wall at a certain distance; each outer wall and each inner wall are inner electrodes with specific dimensions;
a protective cover covering unit for stacking the multilayer printed sheets on the lower protective cover in a staggered manner, and covering the upper protective cover on the uppermost printed sheet;
the static pressure lamination unit is used for carrying out isostatic pressing on the multilayer printing sheet covered with the upper protective cover and the lower protective cover;
and the cutting unit is used for cutting at preset cutting points of the printing sheets to obtain stacked multi-layer printing sheets.
10. An electronic device comprising a processor and a memory;
the memory is used for storing programs;
the processor executing the program implements the method of any one of claims 1 to 7.
CN202310121545.7A 2023-02-14 2023-02-14 Preparation method of internal electrode high-precision stacked chip type multilayer ceramic capacitor Pending CN116313519A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117275943A (en) * 2023-09-26 2023-12-22 德阳三环科技有限公司 Method for improving bending resistance of multilayer chip ceramic capacitor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117275943A (en) * 2023-09-26 2023-12-22 德阳三环科技有限公司 Method for improving bending resistance of multilayer chip ceramic capacitor
CN117275943B (en) * 2023-09-26 2024-05-28 德阳三环科技有限公司 Method for improving bending resistance of multilayer chip ceramic capacitor

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