CN116302851B - FPGA logic abnormality monitoring and recovering method, device, equipment and medium - Google Patents

FPGA logic abnormality monitoring and recovering method, device, equipment and medium Download PDF

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CN116302851B
CN116302851B CN202310589324.2A CN202310589324A CN116302851B CN 116302851 B CN116302851 B CN 116302851B CN 202310589324 A CN202310589324 A CN 202310589324A CN 116302851 B CN116302851 B CN 116302851B
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fpga
target fpga
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interface
reconfiguration
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CN116302851A (en
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高福亮
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BEIJING ZHONGKE WANGWEI INFORMATION TECHNOLOGY CO LTD
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BEIJING ZHONGKE WANGWEI INFORMATION TECHNOLOGY CO LTD
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3089—Monitoring arrangements determined by the means or processing involved in sensing the monitored data, e.g. interfaces, connectors, sensors, probes, agents
    • G06F11/3093—Configuration details thereof, e.g. installation, enabling, spatial arrangement of the probes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0793—Remedial or corrective actions
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
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  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Retry When Errors Occur (AREA)
  • Logic Circuits (AREA)

Abstract

The invention provides a method, a device, equipment and a medium for monitoring and recovering logic abnormality of an FPGA, relating to the technical field of FPGAs, wherein the method comprises the following steps: creating an FPGA initialization and scanning thread; initializing an interface MAC address of a target FPGA based on an FPGA initializing and scanning thread, and scanning an interface Link state of the target FPGA; and under the condition that the initialization of the interface MAC address fails and the interface Link state is the response abnormal state, sending a reconfiguration message to the target FPGA so as to instruct the target FPGA to perform the reconfiguration operation of the logic program. The method and the device can realize automatic monitoring of the logic abnormality of the target FPGA, and send the reconfiguration message to the target FPGA to automatically trigger the target FPGA to perform the reconfiguration operation of the logic program when the logic abnormality of the target FPGA is determined, thereby effectively realizing remote logic abnormality monitoring and recovery of the target FPGA.

Description

FPGA logic abnormality monitoring and recovering method, device, equipment and medium
Technical Field
The invention relates to the technical field of Field Programmable Gate Array (FPGA), in particular to a method, a device, equipment and a medium for monitoring and recovering logic abnormality of an FPGA.
Background
In the related art, a logic program of a field programmable gate array (Field Programmable Gate Array, FPGA) is burned by connecting a joint test group (Joint Test Action Group, JTAG) interface of an FPGA accelerator card through a specific xinline software. The FPGA accelerator card is powered by a device main board, is automatically loaded and operated after being electrified, because of the limitation of hardware design, the logic program of the FPGA still operates under the condition that the main board is not powered off by Reboot hot restarting, the logic program of the FPGA can be triggered to be reloaded only by pulling out the power supply of the device and then electrifying, the existing network can not enter a field machine room to carry out power pulling operation sometimes, and under the condition that the quantity of the shipment equipment is large or the equipment is relatively scattered, the FPGA has logic abnormality problem and can not be remotely managed, and the later investment and maintenance labor cost is huge.
Therefore, how to monitor and recover the remote logic anomaly of the FPGA is a problem that needs to be solved in the industry.
Disclosure of Invention
Aiming at the problems existing in the prior art, the invention provides a method, a device, equipment and a medium for monitoring and recovering logic abnormality of an FPGA.
In a first aspect, the present invention provides a method for monitoring and recovering logic anomalies of an FPGA, including:
creating an FPGA initialization and scanning thread;
initializing an interface MAC address of a target FPGA based on the FPGA initialization and scanning thread, and scanning an interface Link state of the target FPGA;
and under the condition that the initialization of the interface MAC address of the target FPGA fails and the interface Link state is the response abnormal state, sending a reconfiguration message to the target FPGA, wherein the reconfiguration message is used for indicating the target FPGA to perform the reconfiguration operation of the logic program.
Optionally, according to the method for monitoring and recovering logical anomalies of an FPGA provided by the present invention, when it is determined that initialization of an interface MAC address of the target FPGA fails, and the interface Link state is a response anomaly state, a reconfiguration message is sent to the target FPGA, including:
acquiring interface flow statistical data of the target FPGA under the condition that the initialization of the interface MAC address of the target FPGA is failed and the interface Link state is a response abnormal state;
judging whether the target FPGA loses packets or not based on the interface flow statistic data;
and sending a reconfiguration message to the target FPGA under the condition that the target FPGA is determined not to lose the packet.
Optionally, according to the method for monitoring and recovering the logic anomaly of the FPGA provided by the present invention, the method further includes:
under the condition that the packet loss of the target FPGA is determined, initializing an interface MAC address of the target FPGA repeatedly based on the FPGA initializing and scanning thread, scanning an interface Link state of the target FPGA, and under the condition that the packet loss of the target FPGA is determined not to occur and a response message of the target FPGA for initializing the interface MAC address and responding to the interface Link state is not received within a first preset time period, sending a reconfiguration message to the target FPGA.
Optionally, according to the method for monitoring and recovering the logic anomaly of the FPGA provided by the present invention, the method further includes:
and under the condition that the response message of the target FPGA for responding to the logic program reconfiguration of the target FPGA is not received within a second preset time period after the reconfiguration message is sent to the target FPGA, determining that the logic program reconfiguration of the target FPGA fails, controlling a target interface of the target FPGA, and realizing forced reconfiguration operation of the logic program of the target FPGA.
Optionally, according to the method for monitoring and recovering logical anomalies of an FPGA provided by the present invention, when it is determined that initialization of an interface MAC address of the target FPGA fails, and the interface Link state is a response anomaly state, a reconfiguration message is sent to the target FPGA, including:
under the condition that the response message of the target FPGA for initializing the interface MAC address and responding to the interface Link state cannot be normally received, the interface MAC address of the target FPGA is determined to be failed to initialize, the interface Link state is the abnormal response state, and the reconfiguration message is sent to the target FPGA.
Optionally, according to the method for monitoring and recovering logical anomalies of an FPGA provided by the present invention, when it is determined that initialization of an interface MAC address of the target FPGA fails, and the interface Link state is a response anomaly state, a reconfiguration message is sent to the target FPGA, including:
and under the condition that the initialization of the interface MAC address of the target FPGA fails and the interface Link state is a response abnormal state, acquiring a command instruction input by a user on a command line interface, and sending the reconfiguration message to the target FPGA based on the command instruction.
Optionally, according to the method for monitoring and recovering the logic anomaly of the FPGA provided by the present invention, the method further includes:
and counting target information of the logic program of the target FPGA in the reconfiguration process, wherein the target information comprises reconfiguration time information, reconfiguration result information and receiving and transmitting message information communicated with the target FPGA.
In a second aspect, the present invention further provides an FPGA logic anomaly monitoring and recovery device, including:
the creation module is used for creating FPGA initialization and scanning threads;
the initialization and scanning module is used for initializing an interface MAC address of a target FPGA based on the FPGA initialization and scanning thread and scanning the interface Link state of the target FPGA;
the sending module is used for sending a reconfiguration message to the target FPGA under the condition that the initialization failure of the interface MAC address of the target FPGA is determined and the interface Link state is the response abnormal state, wherein the reconfiguration message is used for indicating the target FPGA to perform the reconfiguration operation of the logic program.
In a third aspect, the present invention further provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor, where the processor implements the FPGA logic anomaly monitoring and recovery method according to the first aspect when the processor executes the program.
In a fourth aspect, the present invention also provides a non-transitory computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the FPGA logic anomaly monitoring and recovery method according to the first aspect.
According to the FPGA logic anomaly monitoring and recovering method, device, equipment and medium, an FPGA initialization and scanning thread is established, an interface MAC address of a target FPGA is initialized based on the FPGA initialization and scanning thread, an interface Link state of the target FPGA is scanned, and a reconfiguration message is sent to the target FPGA to instruct the target FPGA to perform reconfiguration operation of a logic program under the condition that the initialization failure of the interface MAC address of the target FPGA is determined and the interface Link state is a response anomaly state; the method and the device realize the monitoring of the logic abnormality of the target FPGA through the built FPGA initialization and scanning thread, and send the reconfiguration message to the target FPGA to automatically trigger the target FPGA to perform the reconfiguration operation of the logic program under the condition that the logic abnormality of the target FPGA is determined, thereby effectively realizing the remote logic abnormality monitoring and recovery of the target FPGA.
Drawings
In order to more clearly illustrate the invention or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic flow chart of the FPGA logic anomaly monitoring and recovery method provided by the invention;
FIG. 2 is a schematic diagram of the structure of the FPGA logic anomaly monitoring and recovery device provided by the invention;
fig. 3 is a schematic diagram of an entity structure of an electronic device according to the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that, in the description of the present invention, the terms "first," "second," and the like are used for distinguishing between similar objects and not for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged, as appropriate, such that embodiments of the present invention may be implemented in sequences other than those illustrated or described herein, and that the objects identified by "first," "second," etc. are generally of a type, and are not limited to the number of objects, such as the first object may be one or more.
The method, the device, the equipment and the medium for monitoring and recovering the FPGA logic abnormality are exemplarily described below with reference to the accompanying drawings.
Fig. 1 is a schematic flow chart of an FPGA logic anomaly monitoring and recovering method provided by the present invention, as shown in fig. 1, the method includes:
step 100, creating an FPGA initialization and scanning thread;
step 110, initializing an interface MAC (Media Access Control Address) address of a target FPGA based on the FPGA initializing and scanning thread, and scanning an interface Link state of the target FPGA;
step 120, when it is determined that the initialization of the interface MAC address of the target FPGA fails, and the interface Link state is a response abnormal state, a reconfiguration message is sent to the target FPGA, where the reconfiguration message is used to instruct the target FPGA to perform a reconfiguration operation of the logic program.
It should be noted that, the execution body of the FPGA logic anomaly monitoring and recovering method provided by the embodiment of the present invention may be an electronic device, a component in the electronic device, an integrated circuit, or a chip. The electronic device may be a mobile electronic device or a non-mobile electronic device. Illustratively, the mobile electronic device may be a mobile phone, a tablet computer, a notebook computer, a palm computer, a wearable device, an Ultra mobile personal computer (Ultra-mobile Personal Computer, UMPC), a netbook or a personal digital assistant (Personal Digital Assistant, PDA), etc., and the non-mobile electronic device may be a server, a network attached storage (Network Attached Storage, NAS), a personal computer (Personal Computer, PC), a Television (Television, TV), a teller machine or a self-service machine, etc., which is not particularly limited by the embodiments of the present invention.
The technical scheme of the embodiment of the invention is described in detail below by taking the method for monitoring and recovering the logic abnormality of the FPGA provided by the invention as an example by executing the computer.
Specifically, in order to overcome the defect that the prior art cannot remotely manage the FPGA when the logic abnormality occurs, the method comprises the steps of creating an FPGA initialization and scanning thread, initializing an interface MAC address of a target FPGA based on the FPGA initialization and scanning thread, scanning an interface Link state of the target FPGA, and sending a reconfiguration message to the target FPGA to instruct the target FPGA to perform the reconfiguration operation of the logic program under the condition that the interface MAC address of the target FPGA is determined to be failed to initialize and the interface Link state is in a response abnormal state; the method and the device realize the monitoring of the logic abnormality of the target FPGA through the built FPGA initialization and scanning thread, and send the reconfiguration message to the target FPGA to automatically trigger the target FPGA to perform the reconfiguration operation of the logic program under the condition that the logic abnormality of the target FPGA is determined, thereby effectively realizing the remote logic abnormality monitoring and recovery of the target FPGA.
It should be noted that, in the embodiment of the present invention, the target FPGA is an FPGA to be subjected to logic anomaly monitoring and recovery. After the logic program of the target FPGA is powered on, loading is completed, after the system is started, software creates an FPGA initialization and scanning thread, the interface MAC address of the target FPGA is initialized through a communication message of an assembly special protocol in the thread, and the interface Link state of the target FPGA is scanned regularly (for example, every 2 seconds, 3 seconds or 5 seconds and the like), and when the interface Link state is the response normal state, the logic of the target FPGA is determined to be normal without any operation; and if the initialization failure of the interface MAC address of the target FPGA is determined and the interface Link state is the response abnormal state, a reconfiguration message is sent to the target FPGA to instruct the target FPGA to perform the reconfiguration operation of the logic program, so that the logic function recovery of the target FPGA is realized.
It can be understood that by creating a background thread and assembling a communication message of a custom special protocol, the embodiment of the invention scans the logic running state of the target FPGA at regular time, and automatically reconfigures the logic program operation of the target FPGA when the abnormality such as no response or no forwarding of the target FPGA is detected, so as to recover the logic function of the target FPGA, and solve the problem that the prior art must pull out the power supply of the device to power off to trigger the restart recovery of the FPGA.
According to the FPGA logic anomaly monitoring and recovering method provided by the invention, the FPGA initialization and scanning thread is established, the interface MAC address of the target FPGA is initialized based on the FPGA initialization and scanning thread, the interface Link state of the target FPGA is scanned, and a reconfiguration message is sent to the target FPGA under the condition that the interface Link state is determined to be in a response anomaly state, so that the target FPGA is instructed to perform the reconfiguration operation of the logic program; the method and the device realize the monitoring of the logic abnormality of the target FPGA through the built FPGA initialization and scanning thread, and send the reconfiguration message to the target FPGA to automatically trigger the target FPGA to perform the reconfiguration operation of the logic program under the condition that the logic abnormality of the target FPGA is determined, thereby effectively realizing the remote logic abnormality monitoring and recovery of the target FPGA.
Optionally, the sending a reconfiguration message to the target FPGA under the condition that it is determined that the initialization of the interface MAC address of the target FPGA fails and the interface Link state is a response abnormal state includes:
acquiring interface flow statistical data of the target FPGA under the condition that the initialization of the interface MAC address of the target FPGA is failed and the interface Link state is a response abnormal state;
judging whether the target FPGA loses packets or not based on the interface flow statistic data;
and sending a reconfiguration message to the target FPGA under the condition that the target FPGA is determined not to lose the packet.
Specifically, in the embodiment of the invention, through the initialization of the FPGA and the monitoring of the logic function of the target FPGA by the scanning thread, under the condition that the initialization failure of the interface MAC address of the target FPGA is determined and the interface Link state is the response abnormal state, the interface flow statistical data of the target FPGA can be obtained, and then whether the target FPGA loses the packet is judged based on the interface flow statistical data, if the logic abnormality of the target FPGA is determined under the condition that the packet loss of the target FPGA does not occur, a reconfiguration message is sent to the target FPGA to instruct the target FPGA to perform the reconfiguration operation of the logic program, thereby realizing the logic function recovery of the target FPGA.
In the embodiment of the invention, in the process of reconfiguring the logic program of the target FPGA, the interface flow of the target FPGA can be counted in real time, and then whether the packet loss occurs in the process of reconfiguring the target FPGA can be judged based on the interface flow statistic data of the target FPGA.
It should be noted that, when it is determined that the initialization of the interface MAC address of the target FPGA fails, the interface Link state is a response abnormal state, and it is determined that no packet loss occurs in the target FPGA based on the interface traffic statistics data of the target FPGA, it may be determined that the operation of the target FPGA is abnormal in an idle state, and a reconfiguration message is sent to the target FPGA to instruct the target FPGA to perform a reconfiguration operation of the logic program, so as to implement a logic function recovery of the target FPGA.
Optionally, the method further comprises:
under the condition that the packet loss of the target FPGA is determined, initializing an interface MAC address of the target FPGA repeatedly based on the FPGA initializing and scanning thread, scanning an interface Link state of the target FPGA, and under the condition that the packet loss of the target FPGA is determined not to occur and a response message of the target FPGA for initializing the interface MAC address and responding to the interface Link state is not received within a first preset time period, sending a reconfiguration message to the target FPGA.
Specifically, in the embodiment of the invention, through the monitoring of the FPGA initialization and the scanning thread on the logic function of the target FPGA, under the condition that the initialization of the interface MAC address of the target FPGA fails and the interface Link state is a response abnormal state, the interface flow statistics data of the target FPGA can be obtained, and then whether the target FPGA loses a packet is judged based on the interface flow statistics data, if the packet loss of the target FPGA is determined, the interface MAC address of the target FPGA is repeatedly initialized based on the FPGA initialization and the scanning thread, the interface Link state of the target FPGA is scanned, and under the condition that the packet loss of the target FPGA is determined not to occur and the response message of the target FPGA for the initialization of the interface MAC address and the interface Link state is not received within the first preset time period, the reconfiguration message is sent to the target FPGA to instruct the target FPGA to perform the reconfiguration operation of the logic program, thereby realizing the logic function recovery of the target FPGA.
It should be noted that, in the embodiment of the present invention, the first preset duration may be adaptively set based on practical applications, for example, the first preset duration is 3 seconds, 5 seconds, or 8 seconds, which is not limited in particular.
Optionally, in the embodiment of the present invention, when it is determined that a packet loss occurs in the target FPGA, the method may repeat the presetting of the interface MAC address of the target FPGA and the scanning of the interface Link state of the target FPGA based on the FPGA initialization and scanning threads, and if the accumulated number of times exceeds the threshold, and still does not receive a response message that the target FPGA responds to the initialization of the interface MAC address and the interface Link state, it may determine that the target FPGA has abnormal operation in the idle state, and send a reconfiguration message to the target FPGA to instruct the target FPGA to perform the reconfiguration operation of the logic program, thereby implementing the recovery of the logic function of the target FPGA.
Optionally, the method further comprises:
and under the condition that the response message of the target FPGA for responding to the logic program reconfiguration of the target FPGA is not received within a second preset time period after the reconfiguration message is sent to the target FPGA, determining that the logic program reconfiguration of the target FPGA fails, controlling a target interface of the target FPGA, and realizing forced reconfiguration operation of the logic program of the target FPGA.
Specifically, in the embodiment of the invention, through the monitoring of the FPGA initialization and scanning threads on the logic function of the target FPGA, when the initialization failure of the interface MAC address of the target FPGA is determined and the interface Link state is the abnormal response state, a reconfiguration message is sent to the target FPGA, and when the response message of the target FPGA for responding to the logic program reconfiguration of the target FPGA is not received within the second preset time period after the reconfiguration message is sent to the target FPGA, the logic program reconfiguration failure of the target FPGA is determined, and the target interface of the target FPGA is controlled, so that the forced reconfiguration operation on the logic program of the target FPGA is realized.
Optionally, the target interface in the embodiment of the present invention may be a JTAG interface of a target FPGA accelerator card; and under the condition that the response message of the target FPGA for responding to the reconfiguration of the logic program of the target FPGA is not received in the second preset time after the reconfiguration message is sent to the target FPGA, determining that the reconfiguration of the logic program of the target FPGA fails, and controlling the JTAG interface of the target FPGA to realize forced reconfiguration operation of the logic program of the target FPGA.
Optionally, a reconfiguration message may be sent to the target FPGA through a custom protocol, then a second preset time period (for example, 8 seconds is required by FPGA hardware) is delayed to wait for the reconfiguration loading of the target FPGA to be completed, the target FPGA replies a response message after the reconfiguration loading is completed, if the response message of the target FPGA is not received within the second preset time period, the reconfiguration message may be sent to the target FPGA for a preset number of times (for example, 3 times), and if the response message of the target FPGA is not received yet, it is determined that the reconfiguration failure of the logic program of the target FPGA is performed, and the reconfiguration issue failure event information may be recorded; if the response message of the target FPGA is normally received, the information of the reconfiguration issuing success event can be recorded.
Optionally, the response message of the target FPGA may carry the result value received by the reconfiguration message, and the response message is successfully received as 1, then the reconfiguration operation is started, the reconfiguration of the target FPGA triggers automatic power-off and reloads the logic program, and the forwarding and response functions of the target FPGA are disabled, so that during the reconfiguration of the target FPGA, the interface Link state acquisition message can be circularly issued to the target FPGA, after the reconfiguration of the target FPGA, the logic loading is completed to restore the normal response message, if the response message of the target FPGA is received within the specified time, the reconfiguration success event of the target FPGA is recorded, and otherwise, the reconfiguration failure event of the target FPGA is recorded.
Optionally, the sending a reconfiguration message to the target FPGA under the condition that it is determined that the initialization of the interface MAC address of the target FPGA fails and the interface Link state is a response abnormal state includes:
under the condition that the response message of the target FPGA for initializing the interface MAC address and responding to the interface Link state cannot be normally received, the interface MAC address of the target FPGA is determined to be failed to initialize, the interface Link state is the abnormal response state, and the reconfiguration message is sent to the target FPGA.
Specifically, in the embodiment of the invention, a background thread is created and a communication message of a custom special protocol is assembled, an interface MAC address of a target FPGA is initialized, an interface Link state of the target FPGA is scanned regularly (for example, every 2 seconds, 3 seconds or 5 seconds and the like), under the condition that an answer message of the target FPGA for initializing the interface MAC address and answering the interface Link state cannot be normally received is determined, the failure of initializing the interface MAC address of the target FPGA is determined, the interface Link state is an answer abnormal state, the logic abnormality of the target FPGA is determined, and a reconfiguration message is sent to the target FPGA to instruct the target FPGA to perform the reconfiguration operation of the logic program, so that the logic function recovery of the target FPGA is realized.
It can be understood that, in the embodiment of the invention, the background thread is created and the communication message of the custom special protocol is assembled to initialize the interface MAC address of the target FPGA, and the interface Link state of the target FPGA is scanned at regular time, if the response message sent by the target FPGA and about the successful initialization of the interface MAC address can be normally received, and if the response message sent by the target FPGA and about the interface Link state as the response normal state can be normally received, the logic of the target FPGA is determined to be normal, and no operation is required at this time; if the response message about the successful initialization of the interface MAC address sent by the target FPGA is not normally received, and the response message about the interface Link state sent by the target FPGA is not normally received, determining that the logic of the target FPGA is abnormal, sending a reconfiguration message to the target FPGA so as to instruct the target FPGA to perform the reconfiguration operation of the logic program, thereby realizing the logic function recovery of the target FPGA.
Optionally, the sending a reconfiguration message to the target FPGA under the condition that it is determined that the initialization of the interface MAC address of the target FPGA fails and the interface Link state is a response abnormal state includes:
and under the condition that the initialization of the interface MAC address of the target FPGA fails and the interface Link state is a response abnormal state, acquiring a command instruction input by a user on a command line interface, and sending the reconfiguration message to the target FPGA based on the command instruction.
Specifically, in the embodiment of the invention, by creating a background thread and assembling a communication message of a custom special protocol, initializing an interface MAC address of a target FPGA, and periodically scanning (for example, every 2 seconds, 3 seconds or 5 seconds, etc.) an interface Link state of the target FPGA, under the condition that the initialization failure of the interface MAC address of the target FPGA is determined and the interface Link state of the target FPGA is in a response abnormal state, a command instruction input by a user on a command line interface can be obtained, and further, a reconfiguration message is sent to the target FPGA based on the command instruction, so that the reconfiguration operation of a logic program of the target FPGA is manually triggered.
Optionally, whether the reconfiguration operation of the logic program of the target FPGA needs to be triggered can be determined according to the interface MAC initialization of the target FPGA and the response condition of the interface Link state.
Optionally, the method further comprises:
and counting target information of the logic program of the target FPGA in the reconfiguration process, wherein the target information comprises reconfiguration time information, reconfiguration result information and receiving and transmitting message information communicated with the target FPGA.
Specifically, in the embodiment of the present invention, the target information of the logic program of the target FPGA in the reconfiguration process may be counted, where the target information may include time information of the reconfiguration of the logic program of the target FPGA, result information of the reconfiguration, and message information for communication with the target FPGA, where the message information for communication with the target FPGA includes reconfiguration starting operation event information, reconfiguration starting result event information, and the like.
It should be noted that, in the reconfiguration process of the target FPGA, the communication messages between the software and the target FPGA have transceiving statistics, when the reconfiguration of the target FPGA is triggered automatically or manually, a reconfiguration event is recorded according to the current system time, after the reconfiguration is completed, a reconfiguration result event is recorded, and in the case of failure of the reconfiguration of the target FPGA, the cause of the failure of the reconfiguration of the target FPGA can be determined by checking the transceiving statistics.
Optionally, in the embodiment of the present invention, the logic running state of the target FPGA may also be queried through a command line.
It should be noted that, in the method for monitoring and recovering the logic exception of the FPGA provided by the embodiment of the present invention, by creating a background thread and assembling a communication message of a custom special protocol, the logic operation state of the target FPGA is scanned at regular time, and when an exception such as no response or no forwarding of the target FPGA is detected, the logic program operation of the target FPGA is automatically reconfigured, so as to recover the logic function of the target FPGA, thereby solving the problem that the prior art must pull out the power supply of the device to trigger the restart recovery of the FPGA, and at the same time triggering the reconfiguration to record the logic exception and recovery event log of the target FPGA.
According to the FPGA logic anomaly monitoring and recovering method provided by the invention, the FPGA initialization and scanning thread is established, the interface MAC address of the target FPGA is initialized based on the FPGA initialization and scanning thread, the interface Link state of the target FPGA is scanned, and a reconfiguration message is sent to the target FPGA under the condition that the interface Link state is determined to be in a response anomaly state, so that the target FPGA is instructed to perform the reconfiguration operation of the logic program; the method and the device realize the monitoring of the logic abnormality of the target FPGA through the built FPGA initialization and scanning thread, and send the reconfiguration message to the target FPGA to automatically trigger the target FPGA to perform the reconfiguration operation of the logic program under the condition that the logic abnormality of the target FPGA is determined, thereby effectively realizing the remote logic abnormality monitoring and recovery of the target FPGA.
The device for monitoring and recovering the FPGA logic abnormality provided by the invention is described below, and the device for monitoring and recovering the FPGA logic abnormality described below and the method for monitoring and recovering the FPGA logic abnormality described above can be referred to correspondingly.
Fig. 2 is a schematic structural diagram of an FPGA logic anomaly monitoring and recovery device according to the present invention, as shown in fig. 2, the device includes: a creation module 210, an initialization and scanning module 220 and a transmission module 230; wherein:
the creation module 210 is used for creating an FPGA initialization and scanning thread;
the initialization and scanning module 220 is configured to initialize an interface MAC address of a target FPGA and scan an interface Link state of the target FPGA based on the FPGA initialization and scanning thread;
the sending module 230 is configured to send a reconfiguration message to the target FPGA, where the reconfiguration message is used to instruct the target FPGA to perform a reconfiguration operation of a logic program when it is determined that the initialization of the interface MAC address of the target FPGA fails and the interface Link state is a response abnormal state.
According to the FPGA logic anomaly monitoring and recovering device, an FPGA initialization and scanning thread is established, an interface MAC address of a target FPGA is initialized based on the FPGA initialization and scanning thread, an interface Link state of the target FPGA is scanned, and a reconfiguration message is sent to the target FPGA under the condition that the initialization failure of the interface MAC address of the target FPGA is confirmed and the interface Link state is a response anomaly state, so that the target FPGA is instructed to perform the reconfiguration operation of a logic program; the method and the device realize the monitoring of the logic abnormality of the target FPGA through the built FPGA initialization and scanning thread, and send the reconfiguration message to the target FPGA to automatically trigger the target FPGA to perform the reconfiguration operation of the logic program under the condition that the logic abnormality of the target FPGA is determined, thereby effectively realizing the remote logic abnormality monitoring and recovery of the target FPGA.
It should be noted that, the device for monitoring and recovering the FPGA logic abnormality provided by the embodiment of the present invention can implement all the method steps implemented by the method embodiment for monitoring and recovering the FPGA logic abnormality, and can achieve the same technical effects, and the same parts and beneficial effects as those of the method embodiment in the embodiment are not described in detail herein.
Fig. 3 is a schematic physical structure of an electronic device according to the present invention, and as shown in fig. 3, the electronic device may include: processor 310, communication interface (Communications Interface) 320, memory 330 and communication bus 340, wherein processor 310, communication interface 320, memory 330 accomplish communication with each other through communication bus 340. The processor 310 may call logic instructions in the memory 330 to perform the FPGA logic anomaly monitoring and recovery method provided by the methods described above, the method comprising:
creating an FPGA initialization and scanning thread;
initializing an interface MAC address of a target FPGA based on the FPGA initialization and scanning thread, and scanning an interface Link state of the target FPGA;
and under the condition that the initialization of the interface MAC address of the target FPGA fails and the interface Link state is the response abnormal state, sending a reconfiguration message to the target FPGA, wherein the reconfiguration message is used for indicating the target FPGA to perform the reconfiguration operation of the logic program.
Further, the logic instructions in the memory 330 described above may be implemented in the form of software functional units and may be stored in a computer-readable storage medium when sold or used as a stand-alone product. Based on this understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
In another aspect, the present invention also provides a computer program product comprising a computer program stored on a non-transitory computer readable storage medium, the computer program comprising program instructions which, when executed by a computer, are capable of performing the method for monitoring and recovering logical anomalies of an FPGA provided by the above methods, the method comprising:
creating an FPGA initialization and scanning thread;
initializing an interface MAC address of a target FPGA based on the FPGA initialization and scanning thread, and scanning an interface Link state of the target FPGA;
and under the condition that the initialization of the interface MAC address of the target FPGA fails and the interface Link state is the response abnormal state, sending a reconfiguration message to the target FPGA, wherein the reconfiguration message is used for indicating the target FPGA to perform the reconfiguration operation of the logic program.
In yet another aspect, the present invention further provides a non-transitory computer readable storage medium having stored thereon a computer program which, when executed by a processor, is implemented to perform the above-provided FPGA logic anomaly monitoring and recovery methods, the method comprising:
creating an FPGA initialization and scanning thread;
initializing an interface MAC address of a target FPGA based on the FPGA initialization and scanning thread, and scanning an interface Link state of the target FPGA;
and under the condition that the initialization of the interface MAC address of the target FPGA fails and the interface Link state is the response abnormal state, sending a reconfiguration message to the target FPGA, wherein the reconfiguration message is used for indicating the target FPGA to perform the reconfiguration operation of the logic program.
The apparatus embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art will understand and implement the present invention without undue burden.
From the above description of the embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus necessary general hardware platforms, or of course may be implemented by means of hardware. Based on this understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the prior art in the form of a software product, which may be stored in a computer readable storage medium, such as ROM/RAM, a magnetic disk, an optical disk, etc., including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method described in the respective embodiments or some parts of the embodiments.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims (8)

1. The FPGA logic anomaly monitoring and recovering method is characterized by comprising the following steps of:
creating an FPGA initialization and scanning thread;
initializing an interface MAC address of a target FPGA based on the FPGA initialization and scanning thread, and scanning an interface Link state of the target FPGA;
when the initialization failure of the interface MAC address of the target FPGA is determined, and the interface Link state is a response abnormal state, sending a reconfiguration message to the target FPGA, wherein the reconfiguration message is used for indicating the target FPGA to perform the reconfiguration operation of the logic program;
the sending a reconfiguration message to the target FPGA under the condition that the initialization of the interface MAC address of the target FPGA is determined to fail and the interface Link state is a response abnormal state includes:
acquiring interface flow statistical data of the target FPGA under the condition that the initialization of the interface MAC address of the target FPGA is failed and the interface Link state is a response abnormal state;
judging whether the target FPGA loses packets or not based on the interface flow statistic data;
sending a reconfiguration message to the target FPGA under the condition that the target FPGA is determined not to lose packets;
the method further comprises the steps of:
under the condition that the packet loss of the target FPGA is determined, initializing an interface MAC address of the target FPGA repeatedly based on the FPGA initializing and scanning thread, scanning an interface Link state of the target FPGA, and under the condition that the packet loss of the target FPGA is determined not to occur and a response message of the target FPGA for initializing the interface MAC address and responding to the interface Link state is not received within a first preset time period, sending a reconfiguration message to the target FPGA.
2. The FPGA logic anomaly monitoring and recovery method of claim 1, further comprising:
and under the condition that the response message of the target FPGA for responding to the logic program reconfiguration of the target FPGA is not received within a second preset time period after the reconfiguration message is sent to the target FPGA, determining that the logic program reconfiguration of the target FPGA fails, controlling a target interface of the target FPGA, and realizing forced reconfiguration operation of the logic program of the target FPGA.
3. The method for monitoring and recovering logical anomalies of an FPGA according to claim 1, wherein, in the case that it is determined that the initialization of the interface MAC address of the target FPGA fails and the interface Link state is a response anomaly state, sending a reconfiguration message to the target FPGA includes:
under the condition that the response message of the target FPGA for initializing the interface MAC address and responding to the interface Link state cannot be normally received, the interface MAC address of the target FPGA is determined to be failed to initialize, the interface Link state is the abnormal response state, and the reconfiguration message is sent to the target FPGA.
4. The method for monitoring and recovering logical anomalies of an FPGA according to claim 1, wherein, in the case that it is determined that the initialization of the interface MAC address of the target FPGA fails and the interface Link state is a response anomaly state, sending a reconfiguration message to the target FPGA includes:
and under the condition that the initialization of the interface MAC address of the target FPGA fails and the interface Link state is a response abnormal state, acquiring a command instruction input by a user on a command line interface, and sending the reconfiguration message to the target FPGA based on the command instruction.
5. The FPGA logic anomaly monitoring and recovery method of any one of claims 1-4, further comprising:
and counting target information of the logic program of the target FPGA in the reconfiguration process, wherein the target information comprises reconfiguration time information, reconfiguration result information and receiving and transmitting message information communicated with the target FPGA.
6. An FPGA logic anomaly monitoring and recovery device, comprising:
the creation module is used for creating FPGA initialization and scanning threads;
the initialization and scanning module is used for initializing an interface MAC address of a target FPGA based on the FPGA initialization and scanning thread and scanning the interface Link state of the target FPGA;
the sending module is used for sending a reconfiguration message to the target FPGA under the condition that the initialization failure of the interface MAC address of the target FPGA is determined and the interface Link state is a response abnormal state, wherein the reconfiguration message is used for indicating the target FPGA to perform the reconfiguration operation of the logic program;
the sending module is specifically configured to:
acquiring interface flow statistical data of the target FPGA under the condition that the initialization of the interface MAC address of the target FPGA is failed and the interface Link state is a response abnormal state;
judging whether the target FPGA loses packets or not based on the interface flow statistic data;
sending a reconfiguration message to the target FPGA under the condition that the target FPGA is determined not to lose packets;
under the condition that the packet loss of the target FPGA is determined, initializing an interface MAC address of the target FPGA repeatedly based on the FPGA initializing and scanning thread, scanning an interface Link state of the target FPGA, and under the condition that the packet loss of the target FPGA is determined not to occur and a response message of the target FPGA for initializing the interface MAC address and responding to the interface Link state is not received within a first preset time period, sending a reconfiguration message to the target FPGA.
7. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the FPGA logic anomaly monitoring and recovery method of any one of claims 1 to 5 when the program is executed by the processor.
8. A non-transitory computer readable storage medium having stored thereon a computer program, wherein the computer program when executed by a processor implements the FPGA logic anomaly monitoring and recovery method of any one of claims 1 to 5.
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