CN116266572A - Electronic component - Google Patents
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- CN116266572A CN116266572A CN202111552112.4A CN202111552112A CN116266572A CN 116266572 A CN116266572 A CN 116266572A CN 202111552112 A CN202111552112 A CN 202111552112A CN 116266572 A CN116266572 A CN 116266572A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5286—Arrangements of power or ground buses
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- Microelectronics & Electronic Packaging (AREA)
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- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The invention relates to an electronic component, which comprises a carrier plate, wherein the carrier plate comprises a plurality of rewiring layers. The multilayer rewiring layer comprises a first reference layer, a first signal layer and a second reference layer, wherein the first reference layer, the first signal layer and the second reference layer are stacked and arranged at intervals; the first reference layer includes a first portion, a second portion spaced apart from the first portion, and a third portion connecting the first portion and the second portion, the first portion, the second portion, and the third portion defining a plurality of first openings exposing portions of the first signal layer.
Description
Technical Field
The present invention relates to the field of semiconductor technology, and more particularly, to an electronic component.
Background
To meet the development of technological products toward higher transmission rate and convenience, the bandwidth is expanded and the packaging volume is reduced, but this affects the performance and stability of the product. For example, to miniaturize the packaged product, the circuit layer is made to achieve high wiring density to thin the package by taking advantage of the fine line dominance of the re-wiring layer (RDL) (e.g., the pitch and spacing L/S of RDL may be 5 μm/5 μm, 2 μm/2 μm, 1 μm/1 μm, etc.), along with the dominance of the thin copper layer thickness. However, when the circuit layer is thinned, the dielectric material (such as polyimide, PI) between the circuit layers is also thinned relatively, so that the distance between the layers of the circuit is very close, and parasitic capacitance is generated, which makes impedance control very difficult, and the unmatched impedance causes very poor electrical performance.
Disclosure of Invention
In view of the above problems in the related art, the present invention provides an electronic device capable of improving the electrical performance of the electronic device.
According to one aspect of an embodiment of the present invention, an electronic component is provided, the electronic component comprising a carrier board comprising a plurality of rewiring layers. The multi-layer rewiring layer comprises a first reference layer, a first signal layer and a second reference layer, wherein the first reference layer, the first signal layer and the second reference layer are stacked and arranged at intervals; the first reference layer includes a first portion, a second portion spaced apart from the first portion, and a third portion connecting the first portion and the second portion, the first portion, the second portion, and the third portion defining a plurality of first openings exposing portions of the first signal layer.
In some embodiments, the first signal layer extends below the spacing between the first portion and the second portion.
In some embodiments, the first signal layer includes differential signal lines.
In some embodiments, the second reference layer has a second opening exposing a portion of the first signal layer.
In some embodiments, the third portion is a wire structure, wherein one end of the third portion of the wire structure is connected to the first portion and the other end is connected to the second portion.
In some embodiments, the plurality of first openings defined by the first portion, the second portion, and the third portion are arranged in a column.
In some embodiments, a portion of the third portion of the wire structure is connected in parallel between the first portion and the second portion, and another portion of the third portion of the wire structure is connected in parallel between the first portion and the second portion and intersects a portion of the third portion such that the plurality of first openings are grid-type openings.
In some embodiments, the electronic device further includes a second signal layer stacked on the first reference layer at intervals, the second signal layer at least partially overlapping the first signal layer through at least one first opening of the first reference layer.
In some embodiments, the third portion partially isolates the first signal layer from the second signal layer.
In some embodiments, the second signal layer is disposed in parallel and overlapping over the first signal layer.
In some embodiments, the first openings of the first reference layer include a first row of openings and a second row of openings, the first row of openings and the second row of openings are non-parallel, the first row of openings corresponds to the first signal layer, and the second row of openings corresponds to the second signal layer.
In some embodiments, the overlapping portion of the first row of openings and the second row of openings corresponds to the overlapping portion of the first signal layer and the second signal layer.
In some embodiments, the electronic device further includes a third reference layer, the third reference layer is stacked on the second signal layer at intervals, and the third reference layer has a third opening, and the third opening corresponds to the second signal layer.
Drawings
The various aspects of the invention are best understood from the following detailed description when read in connection with the accompanying drawings. It should be noted that the various components are not drawn to scale according to standard practice in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1 is a schematic view of a carrier for electronic components according to an embodiment of the invention.
Fig. 2a is a side view of a signal layer and two reference layers in an electronic device according to an embodiment of the invention.
Fig. 2b is a side view of fig. 2a according to one embodiment of the invention.
Fig. 2 c-2 e are side views of the first reference layer of fig. 2a according to other embodiments of the present invention.
Fig. 3a is a perspective view of two signal layers and three reference layers in an electronic device according to an embodiment of the invention.
FIG. 3b is a top view of each of the signal and reference layers of FIG. 3 a.
Fig. 4a is a perspective view of two signal layers and three reference layers in an electronic device according to another embodiment of the invention.
Fig. 4b is a top view of each of the signal and reference layers of fig. 4 a.
DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of elements and arrangements will be described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are in direct contact, and may also include embodiments in which additional components are formed between the first component and the second component such that the first component and the second component may not be in direct contact. Moreover, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Embodiments of the present invention provide an electronic component. Fig. 1 is a schematic view of a carrier for electronic components according to an embodiment of the invention. Referring to fig. 1, a carrier plate 10 is included in an electronic component. In some embodiments, a chip may be attached over the carrier plate 10. The carrier plate 10 includes a multi-layer redistribution layer (RDL) 18 disposed in the multi-layer dielectric layer 12. Each of the plurality of rerouting layers 18 is spaced apart from each other by a dielectric layer 12. The multi-layer redistribution layer 18 may include a first reference layer 100, a second reference layer 200, and a first signal layer 400 stacked. The first reference layer 100 is disposed above the first signal layer 400, and the second reference layer 200 is disposed below the first signal layer 400. The first reference layer 100, the second reference layer 200, and the first signal layer 400 may be spaced apart from one another by the dielectric layer 12. The multi-layer rewiring layer 18 may further include a second signal layer 500 stacked over the first reference layer 100 and a third reference layer 300 stacked over the second signal layer 500. The second signal layer 500 and the third reference layer 300 are spaced apart from each other by the dielectric layer 12. In addition, opposite sides of the first signal layer 400 and the second signal layer 500 may be provided with a reference layer 410 and a reference layer 510, respectively.
Fig. 2a is a side view of a signal layer and two reference layers in an electronic device according to an embodiment of the invention. Fig. 2b is a side view of fig. 2a according to one embodiment of the invention. Referring to fig. 1 and 2a, the first reference layer 100 has a plurality of first openings 140 exposing a portion of the first signal layer 400. In particular, referring to fig. 2a and 2b, the first reference layer 100 includes a first portion 110 and a second portion 120 that are spaced apart such that there is a space between the first portion 110 and the second portion 120. The first signal layer 400 may extend below the space between the first portion 110 and the second portion 120. The first reference layer 100 further includes a third portion 130 disposed in a space between the first portion 110 and the second portion 120 and connecting the first portion 110 and the second portion 120 to form a first opening 140 exposing a portion of the first signal layer 400 between the first portion 110 and the second portion 120. Thus, a first opening 140 exposing a portion of the first signal layer 400 is defined by the first portion 110, the second portion 120, and the third portion 130. The first openings 140 may be any number. The first opening 140 may also expose a surrounding area of the first signal layer 400.
The first signal layer 400 is responsible for electric signal transmission, and the impedance of the first signal layer 400 can influence the resistance transmission loss caused in the electric signal transmission, thereby influencing the signal power loss of the electronic element in operation. In order to control the target conductor impedance, the first opening 140 exposing a portion of the first signal layer 400 is provided in the first reference layer 100 adjacent to the first signal layer 400 by hollowing out a portion of the first reference layer 100 adjacent to the upper side of the first signal layer 400, so as to reduce the reference layer plane. The impedance of the first signal layer 400 can be made to conform to the expectations. Further, the electrical performance of the electronic component can be improved.
The first reference layer 100 may be a ground layer. The second reference layer 200 and the reference layer 410 may also be ground layers. In some embodiments, the first signal layer 400 includes differential signal lines. In some embodiments, the line width and line spacing L/S of the first signal layer 400 is less than or equal to 5 μm/5 μm (e.g., 3 μm/3 μm, 2 μm/2 μm, 1 μm/1 μm, etc.).
In addition, referring to fig. 1 and 2a, the second reference layer 200 under the first signal layer 400 may have a second opening 240 exposing a portion of the first signal layer 400. Thus, openings 140, 240 exposing portions of the first signal layer 400 are disposed above and below the first signal layer 400.
As shown in connection with fig. 2a and 2b, the structure of the second reference layer 200 may be identical to the structure of the first reference layer 100, so that only the structure of the first reference layer 100 is visible in fig. 2 b. In some embodiments, the third portion 130 of the first reference layer 100 is a wire structure having two ends connected to the first portion 110 and the second portion 120, respectively. A portion 130a of the third portion 130 is connected in parallel with each other between the first portion 110 and the second portion 120, and another portion 136 is connected in cross (non-parallel) with a portion 134 and in parallel between the first portion 110 and the second portion 120, such that the plurality of first openings 140 defined by the third portion 130 are grid-type openings. In order to make the signal transmission have perfect impedance matching, but if the upper and lower parts of the signal layer have no perfect reference layer plane, the signal layers of different layers can be mutually interfered, and the hollowed parts of the reference layer are fully distributed with grid-shaped reference layer patterns (grounding wires) so as to reduce electromagnetic interference and further improve the overall electrical performance of the rewiring layer.
Fig. 2 c-2 e are side views of the first reference layer of fig. 2a according to other embodiments of the present invention. In other embodiments, as shown in fig. 2c, 2d, and 2e, the third portion 130 of the first reference layer 100 is a wire structure having two ends respectively connected to the first portion 110 and the second portion 120. Each of the third portions 130 of the wire structure is connected in parallel between the first portion 110 and the second portion 120, and each of the first openings 140 formed is a quadrangular opening. The plurality of first openings 140 are arranged in a column. The angle θ between the third portion 130 and the first portion 110 or the second portion 120 may be any angle, the angle θ being an acute angle as shown in fig. 2c, the angle θ being an obtuse angle as shown in fig. 2d, and the angle θ being a right angle as shown in fig. 2 e.
Fig. 3a is a perspective view of two signal layers and three reference layers in an electronic device according to an embodiment of the invention. As shown in fig. 1 and 3a, the electronic device of the present invention may further include a second signal layer 500 stacked above the first reference layer 100 in addition to the first reference layer 100, the second reference layer 200 and the first signal layer 400. In some embodiments, the second signal layer 500 may include differential signal lines. In some embodiments, the line width and line spacing L/S of the second signal layer 500 is less than or equal to 5 μm/5 μm (e.g., 3 μm/3 μm, 2 μm/2 μm, 1 μm/1 μm, etc.).
In addition, a third reference layer 300 may be stacked above the second signal layer 500. The third reference layer 100 may also be a ground layer.
FIG. 3b is a top view of each of the signal and reference layers of FIG. 3 a. As shown in fig. 3a and 3b, the second signal layer 500 may overlap the first signal layer 400 through the first opening 140 of the first reference layer 100. That is, the first opening 140 is located at a position overlapping with each other between the first signal layer 400 and the second signal layer 500. In this embodiment, the second signal layer 500 is above the first signal layer 400, and the second signal layer 500 is parallel to and completely overlaps the first signal layer 400. In other embodiments, the second signal layer 500 and the first signal layer 400 may also partially overlap. The first signal layer 400 and the second signal layer 500 are isolated by the third portion 130 of the first reference layer 100. In such an embodiment, the first signal layer 400 and the second signal layer 500 may be simultaneously exposed through the first opening 140 of the first reference layer 100. That is, the first opening 140 of the first reference layer 100 corresponds to the second signal layer 500 and corresponds to the first signal layer 400 at the same time.
In addition, the third reference layer 300 above the second signal layer 500 has a third opening 340 corresponding to the second signal layer 500, the third opening 340 corresponds to the second signal layer 500, and a portion of the second signal layer 500 may be exposed through the third opening 340. The second signal layer 500 disposed between the first reference layer 100 and the third reference layer 300 may be exposed through the first opening 140 and the third opening 340 at the same time.
In the present embodiment, the first reference layer 100, the second reference layer 200 and the third reference layer 300 have similar structures, and the opening positions of the plurality of first openings 140 of the first reference layer 100 respectively correspond to the plurality of second openings 240 of the lower second reference layer 200 and the plurality of third openings 340 of the upper third reference layer 300.
Fig. 4a is a perspective view of two signal layers and three reference layers in an electronic device according to another embodiment of the invention. Fig. 4b is a top view of each of the signal and reference layers of fig. 4 a. As shown in fig. 4a and 4b, the second signal layer 500 is not parallel to the first signal layer 400, unlike the embodiment of fig. 3 a. The second signal layer 500 may overlap the first signal layer 400 through the at least one first opening 140 of the first reference layer 100. In the present embodiment, the first openings 140 of the first reference layer 100 between the first signal layer 400 and the second signal layer 500 include two rows of openings arranged in a non-parallel manner, namely, the first row of openings 144 and the second row of openings 145. The first row of openings 144 corresponds to the lower first signal layer 400 and exposes the first signal layer 400, and the second row of openings 145 corresponds to the upper second signal layer 500 and exposes the second signal layer 500. The overlapping portion of the first row of openings 144 and the second row of openings 145 corresponds to the overlapping portion of the first signal layer 400 and the second signal layer 500.
The numbers of reference layers and signal layers in the embodiments of fig. 3 a-3 b and fig. 4 a-4 b are only examples, including but not limited to the numbers described above. In other embodiments, the reference layer and the signal layer may be other numbers. Wherein, a signal layer is arranged between every two adjacent reference layers.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the disclosure. Those skilled in the art should appreciate that the invention may readily be utilized as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the invention.
Claims (13)
1. An electronic component comprising a carrier plate, the carrier plate comprising:
a plurality of rewiring layers, wherein,
the multilayer rewiring layer comprises a first reference layer, a first signal layer and a second reference layer, wherein the first reference layer, the first signal layer and the second reference layer are stacked at intervals;
the first reference layer includes a first portion, a second portion spaced apart from the first portion, and a third portion connecting the first portion and the second portion,
the first portion, the second portion, and the third portion define a plurality of first openings exposing portions of the first signal layer.
2. The electronic component according to claim 1, wherein,
the first signal layer extends below a spacing between the first portion and the second portion.
3. An electronic component according to claim 2, wherein,
the first signal layer includes differential signal lines.
4. The electronic component of claim 2, wherein the second reference layer has a second opening exposing a portion of the first signal layer.
5. The electronic component according to claim 1, wherein,
the third portion is a wire structure, wherein one end of the third portion of the wire structure is connected to the first portion, and the other end is connected to the second portion.
6. The electronic component according to claim 4, wherein,
the plurality of first openings defined by the first portion, the second portion, and the third portion are arranged in a column.
7. The electronic component according to claim 5, wherein,
a portion of the third portion of the wire structure is connected in parallel between the first portion and the second portion, and another portion of the third portion of the wire structure is connected in parallel between the first portion and the second portion and intersects the portion of the third portion such that the plurality of first openings are grid-type openings.
8. The electronic component of claim 1, further comprising:
a second signal layer is formed on the first signal layer,
the second signal layer is stacked on the first reference layer at intervals, and the second signal layer at least partially overlaps with the first signal layer through at least one first opening of the first reference layer.
9. The electronic component according to claim 8, wherein,
the third portion partially isolates the first signal layer from the second signal layer.
10. The electronic component according to claim 9, wherein,
the second signal layer is arranged above the first signal layer in parallel and overlapped.
11. The electronic component according to claim 8, wherein,
the first openings of the first reference layer include a first column of openings and a second column of openings, the first column of openings and the second column of openings being configured non-parallel,
the first row of openings corresponds to the first signal layer, and the second row of openings corresponds to the second signal layer.
12. The electronic component of claim 11, wherein the electronic component comprises a plurality of electronic components,
the overlapping position of the first row opening and the second row opening corresponds to the overlapping position of the first signal layer and the second signal layer.
13. The electronic component of claim 12, further comprising:
a third reference layer is provided on the substrate,
the third reference layer is stacked on the second signal layer at intervals, and is provided with a third opening, and the third opening corresponds to the second signal layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111552112.4A CN116266572A (en) | 2021-12-17 | 2021-12-17 | Electronic component |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111552112.4A CN116266572A (en) | 2021-12-17 | 2021-12-17 | Electronic component |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116266572A true CN116266572A (en) | 2023-06-20 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111552112.4A Pending CN116266572A (en) | 2021-12-17 | 2021-12-17 | Electronic component |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116266572A (en) |
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- 2021-12-17 CN CN202111552112.4A patent/CN116266572A/en active Pending
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