CN116264223A - Chip packaging structure and photoelectric device thereof - Google Patents

Chip packaging structure and photoelectric device thereof Download PDF

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Publication number
CN116264223A
CN116264223A CN202111524154.7A CN202111524154A CN116264223A CN 116264223 A CN116264223 A CN 116264223A CN 202111524154 A CN202111524154 A CN 202111524154A CN 116264223 A CN116264223 A CN 116264223A
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cpa
eic
substrate
pic
chip
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汤宁峰
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ZTE Corp
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ZTE Corp
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Priority to CN202111524154.7A priority Critical patent/CN116264223A/en
Priority to PCT/CN2022/125765 priority patent/WO2023109296A1/en
Publication of CN116264223A publication Critical patent/CN116264223A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/25—Arrangements specific to fibre transmission

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Optical Couplings Of Light Guides (AREA)
  • Light Receiving Elements (AREA)

Abstract

The invention provides a chip packaging structure and photoelectric equipment thereof, wherein the chip packaging structure comprises: an ASIC chip; PIC; an EIC; the ASIC chip, the PIC and the EIC are packaged in the CPA substrate, the ASIC chip is electrically connected with the EIC through the CPA substrate, and the EIC is electrically connected with the PIC through the CPA substrate. According to the technical scheme of the embodiment, the hybrid integrated package of the EIC, the PIC and the ASIC chip can be directly realized on the CPA substrate, a CPO adapter plate is omitted, the layout efficiency of the CPA is improved, the length of a transmission link of an electric signal is effectively reduced, and the electric signal transmission performance of the CPA is improved.

Description

Chip packaging structure and photoelectric device thereof
Technical Field
The present invention relates to the field of integrated chips, and in particular, to a chip package structure and an optoelectronic device thereof.
Background
SERializer/deserializer (SERializer/DESerializer, serDes) technology can effectively increase the serial communication rate, and is widely applied to switch chips and router chips. As the rate of SerDes continues to increase, the conflict between signal integrity and power consumption becomes more apparent, and the advent of Co-Packaged Optics (CPO) has solved this problem well.
Before the CPO can be applied to various devices, the CPO and application specific integrated circuit (Application Specific Integrated Circuit, ASIC) chips need to be packaged as Co-packaged components (Co-Packaged Assemble, CPA). However, CPO is a separate component, and functional chips such as optical chips (Photonic Integrated Circuit, PIC) and electrical chips (Electric Integrated Circuit, EIC) are typically integrated in CPO patch panels. In this case, as shown in fig. 1, the electrical signal between the PIC and the ASIC chip passes through the CPO adapter board, which results in a long transmission link of the electrical signal, and adversely affects signal integrity, power consumption, and bandwidth.
Disclosure of Invention
The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.
The embodiment of the invention provides a chip packaging structure and photoelectric equipment thereof, which can effectively reduce the length of a transmission link of an electric signal and improve the transmission performance of CPA.
In a first aspect, an embodiment of the present invention provides a chip package structure, including:
an ASIC chip; PIC; an EIC; the ASIC chip, the PIC and the EIC are packaged in the CPA substrate, the ASIC chip is electrically connected with the EIC through the CPA substrate, and the EIC is electrically connected with the PIC through the CPA substrate.
In a second aspect, an embodiment of the present invention provides an optoelectronic device, including:
the chip package structure of the first aspect.
The embodiment of the invention comprises the following steps: an ASIC chip; PIC; an EIC; the ASIC chip, the PIC and the EIC are packaged in the CPA substrate, the ASIC chip is electrically connected with the EIC through the CPA substrate, and the EIC is electrically connected with the PIC through the CPA substrate. According to the technical scheme of the embodiment, the hybrid integrated package of the EIC, the PIC and the ASIC chip can be directly realized on the CPA substrate, a CPO adapter plate is omitted, the layout efficiency of the CPA is improved, the length of a transmission link of an electric signal is effectively reduced, and the electric signal transmission performance of the CPA is improved.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate and do not limit the invention.
FIG. 1 is a schematic illustration of a prior art CPO packaged as a stand-alone component to a CPA;
FIG. 2 is a schematic cross-sectional view of a chip package structure according to a first embodiment of the present invention;
fig. 3 is a top view of a chip package structure according to a first embodiment of the present invention;
fig. 4 is a schematic cross-sectional view of a chip package structure according to a second embodiment of the present invention;
fig. 5 is a schematic cross-sectional view of a chip package structure according to a third embodiment of the present invention;
fig. 6 is a schematic cross-sectional view of a chip package structure according to a fourth embodiment of the present invention.
Legend description:
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
It should be noted that although functional block division is performed in the apparatus schematic, in some cases, the steps shown or described may be performed in a different order than the block division in the apparatus, or in the flowchart. The terms first, second and the like in the description, in the claims and in the above-described figures, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.
The invention provides a chip packaging structure and photoelectric equipment thereof, wherein the chip packaging structure comprises: an ASIC chip; PIC; an EIC; the CPA substrate, the ASIC chip, the PIC and the EIC are packaged in the CPA substrate, the ASIC chip is electrically connected with the EIC through the CPA substrate, and the EIC is electrically connected with the PIC through the CPA substrate. According to the technical scheme of the embodiment, the hybrid integrated package of the EIC, the PIC and the ASIC chip can be directly realized on the CPA substrate, a CPO adapter plate is omitted, the layout efficiency of the CPA is improved, the length of a transmission link of an electric signal is effectively reduced, and the electric signal transmission performance of the CPA is improved.
Referring to fig. 1, fig. 1 is a schematic diagram of a conventional CPA package structure, in which a CPO is used as an independent component, and a CPO adapter board and an ASIC chip are integrally packaged on a CPA substrate, and as known to those skilled in the art, a transmission path of an electrical signal is usually an ASIC chip-CPO adapter board-EIC-PIC, or a PIC-EIC-CPO adapter board-ASIC chip, which requires an electrical link channel between the CPO adapter board and the ASCI chip, and an electrical link channel is provided between the EIC and the PIC, so that a transmission link of the electrical signal is long, resulting in large transmission power consumption, poor signal integrity, and limited bandwidth. And, the CPO is a component with standardized size and shape, and the space utilization of the CPO adapter plate surface is lower under the condition of less EIC and PIC quantity.
In addition, some existing CPA packaging structures introduce digital signal processing (Data Signal Process, DSP) chips, in which case, the CPO needs to be packaged with the DSP chip on the CPO substrate, and an increase in the packaging layer number will cause an increase in material cost, resulting in a higher CPA cost.
In order to overcome the drawbacks of the conventional CPA package structure, embodiments of the present invention are further described below with reference to the accompanying drawings.
Referring to fig. 2, the present invention provides a chip package structure, comprising:
an ASIC chip 200; PIC400; EIC300; the CPA substrate 100, the ASIC chip 200, the PIC400, and the EIC300 are packaged in the CPA substrate 100, the ASIC chip 200 is electrically connected to the EIC300 through the CPA substrate 100, and the EIC300 is electrically connected to the PIC400 through the CPA substrate 100.
It should be noted that, in this embodiment, the CPA does not include an independent CPO any more, but the PIC400 and the EIC300 in the CPO are directly packaged together with the ASIC chip 200 in the same CPA substrate 100, so that the hybrid integration of the functional chip and the ASIC chip 200 of the CPO is realized, compared with the structure shown in fig. 1, the transmission link of the CPO adapter board is omitted, the length of the electrical link channel is effectively shortened, and the CPO is a device with a standardized size, and the size of the CPO adapter board is larger than the sizes of the EIC300 and the PIC400, so that the EIC300 and the PIC400 can be laid out more compactly with the ASIC chip 200 without the CPO adapter board, and the space utilization of the CPA substrate 100 is effectively improved.
Various embodiments of the chip package structure are described below by way of several embodiments.
Embodiment one:
in order to solve the problem of the fanout of the PIC400 fiber in the hybrid integration, the CPA substrate 100 of the embodiment adopts a large-sized glass substrate, which has excellent optical characteristics, such as insensitivity to polarization, insensitivity to wavelength, and good thermal stability, and has a certain advantage in cost compared with a silicon-based material, and the photoelectric hybrid characteristic is also superior to that of an organic material. Of course, if the actual requirement is met, silicon-based materials and organic materials may be used as the materials of the substrate, so as to adaptively adjust the coupling connection mode of the PIC400 and the optical fiber 610.
Referring to fig. 2, the CPA needs to be connected to an external component through an optical fiber 610 to obtain an input light source or an output light signal, and the external component may be any component capable of performing optical signal interaction with the CPA, and the optical connector 630 or the external light source (External Laser Source, ELS) 620 shown in fig. 2 is taken as an example in this embodiment. On the premise that the CPA substrate 100 is a glass substrate, in this embodiment, the first optical coupler 510 is disposed on the CPA substrate, and the coupling connection with the optical fiber 610 is achieved through the first optical coupler 510, where the specific structure and parameters of the first optical coupler 510 can be selected according to actual requirements, which is not limited in this embodiment.
It should be noted that the number of the first optical couplers 510 may be any number, and may be disposed at any position of the CPA substrate 100, for example, referring to fig. 3, the plurality of first optical couplers 510 may be distributed on an edge of the CPA substrate 100, or may be distributed on a front side or a back side (not shown) of the CPA substrate 100, and those skilled in the art may be motivated to adjust the positions and the number of the first optical couplers 510 according to actual needs, which are not limited herein.
It should be noted that, when the first optical coupler 510 is disposed at the edge of the CPA substrate 100 as shown on the right side in fig. 5, the first optical coupler 510 may be coupled to the CPA substrate 100 by means of horizontal coupling, and when the first optical coupler 510 is disposed on the opposite side of the CPA substrate 100 as shown on the left side in fig. 5, the first optical coupler 510 may be coupled to the CPA substrate 100 by means of vertical coupling of gratings.
In addition, as shown in fig. 2, in the case where the CPA substrate 100 is a glass substrate, the CPA substrate 100 can conduct an optical signal, for example, an input optical signal, which enters the CPA substrate 100 from the optical fiber 610 through the first optical coupler 510, and then needs to be input to the PIC400 through the CPA substrate 100 for photoelectric conversion. In order to solve this problem, in the embodiment, the first groove 131 is disposed in the CPA substrate 100, the PIC400 is inversely packaged in the first groove 131, so that the optical path side of the PIC400 can be at the same height as the CPA substrate 100, and the second optical coupler 520 is disposed between the PIC400 and the side wall of the first groove 131, so that the coupling connection between the PIC400 and the CPA substrate 100 is realized, so that the waveguide on the lower side of the CPA substrate 100 can transmit the optical signal into the PIC400, or the optical signal converted by the PIC400 is transmitted to the first optical coupler 510 through the waveguide on the lower side of the CPA substrate 100 and is output to the optical fiber 610 through the first optical coupler 510.
In the present embodiment, referring to fig. 2, the ASIC chip 200 and the EIC300 are packaged on the front surface of the CPA substrate 100, and the EIC solder balls 310 and the ASIC chip solder balls 210 may be connected by providing the first electrical link channel 111 in the CPA substrate 100. It should be noted that, the ECI300, the PIC400, and the ASIC chip 200 generally have a plurality of solder balls, and specific solder balls for connecting with each other can be selected according to actual requirements, and in this embodiment, only the connection relationship between the two chips is described, and specific solder ball selection is not in the scope of the discussion of the present embodiment, and will not be repeated in the following.
It should be noted that, referring to fig. 2, when the EIC300 is encapsulated on the front surface of the CPA substrate 100, in order to further shorten the electrical link length between the ASIC chip 200 and the PIC400, the first recess 131 is disposed on the opposite surface of the CPA substrate 100, and the PIC400 is encapsulated in the first recess 131 upside down, so that the EIC300 and the PIC400 can be disposed on the opposite surface, in which case the EIC300 and the PIC400 can be electrically connected through the first through hole 121 in the CPA substrate 100, and the electrical link between the EIC300 and the PIC400 is omitted. It should be noted that, those skilled in the art are familiar with how to realize the electrical connection between the EIC300 and the PIC400 through the first through hole, for example, the inner wall of the first through hole 121 is plated with a conductive material, and the first through hole 121 is configured as a via hole, such that the EIC solder ball 310 and the PIC solder ball 410 are soldered on two sides of the via hole respectively, which is not described herein again.
It should be noted that, the EIC300 is configured to process the electrical signal sent by the ASIC chip 200 and send the processed electrical signal to the PIC400 to drive the modulator of the PIC400 to implement photoelectric conversion, so that the closer the distance between the EIC300 and the PIC400 is, the better the quality of the electrical signal is, the higher the transmission rate is, and the smaller the power consumption required for sending the electrical signal is; in addition, after the PIC400 receives the optical signal input through the optical fiber 610, the electrical signal is obtained through photoelectric conversion and then is transmitted to the EIC300 to be subjected to transimpedance amplification, so that the electrical signal becomes a common voltage signal, and because the common weak high-speed current signal obtained through conversion of the PIC400 is very sensitive to parasitic parameters in a transmission link, the closer the distance between the EIC300 and the PIC400 is, the smaller the parasitic parameters are, the higher the transmission rate can be realized on the premise of ensuring the signal integrity, and therefore, the EIC300 and the PIC400 are arranged in a butt-joint mode, the transmission distance between the EIC300 and the PIC400 is reduced, and the electrical signal transmission device has positive effects on the input or output of the optical signal and the rate improvement aspect.
In addition, since the first groove 131 is disposed on the opposite side of the CPA substrate 100, the PIC400 is easily protruded out of the first groove 131, and the opposite side of the CPA substrate 100 is usually connected with an external component, in order to solve the problem of the mismatch in height when the CPA substrate 100 is placed, in this embodiment, the copper pillar solder balls 140 are disposed on the opposite side of the CPA substrate 100, and by adjusting the length of the copper pillar solder balls 140, the lower side of the copper pillar solder balls 140 is lower than the lower side of the PIC400, so that the connection between the copper pillar solder balls 140 and the external component is ensured when the CPA substrate 100 is placed, and of course, a connector may be used instead of the copper pillar solder balls 140, which is selected according to the actual requirements.
It should be noted that, in a CPA, generally, one ASIC chip 200 and a plurality of CPOs are included, but in this embodiment, the CPOs as independent components are broken into independent EIC300 and PIC400, and a functional chipset is formed by mixing and integrating one EIC300 and one PIC400, so, in order to meet the chip number requirement of the CPA, as shown in fig. 3, one ASIC chip 200 may be disposed in the middle of the front surface of the CPA substrate 100, and a plurality of functional chipsets are disposed around the ASIC chip 200, and the arrangement manner of the functional chipsets may be adjusted according to the actual requirement and is not limited herein.
Through the chip packaging structure of this embodiment, not only the CPO adapter plate is omitted, but also the transmission link length of the electrical signal is further shortened through the manner of oppositely pasting the EIC300 and the PIC400, and the length of the transmission link between the ASIC chip 200 and the PIC400 is effectively optimized.
Based on the above described chip package structure, the following description will be given as a simple example of the function of the CPA, and the implementation of the function of the CPA depends on the chip package structure, and this embodiment does not relate to specific method improvement.
Optical signal output:
in the CPA, the PIC400 converts a SerDes signal of a Switch (Switch) into an optical signal, so as to realize low power consumption and long distance transmission, and the embodiment is exemplified by an external component having the Switch as an input of an electrical signal.
The optical signal generated by the ELS620 sequentially passes through the optical fiber 610 and the first optical coupler 510, enters the CPA substrate 100 made of glass, and is transmitted to the second optical coupler 520 through the optical waveguide on the lower side of the opposite surface of the CPA substrate 100, and is horizontally coupled into the modulator of the PIC400.
After the ASIC chip 200 obtains the input electrical signal, the processed electrical signal enters the CPA substrate 100 through the ASIC chip solder ball 210 through recognition and processing, is transmitted to the EIC300 through the first electrical link 111, is further processed through the EIC300, and is directly transmitted to the PIC400 through the first through hole 121, so as to drive the modulator of the PIC400, and complete the modulation of the light source input by the ELS 620.
The modulated optical signal already contains the data information output by the ASIC chip 200, and the PIC400 inputs the modulated optical signal to the CPA substrate 100 through the second optical coupler 520, and then enters the optical fiber 610 through the first optical coupler 510, so as to convert the electrical signal input to the ASIC chip 200 into an optical signal and output the optical signal.
Optical signal input:
the signal light input from the optical fiber 610 enters the CPA substrate 100 through the first optical coupler 510, then enters the PIC400 through the second optical coupler 520, converts the optical signal into an electrical signal through the PIC400, then transmits the electrical signal to the EIC300 through the first through hole 121, and after the processing of transimpedance amplification in the EIC300, inputs the electrical signal to the ASIC chip 200 through the first electrical link 111, and recognizes and processes the electrical signal through the ASIC chip 200.
Embodiment two:
the chip package structure of this embodiment is similar to that of the first embodiment, and mainly has the following differences:
referring to fig. 4, in order to further package the DPS chip 700 on the front surface of the CPA substrate 100 with the electrical signal, a second electrical link 112 and a third electrical link 113 are provided in the CPA substrate 100, the DSP chip 700 is electrically connected to the EIC300 through the second electrical link 112, and the DSP chip 700 is electrically connected to the ASIC chip 200 through the third electrical link 113.
It should be noted that, the DSP chip 700 can process the electrical signal, increase the bandwidth of the CPA, improve the signal integrity, and those skilled in the art know how to select an appropriate DSP chip 700 according to actual requirements, and the specific type and parameters of the DSP chip 700 are not limited in this embodiment.
It should be noted that, the present embodiment integrates the DSP chip 700 into the CPA substrate 100, which can fully utilize the layout space of the CPA substrate 100, and reduce the number of packaging layers, thereby reducing the packaging cost.
In addition to the above differences, the other parts of the chip package structure of the present embodiment may refer to the description of the first embodiment, and the detailed description is omitted herein for simplicity.
Embodiment III:
the chip package structure of this embodiment is similar to that of the first embodiment, and mainly has the following differences:
referring to fig. 5, in this embodiment, a first groove 131 and a second groove 132 are disposed on the opposite side of the CPA substrate 100, the pic400 is inversely packaged in the first groove 131, the EIC300 is inversely packaged in the second groove 132, a fourth electrical link 114 is disposed in the CPA substrate 100, and the pic400 and the EIC300 are electrically connected through the fourth electrical link 114.
In addition, in order to realize direct driving between the EIC300 and the ASIC chip 200, the second recess 132 is disposed at a position opposite to the ASIC chip 200, that is, the EIC300 and the ASIC chip 200 are oppositely attached, and the APC substrate 100 is provided with the second through hole 122, where the EIC300 and the ASIC chip 200 are directly connected through the second through hole 122, so that a distance between the EIC300 and the ASIC chip 200 is effectively reduced, and a transmission rate is improved.
In addition, in the first embodiment, the copper pillar solder balls 140 are disposed on the opposite side of the CAP substrate 100 to solve the problem of high matching caused by the PIC400, and in the present embodiment, the connectors 150 are disposed on the opposite side of the CPA substrate 100 to solve the problem of high matching caused by the EIC300 and the PIC400.
In addition, in the present embodiment, the first optical coupler 510 adopts two modes of vertical grating coupling and horizontal coupling at the same time, for example, the first optical coupler 510 on the right side shown in fig. 5 is disposed by a horizontal coupling mode, and the first optical coupler 510 on the left side shown is disposed by a vertical grating coupling mode. Of course, in the first embodiment and the second embodiment, the first optical coupler 510 may be disposed in the same manner, and is not limited herein.
In addition to the above differences, the other parts of the chip package structure of the present embodiment may refer to the description of the first embodiment, and the detailed description is omitted herein for simplicity.
Embodiment four:
referring to fig. 6, this embodiment is similar to the first embodiment in the principle of integrating the functional chip and the ASIC chip 200 into the CPA substrate 100, but there are the following differences:
the CPA substrate 100 adopts an organic substrate, and compared with the first embodiment, the first optical coupler 510 and the second optical coupler 520 are omitted, and the optical fiber 610 is directly coupled with the PIC400, and the optical signals of the optical connector 630 and the ELS620 are directly input to the PIC400 through the optical fiber 610, because the organic substrate cannot guide light.
In addition, the PIC400, the EIC300 and the ASIC chip 200 are integrated on the front surface of the CPA substrate 100, and the PIC400 and the EIC300 are electrically connected through the fourth electrical link 114, and the EIC300 and the ASIC chip 200 are electrically connected through the first electrical link 111. Further, since there is no component on the back surface of the CPA substrate 100, the copper pillar solder balls 140 or the connectors 150 need not be provided on the back surface of the CPA substrate 100, and the CPA substrate solder balls 160 need only be provided directly.
In addition, the invention also provides optoelectronic equipment, which comprises the chip packaging structure in any one of the embodiments.
The optoelectronic device of the present embodiment may be a switch, a router, an artificial intelligence (Artificial Intelligence, AI) device, a computing fast link (Compute EXpress Link, CXL) product, or the like, which involves photoelectric conversion and implements high-speed transmission using SerDes technology.
It should be noted that, after any one of the chip package structures of the first to fourth embodiments is applied to the optoelectronic device, since the chip package structure mixes and integrates the PIC and EIC of the CPO module and the ASIC chip into the CPA substrate, the length of the transmission link between the PIC and ASIC chip is effectively reduced, the transmission performance of the CPA is effectively improved, and the packaging times are reduced, so that the low-cost, high-speed and high-integration CPA is realized, and the calculation speed or the exchange speed of the optoelectronic device is significantly improved.
While the preferred embodiment of the present invention has been described in detail, the present invention is not limited to the above embodiment, and various equivalent modifications and substitutions can be made by those skilled in the art without departing from the spirit of the present invention, and these equivalent modifications and substitutions are intended to be included in the scope of the present invention as defined in the appended claims.

Claims (10)

1. A chip package structure, comprising:
an application specific integrated circuit ASIC chip;
an optical chip PIC;
an electrical chip EIC;
and the ASIC chip, the PIC and the EIC are packaged in the CPA substrate, the ASIC chip is electrically connected with the EIC through the CPA substrate, and the EIC is electrically connected with the PIC through the CPA substrate.
2. The chip package structure according to claim 1, wherein:
the CPA substrate is connected with a first optical coupler, and the first optical coupler is used for coupling the CPA substrate and the optical fiber.
3. The chip package structure according to claim 2, wherein:
the CPA substrate is provided with a first groove, the PIC is packaged in the first groove, a second optical coupler is arranged between the PIC and the side wall of the first groove, and the second optical coupler is used for coupling the PIC and the CPA substrate.
4. A chip package structure according to claim 3, wherein:
the first groove is arranged on the reverse side of the CPA substrate, and the PIC is packaged upside down and is arranged in the first groove;
the ASIC chip and the EIC are packaged on the front surface of the CPA substrate, and the EIC and the PIC are oppositely arranged;
the CPA substrate is provided with a first electric link channel and a first through hole, the ASIC chip and the EIC are electrically connected through the first electric link channel, and the PIC and the EIC are electrically connected through the first through hole.
5. The chip package structure according to claim 3, further comprising:
the DSP chip, the ASIC chip and the EIC are packaged on the front surface of the CPA substrate;
the first groove is arranged on the back surface of the CPA substrate, the PIC is inversely packaged in the first groove, and the EIC and the PIC are oppositely arranged;
the CPA substrate is provided with a second electric link channel, a third electric link channel and a first through hole, the DSP and the EIC are electrically connected through the second electric link channel, the DSP and the ASIC chip are electrically connected through the third electric link channel, and the PIC and the EIC are electrically connected through the first through hole.
6. A chip package structure according to claim 3, wherein:
the first groove is arranged on the reverse side of the CPA substrate, and the PIC is packaged upside down and is arranged in the first groove;
the back surface of the CPA substrate is also provided with a second groove, and the EIC is inversely packaged in the second groove;
the ASIC chip is packaged on the front surface of the CPA substrate, and the ASIC chip and the EIC are oppositely arranged;
the CPA substrate is provided with a fourth electric link channel and a second through hole, the ASIC chip and the EIC are electrically connected through the second through hole, and the PIC and the EIC are electrically connected through the fourth electric link channel.
7. The chip package structure according to any one of claims 2 to 6, wherein the coupling manner of the first optical coupler and the CPA substrate includes at least one of:
horizontally coupling;
the gratings are coupled vertically flat.
8. The chip package structure according to any one of claims 2 to 6, wherein:
and the back surface of the CPA substrate is also provided with copper column solder balls or connectors.
9. The chip package structure according to claim 1, wherein:
the ASIC chip, the PIC and the EIC are packaged on the front surface of the CPA substrate, a first electric link channel and a fourth electric link channel are arranged in the CPA substrate, the ASIC chip and the EIC are electrically connected through the first electric link channel, and the PIC and the EIC are electrically connected through the fourth electric link channel.
10. An optoelectronic device comprising a chip package structure according to any one of claims 1 to 9.
CN202111524154.7A 2021-12-14 2021-12-14 Chip packaging structure and photoelectric device thereof Pending CN116264223A (en)

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