CN116259590A - Semiconductor structure and preparation method thereof - Google Patents
Semiconductor structure and preparation method thereof Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 71
- 238000002360 preparation method Methods 0.000 title abstract description 10
- 239000010410 layer Substances 0.000 claims abstract description 231
- 239000011229 interlayer Substances 0.000 claims abstract description 207
- 239000000758 substrate Substances 0.000 claims abstract description 86
- 239000003989 dielectric material Substances 0.000 claims description 47
- 238000004519 manufacturing process Methods 0.000 claims description 30
- 238000000034 method Methods 0.000 claims description 29
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- 239000000463 material Substances 0.000 description 8
- 238000002955 isolation Methods 0.000 description 5
- 230000007547 defect Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The application relates to a semiconductor structure and a preparation method thereof. The semiconductor structure includes a substrate; the first interlayer dielectric layer is positioned on the surface of the substrate; a stress release groove is formed in one side, far away from the substrate, of the first interlayer dielectric layer; the stress relief groove extends from at least a surface of the first interlayer dielectric layer away from the substrate to an interior of the first interlayer dielectric layer. The semiconductor structure can effectively release the stress in the first interlayer dielectric layer through the stress release groove, and the two ends of the first interlayer dielectric layer are prevented from driving the substrate to tilt upwards under the action of the stress.
Description
Technical Field
The present disclosure relates to semiconductor manufacturing technology, and in particular, to a semiconductor structure and a method for manufacturing the same.
Background
An interlayer dielectric layer (Inter Layer Dielectric, ILD for short) is typically formed in the semiconductor device between the metal layer and the semiconductor substrate, and between adjacent metal layers, such as an insulating film, to isolate the metal layer from the semiconductor substrate and adjacent metal layers.
The insulating film generally has good insulating property and extremely high melting point, but has a large difference between thermal expansion coefficient and semiconductor substrate and metal layer, so that the stress generated in the insulating film during the process of forming the insulating film (such as annealing process) causes the warpage defect of the obtained structure, thereby affecting the production yield and the use reliability of the semiconductor device.
Therefore, how to avoid warpage of the structure obtained in the semiconductor process is a current urgent problem to be solved.
Disclosure of Invention
Based on this, it is necessary to provide a semiconductor structure and a method for manufacturing the same, which address the shortcomings in the prior art.
In one aspect, the present application provides a semiconductor structure, including:
a substrate;
the first interlayer dielectric layer is positioned on the surface of the substrate;
a stress release groove is formed in one side, far away from the substrate, of the first interlayer dielectric layer; the stress relief groove extends from at least a surface of the first interlayer dielectric layer away from the substrate to an interior of the first interlayer dielectric layer.
In some embodiments, the stress relief groove extends through the first interlayer dielectric layer to extend from a surface of the first interlayer dielectric layer away from the substrate to the substrate surface.
In some embodiments, the semiconductor structure further comprises:
and the second interlayer dielectric layer is positioned on the surface of the first interlayer dielectric layer, which is far away from the substrate, and fills the stress release groove.
In some embodiments, the first interlayer dielectric layer has a thickness greater than or equal to
In some embodiments, the first interlayer dielectric layer has a thickness greater than or equal to
The thickness of the second interlayer dielectric layer on the first interlayer dielectric layer is greater than or equal to->
In another aspect, according to some embodiments, there is provided a method for manufacturing a semiconductor structure, including:
providing a substrate;
forming a first interlayer dielectric material layer on the surface of the substrate;
and forming a stress release groove which at least extends to the inside of the first interlayer dielectric material layer on one side of the first interlayer dielectric material layer away from the substrate, wherein the reserved first interlayer dielectric material layer is used as a first interlayer dielectric layer.
In some embodiments, the forming a stress relief groove on a side of the first interlayer dielectric material layer away from the substrate, the stress relief groove extending at least to the inside of the first interlayer dielectric material layer, includes:
the stress relief groove penetrates the first interlayer dielectric layer to extend from a surface of the first interlayer dielectric layer away from the substrate to the surface of the substrate.
In some embodiments, the first interlayer dielectric layer has a thickness greater than or equal to
In some embodiments, the method for manufacturing a semiconductor structure further includes:
and forming a second interlayer dielectric layer in the stress release groove and on the surface, far away from the substrate, of the first interlayer dielectric layer.
In some embodiments, the first interlayer dielectric layer has a thickness greater than or equal to
The thickness of the second interlayer dielectric layer on the first interlayer dielectric layer is greater than or equal to/>
In some embodiments, forming a second interlayer dielectric layer in the stress relief groove and on a surface of the first interlayer dielectric layer away from the substrate comprises:
forming a second interlayer dielectric material layer in the stress release groove and on the surface of the first interlayer dielectric layer, which is far away from the substrate;
and removing part of the second interlayer dielectric material layer with the height, and taking the reserved second interlayer dielectric material layer as the second interlayer dielectric layer.
In some embodiments, the second interlayer dielectric material layer is located on the first interlayer dielectric layer to a thickness greater than or equal to
The semiconductor structure and the preparation method thereof have the following beneficial effects:
according to the semiconductor structure and the preparation method thereof, the first interlayer dielectric layer is arranged on the surface of the substrate, and in the formation process of the first interlayer dielectric layer, stress can be generated inside the first interlayer dielectric layer due to inconsistent shrinkage rate of the first interlayer dielectric layer and the substrate, so that the obtained structure has the defect of warping. However, the stress release groove is formed in one side, far away from the substrate, of the first interlayer dielectric layer, so that the stress in the first interlayer dielectric layer can be effectively released through the stress release groove, the substrate is prevented from being driven to tilt upwards together by the two ends of the first interlayer dielectric layer under the action of the stress, the production yield and the use reliability of the first interlayer dielectric layer are improved, the electrical performance of the semiconductor structure is guaranteed, and the production yield and the use reliability of the semiconductor structure are improved.
Drawings
In order to more clearly illustrate the technical solutions of embodiments or conventional techniques of the present application, the drawings required for the descriptions of the embodiments or conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
FIG. 1 (a) is a schematic cross-sectional view of a semiconductor structure before stress relief, according to some embodiments of the present application; fig. 1 (b) is a schematic cross-sectional structure of a semiconductor structure after stress relief according to some embodiments of the present application;
FIG. 2 is a schematic cross-sectional view of a semiconductor structure according to other embodiments of the present application;
FIG. 3 is a schematic cross-sectional view of a semiconductor structure according to further embodiments of the present application;
fig. 4 is a flow chart illustrating a method for fabricating a semiconductor structure according to some embodiments of the present disclosure;
fig. 5 is a schematic flow chart of forming a second interlayer dielectric layer in a stress release groove and on a surface of a first interlayer dielectric layer away from a substrate in a method for manufacturing a semiconductor structure according to some embodiments of the present application;
fig. 6 is a schematic cross-sectional view of a substrate provided in a method for fabricating a semiconductor structure according to some embodiments of the present application;
fig. 7 is a schematic cross-sectional structure of a first interlayer dielectric material layer formed on a surface of a substrate in a method for manufacturing a semiconductor structure according to some embodiments of the present application;
fig. 8 (a) is a schematic cross-sectional structure diagram of a semiconductor structure after forming a stress relief groove and before releasing stress in the method for manufacturing a semiconductor structure according to some embodiments of the present disclosure; fig. 8 (b) is a schematic cross-sectional structure of a semiconductor structure after stress relief grooves are formed in the method for manufacturing a semiconductor structure according to some embodiments of the present application;
fig. 9 is a schematic cross-sectional structure of a second interlayer dielectric material layer formed in a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure;
fig. 10 is a schematic cross-sectional structure of a second interlayer dielectric layer formed in a method for manufacturing a semiconductor structure according to some embodiments of the present application.
Reference numerals illustrate:
1. a substrate; 2. a first interlayer dielectric layer; 20. a first interlayer dielectric material layer; 21. a stress relief groove; 3. a second interlayer dielectric layer; 30. a second interlayer dielectric material layer.
Detailed Description
In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that when an element or layer is referred to as being "on," it can be directly on the other element or layer or intervening elements or layers may be present. It will be understood that, although the terms first and second may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application; for example, the first interlayer dielectric layer may be referred to as a second interlayer dielectric layer, and similarly, the second interlayer dielectric layer may be referred to as a first interlayer dielectric layer; the first interlayer dielectric layer and the second interlayer dielectric layer are different interlayer dielectric layers.
Spatially relative terms, such as "on" and "above," may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then the description would be oriented "on" the other elements or features. Thus, the exemplary term "located on" may include both an upper and a lower orientation. Furthermore, the device may also include an additional orientation (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present application, such that variations of the illustrated shapes due to, for example, manufacturing techniques and/or tolerances are to be expected. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present application.
In one aspect, the present application provides a semiconductor structure according to some embodiments.
Referring to fig. 1 (a) and fig. 1 (b), in some embodiments, the semiconductor structure may include a substrate 1 and a first interlayer dielectric layer 2 on a surface of the substrate 1.
The side of the first interlayer dielectric layer 2, which is far from the substrate 1, is provided with a stress relief groove 21, and the stress relief groove 21 extends at least from the surface of the first interlayer dielectric layer 2, which is far from the substrate 1, to the inside of the first interlayer dielectric layer 2.
In the semiconductor structure provided in the above embodiment, the first interlayer dielectric layer 2 is disposed on the surface of the substrate 1, and in the thermal process (for example, the thermal annealing process) of the preparation process of the first interlayer dielectric layer 2, as shown in fig. 1 (a), stress is generated inside the first interlayer dielectric layer 2 due to inconsistent shrinkage rates of the first interlayer dielectric layer 2 and the substrate 1, so that the obtained structure is not molded according to the designed shape, and a warp defect occurs. However, the stress release groove 21 is disposed on the side of the first interlayer dielectric layer 2 away from the substrate 1, so that the stress in the first interlayer dielectric layer 2 can be effectively released through the stress release groove 21, as shown in the (b) diagram in fig. 1, the two ends of the first interlayer dielectric layer 2 are prevented from driving the substrate 1 to tilt upwards together under the action of the stress, thereby improving the production yield and the use reliability of the first interlayer dielectric layer 2, further being beneficial to ensuring the electrical performance of the semiconductor structure and improving the production yield and the use reliability of the semiconductor structure.
In the semiconductor structure provided in the above embodiment, the material of the substrate 1 is silicon (Si); in other embodiments, the material of the substrate 1 may further include sapphire, glass, germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium nitride (GaN), gallium arsenide (GaAs), or the like.
The material of the first interlayer dielectric layer 2 is not particularly limited in this application. As an example, the first interlayer dielectric layer 2 may include, but is not limited to, a metal layer dielectric (Inter Metal Dielectric, abbreviated as IMD) material. The metal layer dielectric material belongs to a Low-dielectric constant (Low-k) material, the generated capacitance value is lower, and the first interlayer dielectric layer 2 adopting the metal layer dielectric material can reduce the distributed capacitance so as to be beneficial to reducing the inter-layer delay time in the semiconductor structure, thereby improving the electrical property of the semiconductor structure.
As an example, as shown in fig. 1 (b), the stress relief groove 21 may extend to the inside of the first interlayer dielectric layer 2, that is: the depth of the stress relief groove 21 is smaller than the thickness of the first interlayer dielectric layer 2; furthermore, in other embodiments, as shown in fig. 2, the stress relief groove 21 may extend through the first interlayer dielectric layer 2 from the surface of the first interlayer dielectric layer 2 away from the substrate 1 to the surface of the substrate 1, that is: it is also permissible that the depth of the stress relief groove 21 is equal to the thickness of the first interlayer dielectric layer 2.
The thickness of the first interlayer dielectric layer 2 is not particularly limited in this application. As an example, as shown in fig. 1 (b), the thickness t1 of the first interlayer dielectric layer 2 may be greater than or equal to
For example, the thickness t1 of the first interlayer dielectric layer 2 may be +.>
Etc.
Referring to fig. 3, in some embodiments, the semiconductor structure may further include a second interlayer dielectric layer 3.
The second interlayer dielectric layer 3 is located on the surface of the first interlayer dielectric layer 2 away from the substrate 1, and fills the stress relief groove 21.
The thickness of the second interlayer dielectric layer 3 is not particularly limited in this application. As an example, as shown in fig. 3, the thickness t2 of the second interlayer dielectric layer 3 on the first interlayer dielectric layer 2 may be greater than or equal to
For example, the thickness t2 of the second interlayer dielectric layer 3 on the first interlayer dielectric layer 2 may be +.>
Etc. />
The material of the second interlayer dielectric layer 3 is not particularly limited in this application. As an example, the material of the second interlayer dielectric layer 3 may be the same as or similar to the material of the first interlayer dielectric layer 2, so that the first interlayer dielectric layer 2 and the second interlayer dielectric layer 3 have better consistency.
It should be noted that the semiconductor structure according to the present application may be, but is not limited to, applied to the manufacturing process of the digital isolator.
In some embodiments, the substrate 1 may include a device region and an isolation region beside the device region, and the substrate 1 may include a base and a first electrode layer on a surface of the base.
The first interlayer dielectric layer 2 is located on the surface of the isolation region of the substrate 1, and the first interlayer dielectric layer 2 is located on the surface of the first electrode layer, which is far away from the substrate.
The semiconductor structure provided in the above embodiment may be applied to a manufacturing process of a digital isolator, for example:
forming a second interlayer dielectric layer 3 in the stress release groove 21 and on the surface, far away from the substrate 1, of the first interlayer dielectric layer 2, wherein the first interlayer dielectric layer 2 and the second interlayer dielectric layer 3 can jointly form an isolation structure of the digital isolator; a second electrode layer is formed on the surface of the second interlayer dielectric layer 3 away from the substrate 1, and the first electrode layer, the isolation structure and the second electrode layer may together form a digital isolator. The digital isolator can realize mutual isolation between signals when the signals are transmitted in the semiconductor structure, thereby achieving the purposes of protecting the low-voltage module and the like.
It will be appreciated that in the semiconductor structure provided by the above embodiments, the device region may be used to provide a device structure (e.g., a transistor).
In another aspect, the present application also provides a method for manufacturing a semiconductor structure according to some embodiments.
Referring to fig. 4, in some embodiments, the method for manufacturing the semiconductor structure may include the following steps:
s100: a substrate is provided.
S200: a first interlayer dielectric material layer is formed on the surface of the substrate.
S300: and forming a stress release groove which at least extends to the inside of the first interlayer dielectric material layer on one side of the first interlayer dielectric material layer away from the substrate, wherein the reserved first interlayer dielectric material layer is used as the first interlayer dielectric layer.
According to the preparation method of the semiconductor structure, the first interlayer dielectric layer is formed on the surface of the substrate, and in the formation process of the first interlayer dielectric layer, stress can be generated inside the first interlayer dielectric layer due to inconsistent shrinkage rates of the first interlayer dielectric layer and the substrate, so that the obtained structure has the defect of warping. However, by forming the stress release groove extending into the first interlayer dielectric layer on the side, away from the substrate, of the first interlayer dielectric layer, the preparation method can effectively release the stress in the first interlayer dielectric layer, so that the two ends of the first interlayer dielectric layer drive the substrate to tilt upwards together under the action of the stress, the production yield and the use reliability of the first interlayer dielectric layer are improved, the electrical performance of the obtained semiconductor structure is ensured, and the production yield and the use reliability of the obtained semiconductor structure are improved.
In some embodiments, the method for manufacturing a semiconductor structure may further include the steps of:
and forming a second interlayer dielectric layer in the stress release groove and on the surface of the first interlayer dielectric layer far away from the substrate.
Referring to fig. 5, in some embodiments, the forming a second interlayer dielectric layer in the stress relief groove and on a surface of the first interlayer dielectric layer away from the substrate may specifically include the following steps:
s410: and forming a second interlayer dielectric material layer in the stress release groove and on the surface of the first interlayer dielectric layer far away from the substrate.
S420: and removing part of the second interlayer dielectric material layer with the height, and taking the reserved second interlayer dielectric material layer as the second interlayer dielectric layer.
It should be understood that, although the steps in the flowcharts of fig. 4 to 5 are sequentially shown as indicated by arrows, these steps are not necessarily sequentially performed in the order indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least a portion of the steps of fig. 4 to 5 may include a plurality of steps or stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of the execution of the steps or stages is not necessarily sequential, but may be performed in turn or alternately with at least a portion of the steps or stages of other steps or other steps.
In order to more clearly illustrate the preparation methods of the semiconductor structures provided in some of the above embodiments, some embodiments of the present application are understood below with reference to fig. 6 to 10.
In step S100, as shown in fig. 6, a substrate 1 is provided.
In step S200, as shown in fig. 7, a first interlayer dielectric material layer 20 is formed on the surface of the substrate 1.
In step S300, as shown in fig. 8 (a) and 8 (b), a stress relief groove 21 extending at least to the inside of the first interlayer dielectric material layer 20 is formed on the side of the first interlayer dielectric material layer 20 away from the substrate 1, and the remaining first interlayer dielectric material layer 20 serves as the first interlayer dielectric layer 2.
As an example, as shown in fig. 8 (a), the stress relief groove 21 may extend to the inside of the first interlayer dielectric layer 2, that is: the depth of the stress relief groove 21 is smaller than the thickness of the first interlayer dielectric layer 2; furthermore, in other embodiments, as shown in fig. 8 (b), the stress relief groove 21 may extend through the first interlayer dielectric layer 2 from the surface of the first interlayer dielectric layer 2 away from the substrate 1 to the surface of the substrate 1, that is: it is also permissible that the depth of the stress relief groove 21 is equal to the thickness of the first interlayer dielectric layer 2.
The thickness t1 of the first interlayer dielectric layer 2 is not particularly limited in this application. As an example, as shown in fig. 8 (b), the thickness t1 of the first interlayer dielectric layer 2 may be greater than or equal to
For example, the thickness of the first interlayer dielectric layer 2 may be +.>
Etc.
The manner of forming the stress relief groove 21 in step S300 is not particularly limited. As an example, a photolithography etching (abbreviated as Litho etching) process may be used to form the stress relief groove 21 on the first interlayer dielectric material layer 20 side, which may be specifically expressed as the following steps:
forming a photoresist layer on one side of the first interlayer dielectric material layer 20 away from the substrate 1; exposing through the corresponding mask plate, and transferring the pattern of the mask plate to the photoresist layer; exposing the photoresist layer to the region where the stress relief groove 21 is to be opened by development; forming a stress relief groove 21 by etching; the photoresist layer is removed to obtain the stress relief grooves 21.
In the step of forming the stress relief groove 21 described above, the etching involved may include, but is not limited to, dry etching, wet etching, plasma etching, or the like.
In some embodiments, as shown in fig. 9 to 10, the method for preparing a semiconductor structure may further include the following steps:
a second interlayer dielectric layer 3 is formed in the stress relief groove 21 and on the surface of the first interlayer dielectric layer 2 away from the substrate 1.
The thickness of the second interlayer dielectric layer 3 is not particularly limited in this application. As an example, the thickness t2 of the second interlayer dielectric layer 3 on the first interlayer dielectric layer 2 may be greater than or equal to
For example, the thickness t2 of the second interlayer dielectric layer 3 on the first interlayer dielectric layer 2 may be +.>
Etc.
With continued reference to fig. 9 to 10, in some embodiments, the formation of the second interlayer dielectric layer 3 in the stress relief groove 21 and on the surface of the first interlayer dielectric layer 2 away from the substrate 1 may be represented by the following steps S410 to S420:
in step S410, as shown in fig. 9, a second interlayer dielectric material layer 30 is formed in the stress relief groove 21 and on the surface of the first interlayer dielectric layer 2 away from the substrate 1.
In step S420, as shown in fig. 10, a part of the second interlayer dielectric material layer 30 is removed, and the remaining second interlayer dielectric material layer 30 is used as the second interlayer dielectric layer 3.
In step S410, it should be noted that the thickness of the second interlayer dielectric material layer 30 is not specifically limited in this application. As an example, as shown in fig. 9, the thickness t3 of the second interlayer dielectric material layer 30 on the first interlayer dielectric layer 2 may be greater than or equal to
For example, the thickness t3 of the second interlayer dielectric material layer 30 on the first interlayer dielectric layer 2 may be +.>
Etc.
The manner of removing a portion of the second interlayer dielectric material layer 30 in step S420 is not particularly limited. As an example, a chemical mechanical polishing (Chemical Mech anical Polishing, CMP) process may be used, but is not limited to, to remove a portion of the high level second interlayer dielectric material layer 30.
It should be noted that the semiconductor structures in the embodiments of the present application may be prepared by using the corresponding preparation methods of the semiconductor structures, so that technical features between the method embodiments and the structural embodiments may be replaced and supplemented with each other on the premise of not generating conflict, so that those skilled in the art can learn the technical content of the present invention.
The technical features of the above embodiments may be arbitrarily combined, and for brevity, all of the possible combinations of the technical features of the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples only represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the claims. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.
Claims (12)
1. A semiconductor structure, comprising:
a substrate;
the first interlayer dielectric layer is positioned on the surface of the substrate;
a stress release groove is formed in one side, far away from the substrate, of the first interlayer dielectric layer; the stress relief groove extends from at least a surface of the first interlayer dielectric layer away from the substrate to an interior of the first interlayer dielectric layer.
2. The semiconductor structure of claim 1, wherein the stress relief trench extends through the first interlayer dielectric layer to extend from a surface of the first interlayer dielectric layer away from the substrate to the substrate surface.
3. The semiconductor structure of claim 1, wherein the semiconductor structure further comprises:
and the second interlayer dielectric layer is positioned on the surface of the first interlayer dielectric layer, which is far away from the substrate, and fills the stress release groove.
4. The semiconductor structure of any one of claims 1-3, wherein a thickness of the first interlayer dielectric layer is greater than or equal to
5. The semiconductor structure of claim 3, wherein a thickness of the first interlayer dielectric layer is greater than or equal to
The thickness of the second interlayer dielectric layer on the first interlayer dielectric layer is greater than or equal to->
6. A method of fabricating a semiconductor structure, comprising:
providing a substrate;
forming a first interlayer dielectric material layer on the surface of the substrate;
and forming a stress release groove which at least extends to the inside of the first interlayer dielectric material layer on one side of the first interlayer dielectric material layer away from the substrate, wherein the reserved first interlayer dielectric material layer is used as a first interlayer dielectric layer.
7. The method of manufacturing a semiconductor structure according to claim 6, wherein forming a stress relief groove extending at least to an inside of the first interlayer dielectric material layer on a side of the first interlayer dielectric material layer away from the substrate comprises:
the stress relief groove penetrates the first interlayer dielectric layer to extend from a surface of the first interlayer dielectric layer away from the substrate to the surface of the substrate.
8. The method of manufacturing a semiconductor structure according to claim 6 or 7, wherein a thickness of the first interlayer dielectric layer is greater than or equal to
9. The method of manufacturing a semiconductor structure of claim 6, further comprising:
and forming a second interlayer dielectric layer in the stress release groove and on the surface, far away from the substrate, of the first interlayer dielectric layer.
10. The method of manufacturing a semiconductor structure according to claim 9, wherein a thickness of the first interlayer dielectric layer is greater than or equal to
The thickness of the second interlayer dielectric layer on the first interlayer dielectric layer is greater than or equal to->
11. The method for manufacturing a semiconductor structure according to claim 9 or 10, wherein forming a second interlayer dielectric layer in the stress release groove and on a surface of the first interlayer dielectric layer away from the substrate comprises:
forming a second interlayer dielectric material layer in the stress release groove and on the surface of the first interlayer dielectric layer, which is far away from the substrate;
and removing part of the second interlayer dielectric material layer with the height, and taking the reserved second interlayer dielectric material layer as the second interlayer dielectric layer.
12. The method of claim 11, wherein the second interlayer dielectric material layer is on the first interlayer dielectric layer and has a thickness greater than or equal to
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