CN116257104A - Improved grid driving circuit - Google Patents

Improved grid driving circuit Download PDF

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Publication number
CN116257104A
CN116257104A CN202111501266.0A CN202111501266A CN116257104A CN 116257104 A CN116257104 A CN 116257104A CN 202111501266 A CN202111501266 A CN 202111501266A CN 116257104 A CN116257104 A CN 116257104A
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charge pump
voltage
driving
power tube
unit
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林克龙
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SG Micro Beijing Co Ltd
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SG Micro Beijing Co Ltd
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
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  • Automation & Control Theory (AREA)
  • Dc-Dc Converters (AREA)

Abstract

An improved gate drive circuit, characterized by: the circuit comprises a charge pump unit, a voltage division driving unit, a driving selection unit and a power tube; the charge pump unit comprises a first-stage charge pump and a second-stage charge pump, and the first-stage charge pump and the second-stage charge pump are cascaded; the voltage division driving unit is connected with a driving stage of the secondary charge pump and is used for selectively driving the secondary charge pump based on drain voltage and reference voltage of the power tube; the driving selection unit is respectively connected with the output ends of the primary charge pump and the secondary charge pump and is used for selecting the output end of the primary charge pump or the secondary charge pump as the grid driving voltage of the power tube. The invention has simple circuit, low cost and accurate effect.

Description

Improved grid driving circuit
Technical Field
The present invention relates to the field of integrated circuits, and more particularly to an improved gate drive circuit.
Background
In the prior art, a cascade charge pump is generally used as a gate driving circuit, so as to feed back a gate voltage with a larger voltage value for a power tube under the condition of smaller input voltage, thereby realizing gate driving for the power tube.
However, in the prior art, although the effective driving of the power tube can be ensured under the condition of small input voltage, the grid voltage of the power tube is too high due to the excitation action of the charge pump when the input voltage is gradually increased to a higher state. When the gate voltage of the power tube is higher than the breakdown voltage of the power tube, the power tube cannot work normally, and the safety of a later-stage circuit is easily influenced.
On the other hand, the charge pump in the related art needs to be driven by the combined action of the clock signal and the inverter. In the normal operation process of the charge pump, the charge pump driving unit needs to continuously execute signal inversion based on the high and low levels of the clock signal, and controls the capacitors C0 and C1 to be alternately in a charge and discharge state, so that a large amount of power consumption is consumed.
In view of this problem, there is a need for an improved gate drive circuit.
Disclosure of Invention
In order to solve the defects in the prior art, the invention aims to provide an improved grid driving circuit which controls the on and off of a secondary charge pump based on the magnitude of the input voltage Vin of a power tube and selects the output of the primary charge pump or the secondary charge pump as the grid voltage of the power tube according to the magnitude.
The invention adopts the following technical scheme.
An improved gate driving circuit, wherein the circuit comprises a charge pump unit, a voltage division driving unit, a driving selection unit and a power tube; the charge pump unit comprises a first-stage charge pump and a second-stage charge pump, and the first-stage charge pump and the second-stage charge pump are cascaded; the voltage division driving unit is connected with the driving stage of the secondary charge pump and is used for selectively driving the secondary charge pump based on the drain voltage of the power tube and the reference voltage; the driving selection unit is respectively connected with the output ends of the primary charge pump and the secondary charge pump and is used for selecting the output end of the primary charge pump or the secondary charge pump as the grid driving voltage of the power tube.
Preferably, the voltage division driving unit recognizes the drain voltage Vin of the power tube; when Vin is smaller than the drive threshold voltage of the secondary charge pump, the secondary charge pump is normally driven; when Vin is greater than the drive threshold voltage of the secondary charge pump, the secondary charge pump is in a static mode.
Preferably, the voltage division driving unit includes voltage division resistors R0, R1, an error amplifier EA, a nor gate, and an inverter; the voltage dividing resistor R0 and the voltage dividing resistor R1 are connected in series and connected between the power supply voltage Vdd and the ground level, and the voltage dividing V0 of the voltage dividing resistor R0 and the voltage dividing V0 of the voltage dividing resistor R1 are connected to the non-inverting input end of the error amplifier EA; the negative phase input end of the error amplifier EA is connected with a reference voltage Vref, and the output end of the error amplifier EA is connected with one input end of the NOR gate; the other input end of the NOR gate is connected with a clock signal CLK, and the output end of the NOR gate is connected with the inverter; the output end of the inverter is connected with the driving stage of the two-stage charge pump.
Preferably, when the partial pressure V0 is taken
Figure BDA0003401721560000021
When the error amplifier EA outputs a low level, the voltage division driving unit outputs a clock signal CLK; when the partial pressure V0 takes on the value +.>
Figure BDA0003401721560000022
At this time, the error amplifier EA outputs a high level, and the divided voltage driving unit masks the clock signal CLK.
Preferably, when the drive selection unit receives the output voltages of the first-stage charge pump and the second-stage charge pump at the same time, the output voltage of the second-stage charge pump is selected as the gate voltage of the power tube; when the drive selection unit only receives the output voltage of the first-stage charge pump and does not receive the output voltage of the second-stage charge pump, the output voltage of the first-stage charge pump is selected as the gate voltage of the power tube.
Preferably, the driving selection unit comprises a first driving selection MOS tube Mp4 and a second driving selection MOS tube Mp5; the grid electrode of the first driving selection MOS tube Mp4 and the drain electrode of the second driving selection MOS tube Mp5 are in signal connection with the output end of the secondary charge pump; the drain electrode of the first driving selection MOS tube Mp4 and the grid electrode of the second driving selection MOS tube Mp5 are in signal connection with the output end of the primary charge pump; the source electrode of the first driving selection MOS tube Mp4 and the source electrode of the second driving selection MOS tube Mp5 are connected with each other and are connected with the grid electrode of the power tube.
Preferably, the charge pump unit comprises a current source, a primary charge pump, a first control unit, a secondary charge pump and a second control unit; one end of the current source is connected with the drain electrode of the power tube, and the other end of the current source is connected with the input end of the primary charge pump; the output end of the first-stage charge pump is connected with the driving stage of the second-stage charge pump; the first control unit and the second control unit are respectively connected with the control ends of the primary charge pump and the secondary charge pump.
Preferably, the first-stage charge pump and the second-stage charge pump are identical, and the first control unit is identical to the second control unit.
Preferably, the primary charge pump comprises NMOS tubes Mn0 and Mn1, PMOS tubes Mp0 and Mp1, and capacitors C0 and C1; the sources of Mn0 and Mn1 are connected with each other to serve as an input end of the first charge pump, and the sources of MP0 and MP1 are connected with each other to serve as an output end of the first charge pump; the grid electrode of Mn0, the drain electrode of Mn1, the grid electrode of Mp0, the drain electrode of Mp1 and one end of the capacitor C1 are connected; the gate of Mn1, the drain of Mn0, the gate of MP1, the drain of MP0, and one end of the capacitor C0 are connected.
Preferably, the first control unit includes inverters Inv0 and Inv1; the power supply ends of the inverters Inv0 and Inv1 are respectively connected with the drain electrode of the power tube, and the voltage Vin of the drain electrode of the power tube is adopted and grounded; the input end of the inverter Inv0 receives the clock signal CLK, and the output end is connected with the other end of the capacitor C0 and the input end of the inverter Inv1; the output terminal of the inverter Inv1 is connected to the other terminal of the capacitor C1.
Compared with the prior art, the improved grid driving circuit has the advantages that the opening and closing of the secondary charge pump can be controlled based on the input voltage Vin of the power tube, and the output of the primary charge pump or the secondary charge pump is selected as the grid voltage of the power tube. The invention has simple circuit, low cost and accurate effect.
The beneficial effects of the invention also include:
1. the improved grid driving circuit can select one-stage charge pump to work or two-stage charge pumps to work simultaneously based on the magnitude of the input voltage of the power tube. In this way, when the input voltage Vin of the power tube is too large, the number of stages of the charge pump is automatically reduced, so that the stability of the grid driving voltage is ensured.
2. In the invention, when Vin is larger, the voltage division driving unit is directly adopted, the input of the secondary charge pump is canceled, and the secondary charge pump is kept in a static state, so that the power consumption of the system is greatly reduced under the condition that Vin is larger.
Drawings
FIG. 1 is a schematic diagram of a gate driving circuit according to the prior art;
fig. 2 is a schematic circuit diagram of an improved gate driving circuit according to the present invention.
Detailed Description
The present application is further described below with reference to the accompanying drawings. The following examples are only for more clearly illustrating the technical solutions of the present invention and are not intended to limit the scope of protection of the present application.
Fig. 1 is a schematic circuit diagram of a gate driving circuit in the prior art. As shown in fig. 1, the gate driving circuit in the related art includes two cascaded charge pumps. Specifically, when the drain voltage of the power transistor MnPWR is Vin, and the drain voltage is used as an input signal of the primary charge pump, the primary charge pump outputs a voltage of 2×vin, and the voltage is used as an input signal of the secondary charge pump and then is output as 3×vin. The power tube gate voltage is seen to be 3 x vin.
Based on the circuit, although the input voltage Vin of the drain electrode of the power tube may be smaller, the gate voltage of the power tube is larger due to the action of the charge pump, so that the on-resistance of the power tube is effectively reduced, and the conduction of the power tube MnPWR and the action of supplying power to a later-stage circuit can be ensured.
On the other hand, in this process, the inverters Inv0, inv1, inv2, and Inv3 in the two-stage charge pump driving unit are always switched between high and low levels by the clock signal CLK, and the capacitor is charged and discharged accordingly, which makes the chip power consumption very high.
In order to solve the above problems, in the present invention, an improved gate driving circuit is provided.
Fig. 2 is a schematic circuit diagram of an improved gate driving circuit according to the present invention. As shown in fig. 2, an improved gate driving circuit includes a charge pump unit, a voltage dividing driving unit, a driving selection unit, and a power tube; the charge pump unit comprises a first-stage charge pump and a second-stage charge pump, wherein the first-stage charge pump and the second-stage charge pump are cascaded; the voltage division driving unit is connected with the driving stage of the secondary charge pump and is used for selectively driving the secondary charge pump based on the drain voltage of the power tube and the reference voltage; the driving selection unit is respectively connected with the output ends of the primary charge pump and the secondary charge pump and is used for selecting the output end of the primary charge pump or the secondary charge pump as the grid driving voltage of the power tube.
It can be appreciated that the present invention consumes a large amount of power in order to prevent the secondary charge pump from being still in an operating state when the input voltage Vin is excessively large, and thus, a voltage dividing driving unit is provided to stop the operating state of the secondary charge pump when the Vin is excessively large.
In addition, a selection unit is provided at the output ends of the first-stage and second-stage charge pumps, and is used for accurately selecting the end with higher output voltage as the gate voltage of the power tube MnPWR.
Preferably, the voltage division driving unit recognizes the drain voltage Vin of the power tube; when Vin is smaller than the drive threshold voltage of the secondary charge pump, the secondary charge pump is normally driven; when Vin is greater than the drive threshold voltage of the secondary charge pump, the secondary charge pump is in a static mode.
In an embodiment of the present invention, the voltage division driving unit includes an error amplifier EA, which can be used to compare the divided Vin with a preset reference voltage Vref, so as to determine the magnitude of Vin.
Preferably, the voltage division driving unit includes voltage division resistors R0, R1, an error amplifier EA, a nor gate, and an inverter; the voltage dividing resistor R0 and the voltage dividing resistor R1 are connected in series and connected between the power supply voltage Vdd and the ground level, and the voltage dividing V0 of the voltage dividing resistor R0 and the voltage dividing V0 of the voltage dividing resistor R1 are connected to the non-inverting input end of the error amplifier EA; the negative phase input end of the error amplifier EA is connected with a reference voltage Vref, and the output end of the error amplifier EA is connected with one input end of the NOR gate; the other input end of the NOR gate is connected with a clock signal CLK, and the output end of the NOR gate is connected with the inverter; the output end of the inverter is connected with the driving stage of the two-stage charge pump.
It will be appreciated that when the divided voltage V0 enters the non-inverting input of the error amplifier, it will be compared with the reference voltage Vref, and the error amplifier will determine whether its output is 1 or 0 depending on the magnitude of the two. The nor gate will determine whether to mask the clock signal CLK or not through the output of the error amplifier, or to invert the clock signal CLK and output it, and after passing through an inverter, the signal received by the secondary charge pump is either a clock signal or a static signal after the clock signal is masked, that is, a state without input.
Preferably, when the partial pressure V0 is taken
Figure BDA0003401721560000051
When the error amplifier EA outputs a low level, the driving unit outputs a clock signal CLK; when the partial pressure V0 takes on the value +.>
Figure BDA0003401721560000052
At this time, the error amplifier EA outputs a high level, and the driving unit masks the clock signal CLK.
It is understood that in the present invention, the value of the voltage division V0 is determined by the two voltage division resistors R0 and R1. Therefore, the driving threshold voltage value of the secondary charge pump can be confirmed to be V according to the formula ref (R 0 +R 1 )/R 0 . When Vin is larger than the driving threshold voltage, the clock signal is shielded, and when Vin is smaller than the driving threshold voltage, the clock signal is output.
Preferably, when the drive selection unit receives the output voltages of the first-stage charge pump and the second-stage charge pump at the same time, the output voltage of the second-stage charge pump is selected as the gate voltage of the power tube; when the drive selection unit only receives the output voltage of the first-stage charge pump and does not receive the output voltage of the second-stage charge pump, the output voltage of the first-stage charge pump is selected as the gate voltage of the power tube.
It is understood that the driving selection unit may implement selection of different voltages according to the outputs of the primary charge pump and the secondary charge pump.
Preferably, the driving selection unit comprises a first driving selection MOS tube Mp4 and a second driving selection MOS tube Mp5; the grid electrode of the first driving selection MOS tube Mp4 and the drain electrode of the second driving selection MOS tube Mp5 are in signal connection with the output end of the secondary charge pump; the drain electrode of the first driving selection MOS tube Mp4 and the grid electrode of the second driving selection MOS tube Mp5 are in signal connection with the output end of the primary charge pump; the source electrode of the first driving selection MOS tube Mp4 and the source electrode of the second driving selection MOS tube Mp5 are connected with each other and are connected with the grid electrode of the power tube.
It can be understood that the first driving selection MOS transistor and the second driving selection MOS transistor are cross-connected with each other in the present invention, so as to realize selection of the signal with higher voltage in the points a and B in fig. 2.
Preferably, the charge pump unit comprises a current source, a primary charge pump, a first control unit, a secondary charge pump and a second control unit; one end of the current source is connected with the drain electrode of the power tube, and the other end of the current source is connected with the input end of the primary charge pump; the output end of the first-stage charge pump is connected with the driving stage of the second-stage charge pump; the first control unit and the second control unit are respectively connected with the control ends of the primary charge pump and the secondary charge pump.
In an embodiment of the present invention, two stages of charge pumps may be selected as the driving circuit for the gate voltage, and in other embodiments, a cascade of more stages of charge pumps may be used as the driving circuit for the gate voltage. In addition, in the process of voltage selection, the method can also be adopted to realize the selection of the charge pumps with several stages.
The first and second control units described above are signal input circuits connected to the control terminals of the first and second charge pumps, respectively, that is, the other terminals of the capacitors. According to the function of the inverter, the clock signal can be inverted and input into the charge pump in a synchronous delay manner, so that the circulation on and off of the MOS tube in the charge pump are controlled, the switching of the charge pump between two working states is realized, and the voltage of the driving stage is doubled.
Preferably, the first-stage charge pump and the second-stage charge pump are identical, and the first control unit is identical to the second control unit.
It will be appreciated that in the present invention, two or more stages of charge pumps may be provided that are identical, in such a way that calculations and parameter design are facilitated, and the output of each stage is set to the sum of the output of the last stage and Vin.
Preferably, the primary charge pump comprises NMOS tubes Mn0 and Mn1, PMOS tubes Mp0 and Mp1, and capacitors C0 and C1; the sources of Mn0 and Mn1 are connected with each other to serve as an input end of the first charge pump, and the sources of MP0 and MP1 are connected with each other to serve as an output end of the first charge pump; the grid electrode of Mn0, the drain electrode of Mn1, the grid electrode of Mp0, the drain electrode of Mp1 and one end of the capacitor C1 are connected; the gate of Mn1, the drain of Mn0, the gate of MP1, the drain of MP0, and one end of the capacitor C0 are connected.
It can be appreciated that the charge pump of the present invention can be configured by using the scheme of the prior art, and the capacitors are respectively disposed at the two driving ends of the charge pump, so that the charge pump is driven by the alternate discharging to further boost the voltage.
Preferably, the first control unit includes inverters Inv0 and Inv1; the power supply ends of the inverters Inv0 and Inv1 are respectively connected with the drain electrode of the power tube, and the voltage Vin of the drain electrode of the power tube is adopted and grounded; the input end of the inverter Inv0 receives the clock signal CLK, and the output end is connected with the other end of the capacitor C0 and the input end of the inverter Inv1; the output terminal of the inverter Inv1 is connected to the other terminal of the capacitor C1.
It is understood that the charge pump of the present invention is driven based on an inverter and a clock signal.
Compared with the prior art, the improved grid driving circuit has the advantages that the opening and closing of the secondary charge pump can be controlled based on the input voltage Vin of the power tube, and the output of the primary charge pump or the secondary charge pump is selected as the grid voltage of the power tube. The invention has simple circuit, low cost and accurate effect.
While the applicant has described and illustrated the embodiments of the present invention in detail with reference to the drawings, it should be understood by those skilled in the art that the above embodiments are only preferred embodiments of the present invention, and the detailed description is only for the purpose of helping the reader to better understand the spirit of the present invention, and not to limit the scope of the present invention, but any improvements or modifications based on the spirit of the present invention should fall within the scope of the present invention.

Claims (10)

1. An improved gate drive circuit, characterized by:
the circuit comprises a charge pump unit, a voltage division driving unit, a driving selection unit and a power tube; wherein,,
the charge pump unit comprises a primary charge pump and a secondary charge pump, and the primary charge pump and the secondary charge pump are cascaded;
the voltage division driving unit is connected with a driving stage of the secondary charge pump and is used for selectively driving the secondary charge pump based on drain voltage and reference voltage of the power tube;
the driving selection unit is respectively connected with the output ends of the primary charge pump and the secondary charge pump and is used for selecting the output end of the primary charge pump or the secondary charge pump as the grid driving voltage of the power tube.
2. An improved gate drive circuit as claimed in claim 1, wherein:
the voltage division driving unit recognizes the drain voltage Vin of the power tube;
when Vin is smaller than the drive threshold voltage of the secondary charge pump, the secondary charge pump is normally driven;
the secondary charge pump is in a static mode when Vin is greater than a drive threshold voltage of the secondary charge pump.
3. An improved gate drive circuit as claimed in claim 2, wherein:
the voltage division driving unit comprises voltage division resistors R0 and R1, an error amplifier EA, a NOR gate and an inverter;
the voltage dividing resistors R0 and R1 are connected in series and connected between a power supply voltage Vdd and a ground level, and the voltage dividing V0 of the R0 and R1 is connected to the non-inverting input end of the error amplifier EA;
the negative phase input end of the error amplifier EA is connected with a reference voltage Vref, and the output end of the error amplifier EA is connected with one input end of the NOR gate;
the other input end of the NOR gate is connected with a clock signal CLK, and the output end of the NOR gate is connected with the inverter;
and the output end of the inverter is connected with the driving stage of the two-stage charge pump.
4. An improved gate drive circuit as claimed in claim 3, wherein:
when the partial pressure V0 takes on value
Figure FDA0003401721550000011
At this time, the error amplifier EA outputs a low level, and the divided voltage driving unit outputs a clock signal CLK;
when the partial pressure V0 takes on value
Figure FDA0003401721550000012
When the error amplifier EA outputs a high level, the divided voltage driving unit masks the clock signal CLK.
5. An improved gate drive circuit as claimed in claim 1, wherein:
when the drive selection unit receives the output voltages of the primary charge pump and the secondary charge pump at the same time, selecting the output voltage of the secondary charge pump as the grid voltage of the power tube;
and when the drive selection unit only receives the output voltage of the primary charge pump and does not receive the output voltage of the secondary charge pump, selecting the output voltage of the primary charge pump as the gate voltage of the power tube.
6. An improved gate drive circuit as set forth in claim 5 wherein:
the driving selection unit comprises a first driving selection MOS tube MP4 and a second driving selection MOS tube MP5; wherein,,
the grid electrode of the first driving selection MOS tube MP4 and the drain electrode of the second driving selection MOS tube MP5 are in signal connection with the output end of the secondary charge pump;
the drain electrode of the first driving selection MOS tube MP4 and the grid electrode of the second driving selection MOS tube MP5 are in signal connection with the output end of the primary charge pump;
the source electrode of the first driving selection MOS tube MP4 and the source electrode of the second driving selection MOS tube MP5 are connected with each other and are connected with the grid electrode of the power tube.
7. An improved gate drive circuit as claimed in claim 1, wherein:
the charge pump unit comprises a current source, a primary charge pump, a first control unit, a secondary charge pump and a second control unit; wherein,,
one end of the current source is connected with the drain electrode of the power tube, and the other end of the current source is connected with the input end of the primary charge pump;
the output end of the first-stage charge pump is connected with the driving stage of the second-stage charge pump;
the first control unit and the second control unit are respectively connected with the control ends of the primary charge pump and the secondary charge pump.
8. An improved gate drive circuit as defined in claim 7, wherein:
the first control unit and the second control unit are identical.
9. An improved gate drive circuit as claimed in claim 8, wherein:
the primary charge pump comprises NMOS (N-channel metal oxide semiconductor) tubes Mn0 and Mn1, PMOS (P-channel metal oxide semiconductor) tubes Mp0 and Mp1, and capacitors C0 and C1; wherein,,
sources of Mn0 and Mn1 are connected with each other to serve as an input end of the first charge pump, and sources of MP0 and MP1 are connected with each other to serve as an output end of the first charge pump;
the grid electrode of Mn0, the drain electrode of Mn1, the grid electrode of Mp0, the drain electrode of Mp1 and one end of the capacitor C1 are connected;
the gate of Mn1, the drain of Mn0, the gate of MP1, the drain of MP0 and one end of the capacitor C0 are connected.
10. An improved gate drive circuit as claimed in claim 9, wherein:
the first control unit includes inverters Inv0 and Inv1; wherein,,
the power supply ends of the inverters Inv0 and Inv1 are respectively connected with the drain electrode of the power tube, the voltage Vin of the drain electrode of the power tube is adopted, and the ground is grounded;
the input end of the inverter Inv0 receives the clock signal CLK, and the output end is connected with the other end of the capacitor C0 and the input end of the inverter Inv1;
the output terminal of the inverter Inv1 is connected to the other terminal of the capacitor C1.
CN202111501266.0A 2021-12-09 2021-12-09 Improved grid driving circuit Pending CN116257104A (en)

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CN202111501266.0A CN116257104A (en) 2021-12-09 2021-12-09 Improved grid driving circuit

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Application Number Priority Date Filing Date Title
CN202111501266.0A CN116257104A (en) 2021-12-09 2021-12-09 Improved grid driving circuit

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CN116257104A true CN116257104A (en) 2023-06-13

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