CN116249288B - Manufacturing method of multilayer PCB groove for embedded chip structure - Google Patents
Manufacturing method of multilayer PCB groove for embedded chip structure Download PDFInfo
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- CN116249288B CN116249288B CN202310513709.0A CN202310513709A CN116249288B CN 116249288 B CN116249288 B CN 116249288B CN 202310513709 A CN202310513709 A CN 202310513709A CN 116249288 B CN116249288 B CN 116249288B
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4697—Manufacturing multilayer circuits having cavities, e.g. for mounting components
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The invention discloses a method for manufacturing a multilayer PCB groove for embedding a chip structure, which comprises the steps of firstly, setting a corresponding bottom copper layer on an L3 layer according to the design requirement of a groove area, paving a pressed L2 layer, etching a copper window in the corresponding groove area of the L2 layer through line pattern transfer, paving a pressed L1 layer, etching the copper window in the corresponding groove area of the L1 layer through line pattern transfer, realizing groove manufacturing through a laser drilling grooving process, downwards grooving from the L1 layer through laser drilling, enabling the laser drilling to be just contacted with the copper layer of the L3 layer in depth, removing residual glue on the copper layer of the L3 layer at the bottom of the groove through Plasma equipment (Plasma), performing secondary glue removal on the copper layer of the L3 layer by using a horizontal glue removal line, cleaning the residue at the bottom of the groove, finishing solder resist manufacturing by using a stop printing process, avoiding the groove area from entering printing ink, and performing nickel-palladium-gold surface treatment on the copper layer of the L3 layer to finish manufacturing.
Description
Technical Field
The invention belongs to the technical field of PCB (printed circuit board) design and processing, and particularly relates to a method for manufacturing a groove of a multilayer PCB for embedding a chip structure.
Background
As electronic products develop toward lighter, smaller, thinner and more functional, the conventional process of embedding chips (Stackeddie) on the surface of a PCB panel gradually develops toward a process of manufacturing grooves of a PCB suitable for embedding chip structures; the embedded chip technology realizes miniaturization, light weight and multifunction, and is an important means for achieving higher packaging density, high-speed interconnection and multifunctional integration; the groove design meets the requirements of wire bonding (wirebonding, WB) and Flip Chip (FC) to realize interconnection between the embedded chip and the substrate, and the chip is embedded into the groove substrate; part of customers require that the groove area is designed copper-free on the inner wall and copper on the bottom, and nickel-palladium-gold treatment is performed to meet the requirement of embedded chip WB and the requirement of product flatness.
At present, most of the industry uses a method of mechanically forming fixed-depth grooves to manufacture grooves, but the mechanical forming precision is poor, the manufactured grooves have insufficient precision and have position deviation, and the bottom copper layer is easily damaged by fixed depth to cause uneven bottom after nickel-palladium-gold; therefore, it is necessary to provide a new technical solution to solve the problem of manufacturing the multi-layer PCB board groove embedded with the chip structure.
Disclosure of Invention
The invention aims to provide a groove manufacturing method for a multilayer PCB embedded with a chip structure, which can improve the position accuracy of the groove, realize depth control, optimize manufacturing flow and improve the quality of products.
In order to achieve the above object, the solution of the present invention is:
firstly, setting a corresponding bottom copper layer on an L3 layer according to the design requirement of a groove area, paving a laminated L2 layer, etching a copper window in the corresponding groove area of the L2 layer through circuit pattern transfer, paving a laminated L1 layer, and then comprising the following specific steps:
step 1: etching a copper window in the area of the L1 laminate corresponding to the groove through transferring the circuit pattern;
step 2: groove manufacture is realized through a laser drilling grooving process, laser drilling is downwards grooved from the L1 layer, and the depth of the laser drilling is just contacted with the copper layer of the L3 layer;
step 3: removing residual glue on the L3 copper layer at the bottom of the groove through Plasma equipment (Plasma);
step 4: performing secondary photoresist removal on the L3 copper layer by using a horizontal photoresist removing line, and cleaning scraps at the bottom of the groove;
step 5: using a stop printing process to finish the solder resist manufacture and prevent the groove area from entering ink;
step 6: and carrying out nickel-palladium-gold surface treatment on the L3 layer copper layer to finish the manufacture.
As a preferred technical scheme of the present invention, further:
in the method for manufacturing the multilayer PCB groove with the embedded chip structure, in the step 1, a subtractive process is adopted, and a copper window is etched in the area of the L1 laminate corresponding to the groove by pretreatment, film pasting, exposure, development, etching and film removing processes in sequence.
In the method for manufacturing the multilayer PCB groove with embedded chip structure, in step 2, CO is adopted 2 The laser grooving process ablates the dielectric layers between the layers L1 and L3,and forming a concave cavity, wherein the depth of the concave cavity is L1 layer to L3 layer height, and the integrity of the L3 copper layer is ensured.
In the method for manufacturing the multilayer PCB groove with embedded chip structure, in step 2, CO 2 The programming of the laser grooving process is specifically as follows:
1) Staggered addition of radium perforation with the diameter of 100um is performed in the whole area of the groove according to the hole center distance of 80um next to the edge of the groove;
2) The two rows of holes are staggered to cause the supplement of radium holes in the area where the edge cannot be processed;
3) And then a circle of radium perforation with the diameter of 101um is added next to the edge of the groove in a staggered way according to the hole center distance of 50 um.
In the method for manufacturing the multilayer PCB groove with the embedded chip structure, in the step 3, plasma equipment (Plasma) is used for removing the residual glue after laser drilling ablation on the L3 copper layer at the bottom of the groove.
In the method for manufacturing the multilayer PCB groove with the embedded chip structure, in the step 4, the horizontal chemical glue removing line is used for removing glue for the second time, and the surface with the groove design is required to be placed downwards when the residue at the bottom of the groove is cleaned.
In the method for manufacturing the multilayer PCB groove with the embedded chip structure, in the step 5, the solder mask manufacturing adopts a pattern transfer process, and the method is realized by the processes of pretreatment, blocking point screen printing, pre-baking, exposure, development and post-baking in sequence.
In the method for manufacturing the multilayer PCB groove with the embedded chip structure, in the step 6, the nickel-palladium-gold treatment meets the WB requirement, and the flatness of the copper layer at the bottom of the L3 after the nickel-palladium-gold treatment is better.
According to the method for manufacturing the multilayer PCB groove with the embedded chip structure, when the L2 layer corresponds to the groove region and etches the copper window, the sides of the copper window are designed to be respectively expanded with H2 compared with the groove region on the L3 layer, and when the L1 layer corresponds to the groove region and etches the copper window, the sides of the copper window are designed to be respectively expanded with H1 compared with the groove region on the L3 layer.
Compared with the prior art, the invention has the following beneficial effects:
(1) According to the method for manufacturing the multilayer PCB groove for embedding the chip structure, the circuit pattern is transferred to the copper window, copper of the L1 layer and the L2 layer is etched, and grooves are manufactured from the L1 layer to the L3 layer by laser;
(2) The invention provides a method for manufacturing a groove of a multilayer PCB (printed Circuit Board) for embedding a chip structure, which uses CO (carbon monoxide) 2 Ablating the dielectric layers between the L1 layer and the L3 layer in a groove forming mode by laser to form a groove, wherein the laser alignment precision is higher than the mechanical forming precision;
(3) The invention provides a method for manufacturing a groove of a multilayer PCB (printed Circuit Board) for embedding a chip structure, which uses CO (carbon monoxide) 2 The laser grooving method is beneficial to controlling the groove depth, does not damage the L3 copper layer, and ensures the flatness of the bottom of the groove;
(4) According to the manufacturing method of the multilayer PCB groove for the embedded chip structure, provided by the invention, the edge flatness of the groove area, namely the product quality is considered, meanwhile, the production efficiency is greatly improved, and the total productivity and the yield are greatly improved.
Drawings
FIG. 1 is a schematic cross-sectional view of a multilayer PCB after etching an L1 layer copper window;
FIG. 2 is a schematic cross-sectional view of a multilayer PCB after laser drilling and slotting;
FIG. 3 is a schematic cross-sectional view of a completed multi-layer PCB groove;
FIG. 4 is CO 2 Laser grooving programming schematic;
FIG. 5 is CO 2 Laser grooving edge programming schematic.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative and intended to explain the present invention and should not be construed as limiting the invention.
In the description of the present embodiment, it should be understood that the terms "upper", "lower", "TOP", "bottom", "inner", "outer", "L1", "L2", "L3", "BOT", "TOP", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are merely for convenience in describing the present embodiment and simplifying the description, and do not indicate or imply that the device or element in question must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present embodiment. In the description of the present embodiment, the meaning of "plurality" is two or more, unless otherwise specifically defined.
In this example, some data are used only to more clearly illustrate the practice of this patent, unless explicitly stated and defined otherwise, to facilitate an understanding of the reading; in the specific embodiment of the present embodiment, a 10-layer 3-level HDI product is taken as an example, and the grooves are designed to be L1-L3 layers, which should not be construed as limiting the present patent. The specific meaning of the above terms in the present embodiment can be understood by those of ordinary skill in the art according to the specific circumstances.
As shown in fig. 1-3, this embodiment provides a method for manufacturing a multilayer PCB board groove for embedding a chip structure, taking a 10-layer 3-level HDI product as an example, the top view of the groove area is a rectangular-like area of 1.5 x 2.4mm, the groove design depth is L1-L3, firstly, a corresponding bottom copper layer is set on the L3 layer according to the design requirement of the groove area, a lamination L2 layer is laid, a copper window is etched in the corresponding groove area of the L2 layer through line pattern transfer, and a lamination L1 layer is laid; it should be noted that when the L2 layer corresponds to the groove region to etch the copper window, each side of the copper window is designed to be expanded with H2 respectively compared with the groove region on the L3 layer, H2 is 50um, and when the L1 layer corresponds to the groove region to etch the copper window, each side of the copper window is designed to be expanded with H1 respectively compared with the groove region on the L3 layer, H1 is 100um;
because the situation that L2 and L1 inevitably generate movement dislocation occurs in the process of laminating the L2 layer and the L1 layer, the copper window sizes of the L2 layer and the L1 layer are designed to be amplified to a certain extent, and the situation that the copper layer leaks from the finally completed groove and is short-circuited after contacting with the embedded chip is prevented.
The specific operation after pressing L1 is as follows:
step 1: etching a copper window in the L1 laminate corresponding to the groove area through transferring the circuit pattern and according to the design size;
step 2: groove manufacture is realized through a laser drilling grooving process, laser drilling is downwards grooved from the L1 layer, and the depth of the laser drilling is just contacted with the copper layer of the L3 layer;
step 3: removing residual glue on the L3 copper layer at the bottom of the groove through Plasma equipment (Plasma);
step 4: performing secondary photoresist removal on the L3 copper layer by using a horizontal photoresist removing line, and cleaning scraps at the bottom of the groove;
step 5: using a stop printing process to finish the solder resist manufacture and prevent the groove area from entering ink;
step 6: and carrying out nickel-palladium-gold surface treatment on the L3 layer copper layer to finish the manufacture.
As a preferred technical solution of this embodiment, further:
in the step 1, a subtractive process is adopted, and a copper window is etched in the area of the L1 laminate corresponding to the groove by pretreatment, film pasting, exposure, development, etching and film removing processes.
In step 2, CO is adopted 2 The dielectric layers between the L1 layer and the L3 layer are ablated by the laser grooving process to form a concave cavity, and the depth of the concave cavity is the height of the L1 layer to the L3 layer, so that the integrity of the L3 copper layer is ensured.
As shown in fig. 4 to 5, in step 2, CO 2 The programming of the laser grooving process is specifically as follows:
1) Staggered addition of radium perforation with the diameter of 100um is performed in the whole area of the groove according to the hole center distance of 80um next to the edge of the groove;
2) The two rows of holes are staggered to cause the supplement of radium holes in the area where the edge cannot be processed;
3) Then a circle of radium perforation with the diameter of 101um is added next to the edge of the groove in a staggered way according to the hole center distance of 50 um;
at this stage CO 2 In the laser grooving process, 1) -2) is equivalent to carrying out rough trimming operation firstly, 3) then finishing is carried out on the edge as far as possible to ensure that the flatness meets the requirement, and the rough trimming and the finishing are designed by using the same program, thus distinguishing 100um from 101um, avoiding misjudgment and positioning error in equipment processing, and the method is characterized in thatThe embodiment is for example, and the final flatness that can reach is less than or equal to 25um, simultaneously takes the recess of 1.5 x 2.4mm area size as an example, and machining efficiency is 5-6 seconds/piece, has taken into account the quality and the production efficiency of product.
In the step 3, plasma equipment (Plasma) is used for removing the residual glue after laser drilling ablation on the L3 copper layer at the bottom of the groove.
In step 4, the surface with the groove design is required to be downwards placed on the plate when the horizontal chemical glue removing line is used for removing glue for the second time and cleaning the scraps at the bottom of the groove, so that the liquid remained in the concave cavity is prevented from being dried difficultly.
In the step 5, the solder mask is manufactured by adopting a pattern transfer process, and the method is realized by the processes of pretreatment, blocking point screen printing, pre-baking, exposure, development and post-baking in sequence.
In the method for manufacturing the multilayer PCB groove with the embedded chip structure, in the step 6, the nickel-palladium-gold treatment meets the WB requirement, and the flatness of the copper layer at the bottom of the L3 after the nickel-palladium-gold treatment is better.
The embodiment improves the production efficiency by 30% while considering the edge flatness of the groove area, namely the product quality, improves the total yield by 3000 square meters per month, and increases the yield by 600w per month.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Further, one skilled in the art may combine and combine the different embodiments or examples described in this specification.
While embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that variations, modifications and alternatives to the above embodiments may be made by those skilled in the art within the scope of the invention.
Claims (5)
1. A method for manufacturing a groove of a multilayer PCB for embedding a chip structure is characterized in that,
firstly, setting a corresponding bottom copper layer on an L3 layer according to the design requirement of a groove area, paving a lamination L2 layer, etching a copper window on the L2 layer corresponding to the groove area through transferring a circuit pattern, paving a lamination L1 layer, and then comprising the following specific steps:
step 1: etching a copper window in the area of the L1 laminate corresponding to the groove through transferring the circuit pattern;
step 2: groove manufacture is realized through a laser drilling grooving process, laser drilling is downwards grooved from the L1 layer, and the depth of the laser drilling is just contacted with the copper layer of the L3 layer;
step 3: removing residual glue on the L3 copper layer at the bottom of the groove through Plasma equipment (Plasma);
step 4: performing secondary photoresist removal on the L3 copper layer by using a horizontal photoresist removing line, and cleaning scraps at the bottom of the groove;
step 5: using a stop printing process to finish the solder resist manufacture and prevent the groove area from entering ink;
step 6: carrying out nickel-palladium-gold surface treatment on the L3 copper layer to finish the manufacture;
in the step 1, a subtractive process is adopted, and a copper window is etched in the L1 laminate corresponding to the groove area through pretreatment, film pasting, exposure, development, etching and film removing processes in sequence;
in the step 2, CO is adopted 2 The dielectric layers between the L1 layer and the L3 layer are ablated by a laser grooving process to form a concave cavity, wherein the depth of the concave cavity is the height of the L1 layer to the L3 layer, and the integrity of the L3 copper layer is ensured;
in the step 2, CO 2 The programming of the laser grooving process is specifically as follows:
1) Staggered addition of radium perforation with the diameter of 100um is performed in the whole area of the groove according to the hole center distance of 80um next to the edge of the groove;
2) The two rows of holes are staggered to cause the supplement of radium holes in the area where the edge cannot be processed;
3) Then a circle of radium perforation with the diameter of 101um is added next to the edge of the groove in a staggered way according to the hole center distance of 50 um;
when the L2 layer corresponds to the groove area to etch the copper window, each side of the copper window is designed to be respectively expanded with H2 compared with the groove area on the L3 layer, and when the L1 layer corresponds to the groove area to etch the copper window, each side of the copper window is designed to be respectively expanded with H1 compared with the groove area on the L3 layer.
2. The method for manufacturing the multilayer PCB board groove with the embedded chip structure of claim 1, wherein in the step 3, a Plasma device (Plasma) is used to remove the residual glue after laser drilling ablation on the L3 copper layer at the bottom of the groove.
3. The method for manufacturing the grooves of the multi-layer PCB with the embedded chip structure according to claim 1, wherein in the step 4, the surface with the groove design is required to be placed downwards when the horizontal chemical glue removing line is used for secondary glue removing and the scraps at the bottom of the groove are cleaned.
4. The method for manufacturing the multilayer PCB groove with the embedded chip structure according to claim 1, wherein in the step 5, the solder mask manufacturing is realized by adopting a pattern transfer process and sequentially passing through the processes of pretreatment, blocking point screen printing, pre-baking, exposure, development and post-baking.
5. The method for manufacturing the multi-layer PCB board with the embedded chip structure of claim 1, wherein in the step 6, the nickel-palladium-gold treatment meets WB requirements, and the L3 bottom copper layer has better flatness after the nickel-palladium-gold treatment.
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| CN202310513709.0A CN116249288B (en) | 2023-05-09 | 2023-05-09 | Manufacturing method of multilayer PCB groove for embedded chip structure |
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| CN202310513709.0A CN116249288B (en) | 2023-05-09 | 2023-05-09 | Manufacturing method of multilayer PCB groove for embedded chip structure |
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| CN116249288B true CN116249288B (en) | 2023-07-25 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101080146A (en) * | 2006-05-24 | 2007-11-28 | 富葵精密组件(深圳)有限公司 | A method for making L2 blind hole of high-density interconnection circuit board |
| CN102802360B (en) * | 2012-08-17 | 2014-10-01 | 大连太平洋电子有限公司 | Anti-breakdown isolated laser hole blasting method in PCB processing |
| CN102833952B (en) * | 2012-09-18 | 2015-05-20 | 东莞市若美电子科技有限公司 | Adhesive-removal method for printed circuit board HDI (high density interconnection) product |
| US9085826B2 (en) * | 2013-09-27 | 2015-07-21 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Method of fabricating printed circuit board (PCB) substrate having a cavity |
| JP6134914B2 (en) * | 2014-09-08 | 2017-05-31 | パナソニックＩｐマネジメント株式会社 | Laser processing method for conformal mask material |
| CN108925061A (en) * | 2018-07-31 | 2018-11-30 | 王俊 | A kind of production method of PCB soldermask layer |
| CN111542170A (en) * | 2020-04-16 | 2020-08-14 | 江苏普诺威电子股份有限公司 | Method for processing sound hole of MEMS carrier plate |
| CN114650656A (en) * | 2020-12-17 | 2022-06-21 | 北大方正集团有限公司 | Method for manufacturing printed circuit board with step groove |
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