CN116247007B - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- CN116247007B CN116247007B CN202310511164.XA CN202310511164A CN116247007B CN 116247007 B CN116247007 B CN 116247007B CN 202310511164 A CN202310511164 A CN 202310511164A CN 116247007 B CN116247007 B CN 116247007B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 146
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 53
- 238000000034 method Methods 0.000 title claims abstract description 49
- 230000005669 field effect Effects 0.000 claims abstract description 114
- 239000000758 substrate Substances 0.000 claims abstract description 85
- 239000012535 impurity Substances 0.000 claims abstract description 72
- 229910021332 silicide Inorganic materials 0.000 claims description 55
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 55
- 230000008569 process Effects 0.000 claims description 20
- 230000015572 biosynthetic process Effects 0.000 claims description 17
- 238000000137 annealing Methods 0.000 claims description 3
- 239000010408 film Substances 0.000 description 48
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 24
- 238000002955 isolation Methods 0.000 description 22
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- 238000007254 oxidation reaction Methods 0.000 description 18
- 238000010586 diagram Methods 0.000 description 16
- 238000005468 ion implantation Methods 0.000 description 15
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 12
- 229910052796 boron Inorganic materials 0.000 description 12
- 229910052751 metal Inorganic materials 0.000 description 11
- 239000002184 metal Substances 0.000 description 11
- 238000005229 chemical vapour deposition Methods 0.000 description 10
- 239000010410 layer Substances 0.000 description 10
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- 229910052785 arsenic Inorganic materials 0.000 description 9
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 9
- 229910052698 phosphorus Inorganic materials 0.000 description 9
- 239000011574 phosphorus Substances 0.000 description 9
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- 230000004888 barrier function Effects 0.000 description 8
- 229910052759 nickel Inorganic materials 0.000 description 8
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical group CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
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- 229910021334 nickel silicide Inorganic materials 0.000 description 4
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
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- 229910052721 tungsten Inorganic materials 0.000 description 4
- 238000009279 wet oxidation reaction Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
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- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 150000002222 fluorine compounds Chemical class 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 2
- PEUPIGGLJVUNEU-UHFFFAOYSA-N nickel silicon Chemical compound [Si].[Ni] PEUPIGGLJVUNEU-UHFFFAOYSA-N 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
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- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8248—Combination of bipolar and field-effect technology
- H01L21/8249—Bipolar and MOS technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
- H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
- H01L27/0727—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a method for manufacturing a semiconductor device, which comprises the following steps: a first type region forming step of implanting a first type impurity into the semiconductor substrate, and forming a first type region on a drain side of the first field effect transistor forming region, and on source and drain sides of the second field effect transistor forming region, wherein the first field effect transistor forming region is a region in which the first field effect transistor is formed, and the second field effect transistor forming region is a region in which the second field effect transistor is formed; a gate electrode forming step; and forming an electrostatic discharge protection region by implanting a second type impurity into a part of the first type region of the first field effect transistor forming region to form a second type region, wherein the second type impurity has a polarity opposite to that of the first type impurity, the interface position of the second type region is shallower than that of the first type region, and the polarity of the second type region is opposite to that of the first type region, thereby forming the electrostatic discharge protection region in the first field effect transistor forming region. The invention can reduce the manufacturing cost and improve the performance of the semiconductor device.
Description
Technical Field
The present invention relates to the field of semiconductor technology, and more particularly, to a method for manufacturing a semiconductor device.
Background
When an electrostatic Discharge (ESD) protection region is formed on the drain side of a Metal-Oxide-Semiconductor Field-Effect Transistor field effect transistor, it is necessary to cover the region where the field effect transistor is to be formed with a dedicated mask made of a photoresist in order to implant P-type impurities only into a predetermined region of the field effect transistor. In this case, in the manufacture of the semiconductor device, a dedicated mask is required for the P-type impurity implantation, and therefore, the manufacturing process and manufacturing cost of the semiconductor device are excessively high.
Disclosure of Invention
The invention provides a method for manufacturing a semiconductor device, which can manufacture the semiconductor device capable of lowering the operation start voltage of a field effect transistor without increasing the manufacturing cost.
In order to solve the technical problems, the invention is realized by the following technical scheme:
the present invention provides a method of manufacturing a semiconductor device that forms a first field effect transistor and a second field effect transistor having an electrostatic discharge protection region on a semiconductor substrate, the method comprising:
A first type region forming step of forming a first type region on a drain side of a first field effect transistor forming region, which is a region where the first field effect transistor is formed, and on a source side and a drain side of a second field effect transistor forming region, which is a region where the second field effect transistor is formed, by implanting a first type impurity into the semiconductor substrate;
a gate electrode forming step of forming a gate electrode in the first field-effect transistor forming region and the second field-effect transistor forming region, respectively; and
and forming an electrostatic discharge protection region by implanting a second type impurity into a part of the first type region of the first field effect transistor forming region to form a second type region, wherein the second type impurity has opposite polarity to the first type impurity, the interface position of the second type region is shallower than that of the first type region, and the polarity of the second type region is opposite to that of the first type region so as to form the electrostatic discharge protection region in the first field effect transistor forming region.
In one embodiment of the present invention, the method for manufacturing a semiconductor device includes a silicide block forming process of forming the silicide block in the first field effect transistor forming region, wherein the silicide block is located between the gate electrode and the first type region, and the silicide block is formed on a side away from an edge portion of the first type region.
In one embodiment of the present invention, the silicide blocks are distributed along the width direction of the semiconductor substrate.
In an embodiment of the present invention, after the gate electrode is formed, a sidewall of the gate electrode is oxidized to form a sidewall.
In an embodiment of the present invention, the silicide forming process is performed before the forming of the sidewall.
In an embodiment of the present invention, the first type region forming process is performed before the gate electrode forming process is performed.
In one embodiment of the present invention, the gate electrode forming process is performed before the electrostatic discharge protection region forming process is performed.
In one embodiment of the present invention, in the gate electrode forming process, a gate oxide film is formed on the semiconductor substrate, and the gate electrode is formed on the gate oxide film.
In one embodiment of the present invention, the semiconductor substrate is annealed before the first type region forming process is performed.
In an embodiment of the present invention, the impurity concentration of the first type region is higher than the channel impurity concentration of the gate electrode at the same depth.
As described above, the present invention provides a method for manufacturing a semiconductor device capable of manufacturing a semiconductor device in which the operation start voltage of a field effect transistor is reduced without increasing manufacturing cost.
Of course, it is not necessary for any one product to practice the invention to achieve all of the advantages set forth above at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic view of a structure of a semiconductor device according to a first embodiment of the present invention.
Fig. 2 is a diagram of a manufacturing process of the semiconductor device according to the first embodiment of the present invention.
Fig. 3 is a diagram of a manufacturing process of a semiconductor device according to a first embodiment of the present invention.
Fig. 4 is a diagram of a manufacturing process of a semiconductor device according to a first embodiment of the present invention.
Fig. 5 is a diagram of a manufacturing process of a semiconductor device according to a first embodiment of the present invention.
Fig. 6 is a diagram of a manufacturing process of the semiconductor device according to the first embodiment of the present invention.
Fig. 7 is a diagram of a manufacturing process of a semiconductor device according to a first embodiment of the present invention.
Fig. 8 is a diagram of a manufacturing process of a semiconductor device according to a first embodiment of the present invention.
Fig. 9 is a diagram of a manufacturing process of a semiconductor device according to a first embodiment of the present invention.
Fig. 10 is an enlarged view of an electrostatic discharge protection region in the semiconductor device according to the first embodiment of the present invention.
Fig. 11 is a graph of the depth relative to the upper surface of the semiconductor substrate and the impurity concentration of each impurity in the electrostatic discharge protection region of the semiconductor device according to the first embodiment of the present invention.
Fig. 12 is an enlarged view of an electrostatic discharge protection region in a semiconductor device according to a second embodiment of the present invention.
Fig. 13 is a plan view of a semiconductor device according to a second embodiment of the present invention.
Fig. 14 is a diagram of a manufacturing process of a semiconductor device according to a second embodiment of the present invention.
Fig. 15 is a diagram of a manufacturing process of a semiconductor device according to a second embodiment of the present invention.
Fig. 16 is a diagram of a manufacturing process of a semiconductor device according to a second embodiment of the present invention.
Fig. 17 is a diagram of a manufacturing process of a semiconductor device according to a second embodiment of the present invention.
Fig. 18 is a diagram of a manufacturing process of a semiconductor device according to a second embodiment of the present invention.
Fig. 19 is a diagram of a manufacturing process of a semiconductor device according to a second embodiment of the present invention.
Fig. 20 is a diagram of a manufacturing process of a semiconductor device according to a second embodiment of the present invention.
Fig. 21 is a diagram of a manufacturing process of a semiconductor device according to a second embodiment of the present invention.
In the figure: 1. a semiconductor device; 2. a semiconductor substrate; 3. shallow trench isolation structure; 4. a P-type region; 4', a second type P-type region; 5. lightly doped drain regions; 6. a source drain region; 6S, a source electrode region; 6D, a class of drain regions; 6D', a second type drain region; 7. a gate oxide film; 8. an electrostatic discharge protection region; 8', a class II electrostatic discharge protection area; 10. a first field effect transistor; 10', a second type of first field effect transistor; 10b, a first field effect transistor forming region; 10b', a second type first field effect transistor forming region; 20. a second field effect transistor; 21. a source side lightly doped drain region; 22. a drain side lightly doped drain region; 23. an N-type source region; 24. an N-type drain region; 30. a silicide block; G. and a gate electrode.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1, fig. 1 is a schematic view of a structure of a semiconductor device according to a first embodiment of the present invention. In this embodiment, a direction orthogonal to the thickness (depth) direction X of the semiconductor substrate 2 (substrate) is referred to as a width direction Y. The cross section shown in fig. 1 is continuously formed in a predetermined range in the depth direction orthogonal to the thickness direction X and the width direction Y, respectively, and the description thereof is omitted. In the following description, an example is given of the thickness and the width, but the present invention is not limited to this example, and for example, an error range such as an injection amount in a manufacturing process or the like, or an error range such as a thickness and a width of a completed product is allowed.
Referring to fig. 1, in an embodiment of the present invention, a semiconductor device 1 includes a first field effect transistor 10, and the first field effect transistor 10 is a Grounded Gate NMOS (GGNMOS). The first field effect transistor 10 includes a semiconductor substrate 2, a shallow trench isolation structure 3, a P-type region 4, a lightly doped drain region 5, a source drain region 6, a gate oxide film 7, and a gate electrode G. Wherein the semiconductor substrate 2 includes a P-well region formed by implanting P-type impurities. The shallow trench isolation structure 3 is formed by a shallow trench isolation process (shallow trench isolation, STI). One type of P-type region 4 is a first type region formed on the drain side. Lightly doped drain regions 5 are formed on the source side and the drain side, respectively. The source/drain regions 6 are second type regions formed on the source side and the drain side, respectively, and 6S in fig. 1 denotes a source/drain region on the source side and 6D denotes a source/drain region on the drain side. In this embodiment, the P-type region 4 and the source-drain region 6D are PN-combined to form an electrostatic discharge protection region 8. Wherein, in the case of electrostatic discharge (ESD) application, the type of ESD protection region 8 can be used to suppress the type of first fet 10 from malfunctioning.
Referring to fig. 1, in one embodiment of the present invention, a first field effect transistor 10 includes a drain electrode and a gate electrode G. The drain may be a drain in an NMOS transistor, may be formed in the P-type semiconductor substrate 2 or a P-well region, and may serve as an N-type impurity diffusion region. The gate electrode G is provided on the semiconductor substrate 2 with the gate oxide film 7 interposed therebetween. In the present embodiment, one type of the first field effect transistor 10 includes an N-type impurity diffusion region, and the N-type impurity diffusion region can be used as a source of an NMOS transistor. In this embodiment, the first field effect transistor 10 may be an NMOS device with a larger width. Wherein the gate electrode, source and body (body) are connected to ground, and the drain is connected to the I/O pad.
Referring to fig. 1, in one embodiment of the present invention, the semiconductor substrate 2 may be a P-type silicon substrate. The semiconductor substrate 2 includes a P-well region and a shallow trench isolation structure 3. In this case, a P-type impurity such as boron (B) is implanted into the semiconductor substrate 2 to form a P-type polar region, i.e., a P-well region. The shallow trench isolation structure 3 is a structure that partitions each region of the semiconductor substrate 2. Specifically, the shallow trench isolation structure 3 may be formed by digging a trench (trench) at a predetermined position and burying the dug trench with a silicon oxide film. Wherein the shallow trench isolation structure 3 is an insulator, so that regions on the surface of the semiconductor substrate 2 can be electrically isolated by the shallow trench isolation structure 3.
Referring to fig. 1, in an embodiment of the present invention, a P-type region 4 may be formed by implanting P-type impurities such as boron (B) into the drain side of the semiconductor substrate 2 to form a P-type high concentration region in the semiconductor layer. The P-type region 4 and a drain-side source-drain region 6D described later form a PN junction, and form an electrostatic discharge protection region 8.
Referring to fig. 1, in an embodiment of the present invention, a lightly doped drain region 5 may be formed in a low concentration doped region formed in a semiconductor layer by implanting N-type impurities such As arsenic (As) or phosphorus (P) into a source side and a drain side of a semiconductor substrate 2. By forming a low concentration region in the semiconductor layer, the P-well region depletion layer in the lower portion of the gate electrode G is enlarged, thereby reducing the electric field strength.
Referring to fig. 1, in one embodiment of the present invention, transistors may be formed at a plurality of area locations on a semiconductor substrate 2 according to the design of an integrated circuit. In this embodiment, the source-drain region 6 can be formed by implanting an N-type impurity such As arsenic (As) or phosphorus (P) into a drain region where a transistor is to be provided. The source-drain region 6D corresponds to a drain electrode, and the source-drain region 6 may be formed of polysilicon. The interface position of the source/drain region 6D is shallower than the interface position of the P-type region 4.
Referring to fig. 1, in an embodiment of the present invention, a gate oxide film 7 is disposed under a gate electrode G, and the gate oxide film is formed on a surface of a semiconductor substrate 2. By forming the gate oxide film 7, a channel region at the bottom of the gate electrode G in the semiconductor substrate 2 is insulated from the gate electrode G. So that carriers are appropriately moved between the source and the drain with a voltage applied to the gate electrode G, and a current flows in the channel region.
Referring to fig. 1, in an embodiment of the present invention, the gate electrode G may be polysilicon. And a gate electrode G is formed on the gate oxide film 7. In addition to polysilicon, a High dielectric constant insulating film/Metal Gate (MGHK) may be used for the Gate electrode G.
Referring to fig. 1 to 9, the present invention provides a process for manufacturing a semiconductor device 1 according to the above embodiment. In this embodiment, the first field effect transistor 10 may be an NMOS transistor with a grounded gate. The second field effect transistor 20 is in particular a medium voltage PMOS transistor. In fig. 2 to 9, illustrations of other PMOS transistors or NMOS transistors formed on the semiconductor substrate 2, except for the first field-effect transistor 10 and the second field-effect transistor 20, are omitted.
Referring to fig. 1 and 2, in step S10, a shallow trench isolation structure 3 is formed on a semiconductor substrate 2. The shallow trench isolation structure 3 is a structure for partitioning each region of the semiconductor substrate 2, and the shallow trench isolation structure 3 may be formed by recessing (trench) at a predetermined position and filling the trench with a silicon oxide film. Wherein the shallow trench isolation structure 3 is an insulator to electrically isolate regions formed on the semiconductor substrate 2. In this embodiment, an oxide film having a thickness of, for example, 8nm may be formed on the upper surface of the semiconductor substrate 2 by a thermal oxidation method. And the oxide film is located outside the area where the shallow trench isolation structure 3 is located. The thermal oxidation method may be any of dry oxidation, wet oxidation, and steam oxidation.
Referring to fig. 1 and 2, in an embodiment of the present invention, P-type impurities such As boron (B) are then implanted into the first fet forming region 10B, and N-type impurities such As arsenic (As) or phosphorus (P) are implanted into the second fet forming region 20B. Then, the semiconductor substrate 2 is annealed, a P-well region is formed in the first field effect transistor forming region 10b of one type, and an N-well region is formed in the second field effect transistor forming region 20 b.
Referring to fig. 3, in an embodiment of the present invention, P-type impurities are implanted into the first field effect transistor forming region 10b and the second field effect transistor forming region 20b, the P-type region 4 is formed in the first field effect transistor forming region 10b, and the source-side lightly doped drain region 21 and the drain-side lightly doped drain region 22 are formed in the second field effect transistor forming region 20b in step S12 shown in fig. 3. In the present embodiment, in the semiconductor substrate 2, the upper surface of the semiconductor substrate 2 is masked (masked) with a photoresist. Also, the masked surface of the semiconductor substrate 2 does not include the P-type region 4, the source-side lightly doped drain region 21, and the drain-side lightly doped drain region 22. Wherein a P-type region 4 is formed on the drain side of a first fet formation region 10 b. The source-side lightly doped drain region 21 and the drain-side lightly doped drain region 22 are formed in the second field effect transistor forming region 20 b. The source-side lightly doped drain region 21 and the drain-side lightly doped drain region 22 are first type regions.
Referring to fig. 3, in an embodiment of the present invention, impurities are then implanted into the semiconductor substrate 2 in a state where the upper surface of the semiconductor substrate 2 is masked, a P-type region 4 is formed in a first field effect transistor forming region 10b, and a source-side lightly doped drain region 21 and a drain-side lightly doped drain region 22 are formed in a second field effect transistor forming region 20 b. In the present embodiment, the ion implantation energy for forming the P-type region 4, the source-side lightly doped drain region 21, and the drain-side lightly doped drain region 22 is, for example, 60keV, and the ion implantation dose is, for example, 3e+13 orders of magnitude/cm 2 . And the P-type region 4, the source-side lightly doped drain region 21, and the drain-side lightly doped drain region 22 can be formed by implanting P-type impurities such as boron (B) into the P-well region.
Referring to fig. 4 to 9, in an embodiment of the present invention, next, in step S14 shown in fig. 4, a mask for forming the source side lightly doped drain region 21 and the drain side lightly doped drain region 22 is removed. And a mask is formed on the surface of the semiconductor substrate 2 except for the region where the gate electrode G is to be provided in each of the first field-effect-tube forming region 10b and the second field-effect-tube forming region 20b of one type. And a gate oxide film 7 is formed in a region where the gate electrode G is to be provided by a thermal oxidation method. The thermal oxidation method may be any of dry oxidation, wet oxidation, and steam oxidation. In fig. 4 to 9, illustration of the thin oxide film on the upper surface of the semiconductor substrate 2 is omitted.
Referring to fig. 4, in an embodiment of the present invention, after forming the gate oxide film 7, the region where the gate electrode G is to be formed is patterned by photolithography in the first field effect transistor forming region 10b and the second field effect transistor forming region 20b, respectively. Then, after removing the mask formed by the photoresist, polysilicon for the gate electrode G is deposited in a design region on the upper surface of the semiconductor substrate 2 by chemical vapor deposition (Chemical Vapor Deposition, CVD).
Referring to fig. 5, in an embodiment of the present invention, next, in step S16 shown in fig. 5, N-type impurities such As arsenic (As) are implanted into the first field effect transistor forming regions 10b in a state where the upper surface of the semiconductor substrate 2 is masked except for the lightly doped drain region 5, thereby forming the lightly doped drain region 5 on the source side and the drain side. The lightly doped drain region 5 forming a first field effect transistor forming region 10b of the type has an ion implantation energy of, for example, 10keV and an ion implantation dose of, for example, 1e+15 orders of magnitude/cm 2 . By making the ion implantation energy of the impurity in the lightly doped drain region 5 lower than that of the impurity in the P-type region 4, the interface position in the lightly doped drain region 5 on the source side and the drain side is formed shallower than that of the P-type region 4.
Referring to fig. 4 and 6, in an embodiment of the present invention, next, in step S18 shown in fig. 6, sidewalls SW are formed at the first field effect transistor forming region 10b and the second field effect transistor forming region 20b, and the gate electrodes G, and source regions 6S and drain regions 6D are formed at the first field effect transistor forming region 10 b. In this embodiment, an oxide film may be formed at each gate electrode G by chemical vapor deposition of tetraethyl silicate (Tetraethyl orthosilicate, TEOS). And anisotropically etching is performed to form an oxide film only on the side walls of the gate electrodes G. The oxide film formed on the sidewall of each gate electrode G serves as a sidewall SW. In addition to tetraethyl silicate, a silicon nitride (SiN) film formed by a chemical vapor deposition method may be stacked during film formation.
Referring to fig. 1 and 6, in an embodiment of the present invention, next, except for the source region 6S, the drain region 6D, and the source and drain regions 6 in the first field effect transistor forming region 10b, the upper surfaces of the semiconductor substrate 2 and the shallow trench isolation structure 3 are masked, and N-type impurities such as phosphorus (P) are respectively implanted into the P-type region 4 and the lightly doped drain region 5 to form the N-type source region 6S and the drain region 6D. To form the lightly doped drain region 5 in the first field effect transistor forming region 10b of the type having an ion implantation energy of, for example, 15keV and an ion implantation dose of, for example, 7e+15 orders/cm 2 . In the present embodiment, the interface position of the source region 6S and the drain region 6D is shallow in the interface position of the P-type region 4, and the interface position of the source region 6S and the drain region 6D is, for example, 0.1 μm deep with respect to the upper surface of the semiconductor substrate 2.
Referring to fig. 1, 6 and 7, in an embodiment of the present invention, next, in step S20 shown in fig. 7, the upper surface of the semiconductor substrate 2 is masked except for the N-type source region 23 and the N-type drain region 24 in the second field effect transistor forming region 20B and the source-drain region 6 in the other PMOS transistor forming region, and P-type impurities such as boron (B) are implanted into the source-side lightly doped drain region 21 and the drain-side lightly doped drain region 22 to form the N-type source region 23 and the N-type drain region 24.
Referring to fig. 6 to 8, in an embodiment of the present invention, next, in step S22 shown in fig. 8, after removing the mask formed by the photoresist, the semiconductor substrate 2 is annealed to activate impurities such As boron (B), arsenic (As), and phosphorus (P) implanted into each region. On the drain side of the first field-effect transistor formation region 10b, the connection interface between the P-type region 4 and the drain region 6D is PN-bonded to form an electrostatic discharge protection region (ESD protection region) 8.
Referring to fig. 6 to 9, in an embodiment of the present invention, next, in step S24 shown in fig. 9, in order to silicide at the designed position in the first field effect transistor forming region 10b, a photoresist is coated on the oxide film to form a pattern. Then, the oxide film is removed only in a predetermined region where the silicide region is formed by wet etching using hydrofluoric acid (HF) and/or chemical dry etching, and an opening of the oxide film is formed. Next, nickel (Ni) is deposited on the upper surface of the semiconductor substrate 2 by a physical vapor deposition (Physical Vapour Deposition, PVD) method such as sputtering. After forming the nickel (Ni) film, an annealing treatment is performed to change the junction of silicon (Si) and nickel (Ni) into nickel silicide (NiSi). Next, nickel (Ni) is removed from the upper surface of the semiconductor substrate 2 except for the source, drain and gate regions. The silicide such as nickel silicide is formed by a general silicide process flow as described above.
Referring to fig. 9, in an embodiment of the present invention, an interlayer insulating film is formed on the conductive layer or electrodes and wirings in the first field effect transistor forming region 10b and the second field effect transistor forming region 20 b. Then, a contact hole (contact) is formed by dry etching, and the contact hole can be used to connect the source, drain, gate, and electrodes of the substrate, respectively. In this embodiment, a barrier metal is formed on the inner wall surface of the contact hole to prevent silicide such as nickel silicide from being exposed to the environment of fluorine compound and fluorine (F) when tungsten (W) is filled into the contact hole. The barrier metal is, for example, a thin film made of titanium (Ti) or titanium nitride (TiN), and may be formed by sputtering or chemical vapor deposition. The film thickness of the barrier metal may be, for example, 10nm to 15nm. After the formation of the barrier metal, tungsten (W) or copper (Cu) is filled into the contact hole to form a contact portion, and metal wiring or the like is laid on the upper surface of the contact portion to form each electrode of the source electrode, the drain electrode, and the gate electrode. The semiconductor device 1 according to the present embodiment is manufactured through the above process flow.
Referring to fig. 6, 10 and 11, fig. 10 is an enlarged view of an esd protection region in the semiconductor device according to the first embodiment. Fig. 11 is a graph showing the depth relative to the upper surface of the semiconductor substrate and the impurity concentration of each impurity in the electrostatic discharge protection region of the semiconductor device. In the graph shown in fig. 11, the horizontal axis represents the depth of the electrostatic discharge protection region with respect to the upper surface of the semiconductor substrate 2. The vertical axis represents the impurity concentration of each impurity in the electrostatic discharge protection region. In fig. 11, the solid line indicates the impurity concentration of arsenic (As), the broken line indicates the impurity concentration of phosphorus (P), and the dash-dot line indicates the impurity concentration of boron (B).
Referring to fig. 6, 10 and 11, in one embodiment of the present invention, a contact portion of a drain electrode is formed on the semiconductor substrate 2 at the drain side of a first field effect transistor 10. A drain region 6D and a P-type region 4 are formed at the bottom of the contact portion of the drain electrode, and a PN junction is formed at the interface of each region. Wherein a type of drain region 6D and a type of P-type region 4 serve as a type of esd protection region 8.
Referring to FIGS. 10 and 11, according to FIG. 11, regarding the impurity concentration of each impurity, the impurity concentration in the PN junction interface of the one type drain region 6D and the one type P region 4 is, for example, 1e+18/cm, in the vicinity of the depth of 0.1 μm 3 In a higher state.
Referring to fig. 4 and 6, and fig. 10 and 11, in an embodiment of the present invention, in the PN junction interface between the P-type region 4 and the drain-type region 6D, the impurity concentration of each impurity is in a higher state. In the present embodiment, the impurity concentration of the P-type region 4 of one type is higher than the impurity concentration at the same depth under the gate electrode G. Therefore, the depletion layer in the PN junction interface of the one type drain region 6D and the one type P-type region 4 is narrower than the depletion layer in the PN junction interface between the one type drain region 6D and the P-well region of the semiconductor substrate 2.
Referring to fig. 10 and 11, in an embodiment of the present invention, the voltage for causing avalanche breakdown is reduced by forming a narrower depletion layer at the PN junction interface between the drain region 6D and the P-type region 4. Thus, parasitic bipolar transistors in the P-well region of a first type of field effect transistor 10 are turned on by a low voltage. Further, since the parasitic bipolar transistor is turned on, a large current flows between the one type of drain region 6D and the source region 6S, and the ESD surge applied to the I/O pad is released to the ground (ground potential), whereby the ESD surge can be prevented from being applied to the circuit connected to the one type of first field effect transistor 10.
Referring to fig. 1, 12 and 13, in another embodiment of the present invention, fig. 12 is an enlarged view of an esd protection area in a semiconductor device according to a second embodiment. Fig. 13 is a plan view of the semiconductor device according to the second embodiment. As shown in fig. 12 and 13, the first field effect transistor 10 of the present embodiment is different from the first embodiment in that the manufacturing process of the present embodiment includes a process of disposing a silicide block 30 between the gate electrode G and the second P-type region 4' in the width direction, wherein the silicide block 30 is an insulator. The silicide block 30 may use an insulating layer when forming the sidewall SW. The silicide block 30 is formed in the design region between the gate electrode and the edge of the P-type region together with the sidewall SW by using photolithography and etching.
Referring to fig. 12 and 13, in another embodiment of the present invention, silicide blocks 30 are formed at positions away from the edge portions of the two-type P-type regions 4'. In the present embodiment, the distance between the second P-type region 4' and the silicide block 30 is not limited to a specific value, but may be adjusted according to the impurity diffusion requirement of the thermal oxidation process. In the thermal oxidation process, boron (B) as a P-type impurity does not diffuse under the silicide block 30. In this embodiment, the distance between the second type P-type region 4' and the silicide block 30 is, for example, 50nm.
Referring to fig. 1, 12 to 21, in another embodiment of the present invention, the difference between the present embodiment and the first embodiment is that silicide blocks 30 are provided at positions away from the edge portions of the two-type P-type regions 4' in the manufacturing process of the semiconductor device 1. In this embodiment, the manufacturing process of the semiconductor device 1 in the first embodiment is the same as that of the first embodiment except that silicide blocks are provided at positions distant from the edge portions of the second-type P-type regions 4'. In this embodiment, steps different from those in the first embodiment will be mainly described. The same reference numerals as those of the first embodiment are used for the same structures as those of the first embodiment. In fig. 14 to 21, illustration of other PMOS transistors or NMOS transistors formed on the semiconductor substrate 2 except for the first field-effect transistor 10 and the second field-effect transistor 20 is omitted.
Referring to fig. 1 and 14, in another embodiment of the present invention, in step S30 shown in fig. 14, a shallow trench isolation structure 3 is formed on a semiconductor substrate 2. The shallow trench isolation structure 3 is a structure for partitioning each region of the semiconductor substrate 2, and the shallow trench isolation structure 3 may be formed by recessing (trench) at a predetermined position and filling the trench with a silicon oxide film. Wherein the shallow trench isolation structure 3 is an insulator to electrically isolate regions formed on the semiconductor substrate 2. In this embodiment, an oxide film having a thickness of, for example, 8nm may be formed on the upper surface of the semiconductor substrate 2 by a thermal oxidation method. And the oxide film is located outside the area where the shallow trench isolation structure 3 is located. The thermal oxidation method may be any of dry oxidation, wet oxidation, and steam oxidation.
Referring to fig. 1 and 14, in another embodiment of the present invention, P-type impurities such As boron (B) are implanted into the second type first fet forming region 10B', and N-type impurities such As arsenic (As) or phosphorus (P) are implanted into the second fet forming region 20B. Then, the semiconductor substrate 2 is annealed, a P-well region is formed in the second type first field effect transistor forming region 10b', and an N-well region is formed in the second field effect transistor forming region 20 b.
Referring to fig. 1, 12 and 15, in another embodiment of the present invention, next, in step S32 shown in fig. 15, P-type impurities are implanted into the second type first fet forming region 10b ' and the second fet forming region 20b, the second type P-type region 4' is formed in the second type first fet forming region 10b ', and the source side lightly doped drain region 21 and the drain side lightly doped drain region 22 are formed in the second fet forming region 20 b. In the present embodiment, in the semiconductor substrate 2, the upper surface of the semiconductor substrate 2 is masked (masked) with a photoresist. Also, the masked surface of the semiconductor substrate 2 does not include the source-side lightly doped drain region 21 and the drain-side lightly doped drain region 22 in the second field effect transistor formation region 20 b. Wherein a P-type region 4 is formed on the drain side of a first fet formation region 10 b. The source-side lightly doped drain region 21 and the drain-side lightly doped drain region 22 are formed in the second field effect transistor forming region 20 b. In this embodiment, the mask is sized to ensure that the process window size of the mask is such that silicide blocks 30 are formed between the gate electrode G and the P-type regions 4'.
Referring to fig. 1 and 15, in another embodiment of the present invention, next, in a state where the upper surface of the semiconductor substrate 2 is masked, impurities are implanted into the semiconductor substrate 2, the second type P-type region 4 'is formed in the second type first fet forming region 10b', and the source side lightly doped drain region 21 and the drain side lightly doped drain region 22 are formed in the second fet forming region 20 b. In the present embodiment, the ion implantation energy for forming the two types of P-type regions 4', the source side lightly doped drain region 21 and the drain side lightly doped drain region 22 is, for example, 60keV, and the ion implantation dose is, for example, 3e+13 orders of magnitude/cm 2 . And the P-type region 4, the source-side lightly doped drain region 21, and the drain-side lightly doped drain region 22 can be formed by implanting P-type impurities such as boron (B) into the P-well region.
Referring to fig. 1 and 12, and fig. 16 to 21, in another embodiment of the present invention, next, in step S34 shown in fig. 16, a mask for forming the source side lightly doped drain region 21 and the drain side lightly doped drain region 22 is removed. And a mask is formed on the surface of the semiconductor substrate 2 except for the area where the gate electrode G is to be provided, in each of the second type first field effect transistor forming area 10b' and the second field effect transistor forming area 20 b. And a gate oxide film 7 is formed in a region where the gate electrode G is to be provided by a thermal oxidation method. The thermal oxidation method may be any of dry oxidation, wet oxidation, and steam oxidation. In fig. 16 to 21, illustration of a thin oxide film on the upper surface of the semiconductor substrate 2 is omitted. In this embodiment, the mask is sized to ensure that the process window size of the mask is such that silicide blocks 30 are formed between the gate electrode G and the P-type regions 4'.
Referring to fig. 16, in another embodiment of the present invention, after forming the gate oxide film 7, the region where the gate electrode G is to be formed is patterned by photolithography in the second type of first field effect transistor forming region 10b' and the second field effect transistor forming region 20b, respectively. Then, after removing the mask formed by the photoresist, polysilicon for the gate electrode G is deposited in a design region on the upper surface of the semiconductor substrate 2 by a chemical vapor deposition method.
Referring to fig. 1 and 17, in another embodiment of the present invention, next, in step S36 shown in fig. 17, N-type impurities such As arsenic (As) are implanted into the second type first field effect transistor forming regions 10b' in a state where the upper surface of the semiconductor substrate 2 except the lightly doped drain region 5 is masked, thereby forming the lightly doped drain region 5 on the source side and the drain side. The lightly doped drain region 5 forming the second type first field effect transistor forming region 10b' has an ion implantation energy of, for example, 10keV and an ion implantation dose of, for example, 1e+15 orders of magnitude/cm 2 . By making the ion implantation energy of the impurity in the lightly doped drain region 5 lower than that of the impurity in the second type P-type region 4', the interface position in the lightly doped drain region 5 on the source side and the drain side is made shallower than that of the second type P-type region 4'.
Referring to fig. 12, 16 and 18, in another embodiment of the present invention, next, in step S38 shown in fig. 18, side walls SW are formed at the second type first fet forming region 10b ' and the second fet forming region 20b, and the gate electrodes G, and source regions 6S and drain regions 6D ' are formed at the second type first fet forming region 10b '. In this embodiment, the oxide film may be formed at each gate electrode G by chemical vapor deposition of tetraethyl silicate. And anisotropically etching is performed to form an oxide film only on the side walls of the gate electrodes G. The oxide film formed on the sidewall of each gate electrode G serves as a sidewall SW. In addition to tetraethyl silicate, a silicon nitride (SiN) film formed by a chemical vapor deposition method may be stacked during film formation.
Referring to figures 1 and 18 of the drawings,in another embodiment of the present invention, next, the upper surfaces of the semiconductor substrate 2 and the shallow trench isolation structure 3 are masked except for the source region 6S, the drain region 6D 'and the source and drain regions 6 in the second type first field effect transistor formation region 10b' and the other NMOS transistor formation region, and N-type impurities such as phosphorus (P) are respectively injected into the second type P-type region 4 'and the lightly doped drain region 5 to form an N-type source region 6S and a second type drain region 6D'. To form the lightly doped drain region 5 in the second type first FET forming region 10b', the ion implantation energy is, for example, 15keV, and the ion implantation dose is, for example, 7e+15 orders/cm 2 . In the present embodiment, the interface position of the source region 6S and the second type drain region 6D ' is shallow to the interface position of the second type P-type region 4', and the interface position of the source region 6S and the second type drain region 6D ' is deep to, for example, 0.1 μm with respect to the upper surface of the semiconductor substrate 2. In this embodiment, the upper surface of the second type P-type region 4 'is PN-bonded with the lower surface portion of the second type drain region 6D'.
Referring to fig. 1 and 19, in another embodiment of the present invention, next, in step S40 shown in fig. 19, the upper surface of the semiconductor substrate 2 is masked and P-type impurities such as boron (B) are implanted into the source side lightly doped drain region 21 and the drain side lightly doped drain region 22, except for the N-type source region 23 and the N-type drain region 24 in the second field effect transistor forming region 20B and the source drain region 6 in the other PMOS transistor forming region, to form the N-type source region 23 and the N-type drain region 24.
Referring to fig. 1, 12 and 20, in another embodiment of the present invention, next, in step S42 shown in fig. 20, after removing the mask formed by the photoresist, the semiconductor substrate 2 is annealed to activate impurities such As boron (B), arsenic (As), phosphorus (P) and the like implanted into each region. On the drain side of the first fet formation region 10', the junction interface between the second P-type region 4' and the second drain region 6D 'is PN-joined to form the second esd protection region 8'.
Referring to fig. 12 and 20, in another embodiment of the present invention, tetraethyl silicate is deposited by chemical vapor deposition, and the oxide film on the upper surface of the second-type first fet forming region 10b 'is patterned by etching, and silicide blocks 30 are formed at positions spaced apart from the channel-side edge portions of the second-type P-type region 4' by a predetermined distance in the width direction.
Referring to fig. 1, 12 and 21, in another embodiment of the present invention, next, in step S44 shown in fig. 21, in order to silicide at the designed position in the second-type first fet forming region 10b', a photoresist is coated on the oxide film to form a pattern. Then, the oxide film is removed only in a predetermined region where the silicide region is formed by wet etching using hydrofluoric acid (HF) and/or chemical dry etching, and an opening of the oxide film is formed. Next, nickel (Ni) is deposited on the upper surface of the semiconductor substrate 2 by a physical vapor deposition method such as sputtering. After forming the nickel (Ni) film, an annealing treatment is performed to change the junction of silicon (Si) and nickel (Ni) into nickel silicide (NiSi). Next, nickel (Ni) is removed from the upper surface of the semiconductor substrate 2 except for the source, drain and gate regions. The silicide such as nickel silicide is formed by a general silicide process flow as described above.
Referring to fig. 1, 12, 14 and 21, in another embodiment of the present invention, the silicide block 30 is then removed by anisotropic etching. In the present embodiment, in the second type of the first fet forming regions 10b', the silicided regions on the upper surface of the semiconductor substrate 2 are silicide regions, such as source, drain and gate regions. The non-silicided region of the upper surface of the semiconductor substrate 2 is a non-silicide region due to the coverage by the oxide film. In step S42 described above, the region having the silicide block 30 is formed as a region covered with the oxide film on the upper surface of the semiconductor substrate 2 after the silicide block 30 is removed, and is thus also a non-silicide region. Wherein the non-silicide regions function as ballasting (ballast) resistors. Therefore, the silicide block 30 is formed at a position distant from the edge portion of the second-type P-type region 4', and diffusion of impurities of the second-type P-type region 4' into the non-silicide region can be suppressed.
Referring to fig. 18 and 21, in another embodiment of the present invention, an interlayer insulating film is formed on the conductive layer or electrodes and wirings in the second type first field effect transistor forming region 10b' and the second field effect transistor forming region 20 b. Then, a contact hole (contact) is formed by dry etching, and the contact hole can be used to connect the source, drain, gate, and electrodes of the substrate, respectively. In this embodiment, a barrier metal is formed on the inner wall surface of the contact hole to prevent silicide such as nickel silicide from being exposed to the environment of fluorine compound and fluorine (F) when tungsten (W) is filled into the contact hole. The barrier metal is, for example, a thin film made of titanium (Ti) or titanium nitride (TiN), and may be formed by sputtering or chemical vapor deposition. The film thickness of the barrier metal may be, for example, 10nm to 15nm. After the formation of the barrier metal, tungsten (W) or copper (Cu) is filled into the contact hole to form a contact portion, and metal wiring or the like is laid on the upper surface of the contact portion to form each electrode of the source electrode, the drain electrode, and the gate electrode. The semiconductor device 1 according to the present embodiment is manufactured through the above process flow.
Referring to fig. 1, 12 and 21, in another embodiment of the present invention, a non-silicide region is formed between the second P-type region 4' and the gate electrode G in the manufacturing process, and the non-silicide region may be used as a ballast resistor. Wherein the silicide block 30 is formed at a position distant to the edge portion of the second type P-type region 4'. Whereby non-silicide regions are also formed at locations remote from the second type P-type regions 4'. Therefore, diffusion of impurities of the second type P-type region 4' into the non-silicide region can be suppressed.
Referring to fig. 21, in another embodiment of the present invention, the function of the ballast resistor in the first field effect transistor 10 (ESD protection circuit) is described below, wherein the first field effect transistor 10 includes the second ESD protection region 8'. It is assumed that a plurality of ESD protection circuits (GGNMOS) are connected to the same input-output pad, and that the plurality of ESD protection circuits (GGNMOS) are connected in parallel. When each ESD protection circuit is not provided with a non-silicide region, that is, when the ballast resistor in the present embodiment is not provided, a large current may flow only through a specific ESD protection circuit. In this case, a plurality of ESD protection circuits cannot operate, and a large current flows through the ESD protection circuits capable of operating at a low voltage, and thus a part of the ESD protection circuits may be damaged.
Referring to fig. 21, in another embodiment of the present invention, in the case where each ESD protection circuit has a ballast resistor, a current flowing from an input/output pad in a semiconductor device can be uniformly flown to a plurality of ESD protection circuits connected in parallel, so that a voltage drop of the potential of the input/output pad is suppressed, and all the ESD protection circuits can be operated normally. In addition, when the present embodiment is applied to an analog circuit, the ac characteristics can be provided with sufficient margin for various specifications.
Referring to fig. 1 to 21, a method for manufacturing a semiconductor device according to various embodiments of the present invention includes forming a first field effect transistor having an esd protection region and a second field effect transistor on a semiconductor substrate. In the present invention, a method for manufacturing a semiconductor device includes: and a first type region forming step of forming a first type region on a drain side of a first field effect transistor forming region which is a region for forming the first field effect transistor, and forming first type regions on a source side and a drain side of a second field effect transistor forming region which is a region for forming the second field effect transistor, respectively, by implanting a first type impurity into the semiconductor substrate. And a gate electrode forming step of forming a gate electrode G in the first field effect transistor forming region and the second field effect transistor forming region, respectively. And an electrostatic discharge protection region forming step of forming an electrostatic discharge protection region in the first field effect transistor forming region by implanting a second type impurity having a polarity opposite to that of the first type impurity into a part of the first type region of the first field effect transistor forming region, and forming a second type region having an interface position shallower than that of the first type region and having a polarity opposite to that of the first type region.
As shown in fig. 1 to 21, according to the method of manufacturing a semiconductor device of the present invention, in the step of forming the first type region in the second field effect transistor formation region, the first type impurity is injected into the predetermined region on the drain side in the first field effect transistor formation region, thereby forming the first type region in the electrostatic discharge protection region of the first field effect transistor. Thus, the electrostatic discharge protection region can be formed in the first field effect transistor without adding a mask or a manufacturing process. That is, the electrostatic discharge protection region can be formed in the first field-effect transistor without increasing the manufacturing cost, and avalanche breakdown is likely to occur in the PN junction surface (interface between the first type region and the second type region) in the electrostatic discharge protection region, so that the operation start voltage of the field-effect transistor can be reduced.
Referring to fig. 1 to 21, the method for manufacturing a semiconductor device according to the present invention includes a silicide block forming step of forming a silicide block between the gate electrode and the first type region in the width direction of the semiconductor substrate in the first field effect transistor forming region so as to be away from an edge portion of the first type region.
Referring to fig. 1 to 21, according to the method of manufacturing a semiconductor device of the present invention, a silicide block is formed between the gate electrode and the first type region in the width direction of the semiconductor substrate in the first field effect transistor formation region so as to be away from an edge portion of the first type region. This can suppress diffusion of impurities contained in the first type region to the lower portion of the silicide block. Therefore, the yield in manufacturing the semiconductor device can be improved.
Referring to fig. 1 to 21, in the semiconductor device and the method for manufacturing the same according to the present invention, the first type region forming step is a step preceding the gate electrode forming step. Thus, the first type region having a deep junction can be formed without considering penetration by ion implantation of polysilicon at the time of gate electrode formation.
The embodiments of the invention disclosed above are intended only to help illustrate the invention. The embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best understand and utilize the invention. The invention is limited only by the claims and the full scope and equivalents thereof.
Claims (8)
1. A method of manufacturing a semiconductor device in which a first field-effect transistor and a second field-effect transistor having an electrostatic discharge protection region are formed over a semiconductor substrate, comprising:
a first type region forming step of forming a first type region on a drain side of a first field effect transistor forming region, which is a region where the first field effect transistor is formed, and on a source side and a drain side of a second field effect transistor forming region, which is a region where the second field effect transistor is formed, by implanting a first type impurity into the semiconductor substrate;
a gate electrode forming step of forming a gate electrode in the first field-effect transistor forming region and the second field-effect transistor forming region, respectively;
an electrostatic discharge protection region forming step of implanting a second type impurity into a part of the first type region of the first field effect transistor forming region to form a second type region, wherein the second type impurity is shallower than the first type region and the second type region is opposite to the first type region in polarity, so as to form the electrostatic discharge protection region in the first field effect transistor forming region, wherein the second type region is a source-drain region, and the first type region and the second type region are PN-combined to form the electrostatic discharge protection region; and
And a silicide block forming step of forming the silicide block in the first field effect transistor forming region, wherein the silicide block is located between the gate electrode and the first type region in a horizontal direction, and the silicide block is formed on a side away from an edge portion of the first type region, and the silicide block is distributed in a width direction of the semiconductor substrate.
2. The method of manufacturing a semiconductor device according to claim 1, wherein after the gate electrode is formed, a sidewall of the gate electrode is oxidized to form a sidewall.
3. The method of manufacturing a semiconductor device according to claim 2, wherein the silicide formation step is performed before the formation of the side wall.
4. The method according to claim 1, wherein the first-type region forming step is performed before the gate electrode forming step is performed.
5. The method of manufacturing a semiconductor device according to claim 1, wherein the gate electrode forming step is performed before the electrostatic discharge protection region forming step is performed.
6. The method according to claim 1, wherein in the gate electrode forming step, a gate oxide film is formed over the semiconductor substrate, and the gate electrode is formed over the gate oxide film.
7. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate is subjected to an annealing treatment before the first-type region forming process is performed.
8. The method for manufacturing a semiconductor device according to claim 1, wherein an impurity concentration of the first type region is higher than a channel impurity concentration of the gate electrode at the same depth.
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