CN116230507B - Method for preparing semiconductor structure - Google Patents
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- CN116230507B CN116230507B CN202310512076.1A CN202310512076A CN116230507B CN 116230507 B CN116230507 B CN 116230507B CN 202310512076 A CN202310512076 A CN 202310512076A CN 116230507 B CN116230507 B CN 116230507B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02115—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material being carbon, e.g. alpha-C, diamond or hydrogen doped carbon
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
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Abstract
The invention provides a preparation method of a semiconductor structure, after an SOC film is formed on a silicon wafer, at least one heating process and a cooling process are alternately executed, wherein the heating process is to heat the SOC film to a first preset temperature and keep the first preset time, the cooling process is to cool the SOC film to a second preset temperature and keep the second preset time, the first preset temperature is greater than the second preset temperature, and the first preset temperature and the second preset temperature are both 155-185 ℃, and because the SOC material has better fluidity and can not harden in 155-185 ℃, the heating and cooling are circulated in the temperature interval, so that the filling capacity of the SOC material can be improved; and then the SOC film is hardened and the subsequent photoetching process is carried out, so that the focal depth of the photoetching process can be ensured and the linewidth uniformity and the roundness of photoetching can be improved at the same time because the surface evenness of the SOC film is improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a preparation method of a semiconductor structure.
Background
As semiconductor fabrication process nodes advance, there is a demand for smaller line widths and smaller cycles for pattern sizes, requiring multiple patterning techniques, i.e., photolithography-etch-photolithography-etch processes, under conditions of insufficient resolution of the lithography machine. In the multilayer patterning technology, the SOC (spin-on carbon) film is one of the most critical layers, which can play 2 roles in the photolithography-etching process, namely as a fill-up coating for photolithography and as a hard mask barrier layer (HardMask) for etching, which requires repeated photolithography-etching about 3 to 4 times in the preparation of a film structure such as a device connection layer (CT layer).
The preparation process of the device connection layer pattern comprises forming a dielectric layer on a substrate, etching the dielectric layer to form a deep trench (depth about 2500 angstrom) exposing a source/drain region in the substrate, and then etching the dielectric layer to form a hole (depth about 700 angstrom) exposing a gate electrode on the substrate, wherein the hole exposing the gate electrode is usually formed by etching for 2 times (for example, half is formed by first etching and half is formed by first etching) due to the limitation of the photolithography process. Photolithography of holes is very sensitive to Depth of Focus (DoF), and small changes in Focus tend to cause significant changes in critical dimensions (Critical Dimension, CD), so the DoF of holes is typically very small (e.g., 60 nm). The SOC film fills up holes or grooves in the silicon wafer, so that a smooth surface is provided for the photoresist, and a process window of the DoF can be well ensured.
However, when the holes are formed by the first etching, deep grooves are formed at the periphery of the holes, when the holes are formed by the second etching, not only the deep grooves are formed at the periphery of the holes, but also the holes formed after the first hole etching, when the holes are coated, the surface flatness of the silicon wafer is poor, the patterns are dense, the depth-to-width ratio of the holes and the deep grooves is large, so that the SOC can not completely fill the grooves and the holes, and therefore, the formed SOC film cannot meet the requirement of focal depth due to uneven surface.
Disclosure of Invention
The invention aims to provide a preparation method of a semiconductor structure, which is used for solving the problem that an SOC material in the prior art cannot fill holes or deep grooves well.
In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor structure, comprising:
providing a silicon wafer, and coating an SOC material on the silicon wafer to form an SOC film;
alternately executing at least one heating process and a cooling process, wherein the heating process is to heat the SOC film to a first preset temperature and keep the first preset time, the cooling process is to cool the SOC film to a second preset temperature and keep the second preset time, the first preset temperature is greater than the second preset temperature, and the first preset temperature and the second preset temperature are both 155-185 ℃;
baking the SOC film to harden the SOC film; and
and forming a photoresist layer on the SOC film and performing a photolithography process.
Optionally, the first predetermined temperature is 175 ℃ to 185 ℃, and the second predetermined temperature is 155 ℃ to 165 ℃.
Optionally, the first predetermined time and the second predetermined time are 17 s-23 s.
Optionally, when the heating process and the cooling process are performed, the silicon wafer rotates at a predetermined rotation speed.
Optionally, the preset rotating speed is 90 r/min-110 r/min.
Optionally, the silicon wafer changes the rotation direction every third preset time when rotating.
Optionally, the third predetermined time is 17 s-23 s.
Optionally, before the heating process is performed, the method further includes:
heating the SOC film to a third preset temperature which is less than the first preset temperature and is 155-165 ℃, and keeping for a third preset time which is 17-23 s.
Optionally, the silicon wafer is provided with a plurality of holes and/or grooves, the holes and the grooves extend from the surface of the silicon wafer into the silicon wafer, and the SOC film covers the surface of the silicon wafer and fills at least part of the depths of the holes and the grooves.
Optionally, the step of baking the SOC film to harden the SOC film includes:
heating the SOC film to 235-255 ℃ and maintaining for 55-75 s; the method comprises the steps of,
the SOC film was cooled to room temperature.
The invention provides a preparation method of a semiconductor structure, after an SOC film is formed on a silicon wafer, at least one heating process and a cooling process are alternately executed, wherein the heating process is to heat the SOC film to a first preset temperature and keep the first preset time, the cooling process is to cool the SOC film to a second preset temperature and keep the second preset time, the first preset temperature is greater than the second preset temperature, and the first preset temperature and the second preset temperature are both 155-185 ℃, and because the SOC material has better fluidity and can not harden in 155-185 ℃, the heating and cooling are circulated in the temperature interval, so that the filling capacity of the SOC material can be improved; and then the SOC film is hardened and the subsequent photoetching process is carried out, so that the focal depth of the photoetching process can be ensured and the linewidth uniformity and the roundness of photoetching can be improved at the same time because the surface evenness of the SOC film is improved.
Drawings
Fig. 1 is a flowchart of a method for manufacturing a semiconductor structure according to an embodiment of the present invention;
fig. 2a to fig. 5b are schematic structural diagrams corresponding to corresponding steps of a method for manufacturing a semiconductor structure according to a first embodiment of the present invention;
FIG. 6 is a graph showing the comparison of temperature curves between the SOC films after forming the SOC films and until hardening the SOC films in the prior art according to the first embodiment of the present invention;
FIG. 7a is a schematic diagram of a pattern profile of a hole formed by post-lithography using a prior art scheme according to an embodiment of the present invention;
FIG. 7b is a schematic diagram of a pattern outline of a hole formed by post-lithography according to the embodiment of the present invention;
fig. 8 to 10 are schematic structural diagrams corresponding to corresponding steps of a method for manufacturing a semiconductor structure according to a second embodiment of the present invention;
wherein, the reference numerals are as follows:
100-a substrate; 200-gate structure; 300-dielectric layer; 301-grooves; 302/303-holes; 401/402-SOC membrane.
Detailed Description
Specific embodiments of the present invention will be described in more detail below with reference to the drawings. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
Fig. 1 is a flowchart of a method for manufacturing a semiconductor structure according to this embodiment. As shown in fig. 1, the method for preparing the semiconductor structure includes:
step S100: providing a silicon wafer, and coating an SOC material on the silicon wafer to form an SOC film;
step S200: alternately executing at least one heating process and a cooling process, wherein the heating process is to heat the SOC film to a first preset temperature and keep the first preset time, the cooling process is to cool the SOC film to a second preset temperature and keep the second preset time, the first preset temperature is greater than the second preset temperature, and the first preset temperature and the second preset temperature are both 155-185 ℃;
step S300: baking the SOC film to harden the SOC film; the method comprises the steps of,
step S400: and forming a photoresist layer on the SOC film and performing a photolithography process.
Specifically, please refer to fig. 2 a-5 b, which are schematic structural diagrams corresponding to corresponding steps of the method for manufacturing a semiconductor structure according to the present embodiment. Next, a method for manufacturing the semiconductor structure according to the present embodiment will be described in detail with reference to fig. 2a to 5 b.
Fig. 2b is a schematic cross-sectional view along the AA direction of fig. 2a, referring to fig. 2a and fig. 2b, step S100 is performed to provide the silicon wafer, where the silicon wafer includes a substrate 100, a gate structure 200 and a dielectric layer 300, the gate structure 200 is located on the substrate 100, and the dielectric layer 300 covers the substrate 100 and the gate structure 200.
Structures such as source/drain regions, trench 301 isolation structures and the like may be formed in the substrate 100, the dielectric layer 300 has a plurality of trenches 301 therein, the trenches 301 extend from the surface of the dielectric layer 300 to penetrate through the dielectric layer 300 and expose the source/drain regions in the substrate 100, and the trenches 301 are contact holes for leading out the source/drain regions, and have a depth of about 2500 angstroms.
Referring to fig. 3, an SOC material is coated on the silicon wafer to form an SOC film 401, and the SOC film 401 covers the dielectric layer 300 and fills a portion of the depth of the trench 301. When the SOC material is coated, the silicon wafer can be placed on a rotary table, the rotary table drives the silicon wafer to rotate, meanwhile, the SOC material is dripped into the center of the silicon wafer, and when the silicon wafer rotates, the SOC material in the center of the silicon wafer diffuses to the edge of the silicon wafer under the action of centrifugal force until an SOC film with a preset thickness is formed.
It should be noted that, because the depth-width ratio of the trench 301 is large, the pattern is too dense, and the mobility of the SOC material is poor and the filling capability is insufficient at normal temperature, the SOC material is difficult to enter the bottommost portion of the trench 301, so that the SOC film 401 can only fill a part of the depth of the trench 301, and at this time, the surface flatness of the SOC film 401 is poor.
Step S200 is performed to rapidly heat the SOC film 401 to a third predetermined temperature and hold for a third predetermined time, for example, the SOC film 401 may be rapidly heated to 160 ℃ and hold for 20S.
As an alternative embodiment, the third predetermined temperature may be 155 ℃ to 165 ℃, and the third predetermined time may be 17s to 23s, but should not be limited thereto.
Next, at least one heating process and at least one cooling process are alternately performed. Wherein the temperature increasing process is to increase the temperature of the SOC film 401 to a first predetermined temperature and hold for a first predetermined time, for example, the SOC film 401 may be increased to 180 ℃ and hold for 20s. The temperature reduction process is to reduce the temperature of the SOC film 401 to a second predetermined temperature for a second predetermined time, for example, the SOC film 401 may be reduced to 160 ℃ and maintained for 20s.
The first predetermined temperature and the second predetermined temperature are 155 ℃ to 185 ℃, and the first predetermined temperature is greater than the second predetermined temperature and the third predetermined temperature. Because the SOC material has better fluidity at 155-185 ℃ and can not harden, the temperature is circularly increased and decreased in the temperature range, and the filling capacity of the SOC material can be improved. As shown in fig. 4, after the temperature increasing process and the temperature decreasing process are alternately performed at least once, the surface flatness of the SOC film 401 is improved.
As an alternative embodiment, the first predetermined temperature may be 175 ℃ to 185 ℃, the second predetermined temperature may be 155 ℃ to 165 ℃, and the first predetermined time and the second predetermined time may be 17s to 23s, but should not be limited thereto.
In this embodiment, when the temperature raising process and the temperature lowering process are performed, the silicon wafer may be rotated at a predetermined rotation speed, for example, the silicon wafer may be rotated at a speed of 100r/min, and the filling capability of the SOC film 401 may be further improved when the silicon wafer is rotated due to the good fluidity of the SOC material at this time.
As an alternative embodiment, the predetermined rotation speed is 90r/min to 110r/min, but the rotation speed is not limited thereto.
Further, the rotation direction of the silicon wafer may be changed every third predetermined time when the silicon wafer is rotated, for example, the rotation direction of the silicon wafer may be changed every 20s, and the filling capability of the SOC film 401 may be further improved by the forward rotation and the reverse rotation of the silicon wafer.
As an alternative embodiment, the third predetermined time is 17s to 23s, but should not be limited thereto.
Step S300 is performed to bake the SOC film 401, and the silicon wafer stops rotating during baking. Specifically, the SOC film 401 may be heated to a temperature of 235 to 255 ℃ and maintained for 55 to 75 seconds, so that the SOC material rapidly undergoes a Cross-linking reaction (Cross Link) to harden the SOC film 401. After that, the SOC film 401 is cooled to room temperature.
Fig. 5b is a schematic cross-sectional view of fig. 5a along the AA direction, referring to fig. 5a and 5b, step S400 is performed to form a photoresist layer on the SOC film 401 and perform a photolithography process to form a plurality of holes 302, where the holes 302 extend from the surface of the dielectric layer 300 to penetrate the dielectric layer 300 and expose the gate structure 200 on the substrate 100, and the holes 302 are used as contact holes for guiding out the gate structure 200, and have a depth of about 700 a. Since the surface flatness of the SOC film 401 is improved, the depth of focus of the photolithography process can be ensured, and the line width uniformity and the rounding degree of photolithography can be improved.
FIG. 6 is a graph showing the comparison of temperature curves between the SOC film formed and the cured SOC film in the prior art and in the present example. As shown in fig. 6, in the prior art, the SOC film is directly baked and hardened after being formed, but in this embodiment, the SOC film is rapidly heated to 160 ℃ and maintained for 20s; heating the SOC film to 180 ℃ at a speed of 5 ℃/S and maintaining for 20 seconds; cooling the SOC film to 160 ℃ at a speed of 5 ℃/S and keeping for 20 seconds; heating the SOC film to 180 ℃ at a speed of 5 ℃/S and maintaining for 20 seconds; cooling the SOC film to 160 ℃ at a speed of 5 ℃/S and keeping for 20 seconds; the SOC film was then warmed to 250℃and held for 60 seconds.
Through testing, by adopting the existing scheme, the SOC film is subjected to photoetching after being hardened, the focal depth is 45nm, the line width uniformity is 4.3nm, the roundness is 5.2nm, and the figure outline of a hole formed by photoetching is shown in figure 7 a. By adopting the scheme of the embodiment, photoetching is carried out after the SOC film is hardened, the focal depth is 60nm, the line width uniformity is 3.7nm, the roundness is 4.5nm, and the figure outline of the hole formed by photoetching is shown in figure 7 b. Therefore, the embodiment can ensure the focal depth of the photoetching process and improve the linewidth uniformity and the roundness of photoetching.
Example two
In the first embodiment, after the hole 302 is formed, as shown in fig. 8, an SOC material is coated on the silicon wafer to form an SOC film 402, and the SOC film 402 covers the dielectric layer 300 and fills a part of the depth of the trench 301 and the hole 302. When the SOC material is coated, the silicon wafer can be placed on a rotary table, the rotary table drives the silicon wafer to rotate, meanwhile, the SOC material is dripped into the center of the silicon wafer, and when the silicon wafer rotates, the SOC material in the center of the silicon wafer diffuses to the edge of the silicon wafer under the action of centrifugal force until an SOC film with a preset thickness is formed.
It should be noted that, because the depth-width ratio of the trench 301 is large, the pattern is too dense, and the mobility of the SOC material at normal temperature is poor, and the filling capability is insufficient, the SOC material is difficult to enter the trench 301 and the bottom of the hole 302, so the SOC film 402 can only fill part of the depths of the trench 301 and the hole 302, and at this time, the surface flatness of the SOC film is poor.
Next, the SOC film 402 is rapidly warmed to a third predetermined temperature and held for a third predetermined time, for example, the SOC film 402 may be rapidly warmed to 160 ℃ and held for 20s.
As an alternative embodiment, the third predetermined temperature may be 155 ℃ to 165 ℃, and the third predetermined time may be 17s to 23s, but should not be limited thereto.
Next, at least one heating process and at least one cooling process are alternately performed. Wherein the temperature increasing process is to increase the temperature of the SOC film 402 to a first predetermined temperature and hold for a first predetermined time, for example, the SOC film 402 may be increased to 180 ℃ and hold for 20s. The cooling process is to cool the SOC film 402 to a second predetermined temperature for a second predetermined time, for example, the SOC film 402 may be cooled to 160 ℃ and maintained for 20s.
The first predetermined temperature and the second predetermined temperature are 155 ℃ to 185 ℃, and the first predetermined temperature is greater than the second predetermined temperature and the third predetermined temperature. Because the SOC material has better fluidity at 155-185 ℃ and can not harden, the temperature is circularly increased and decreased in the temperature range, and the filling capacity of the SOC material can be improved. As shown in fig. 9, after the temperature increasing process and the temperature decreasing process are alternately performed at least once, the surface flatness of the SOC film 402 is improved.
As an alternative embodiment, the first predetermined temperature may be 175 ℃ to 185 ℃, the second predetermined temperature may be 155 ℃ to 165 ℃, and the first predetermined time and the second predetermined time may be 17s to 23s, but should not be limited thereto.
In this embodiment, when the temperature raising process and the temperature lowering process are performed, the silicon wafer may be rotated at a predetermined rotation speed, for example, the silicon wafer may be rotated at a speed of 100r/min, and the filling capability of the SOC membrane 402 may be further improved when the silicon wafer is rotated due to the good fluidity of the SOC material at this time.
As an alternative embodiment, the predetermined rotation speed is 90r/min to 110r/min, but the rotation speed is not limited thereto.
Further, the silicon wafer may change the rotation direction every third predetermined time when it is rotated, for example, the silicon wafer may change the rotation direction every 20s, and the filling ability of the SOC film 402 may be further improved by the forward rotation and the reverse rotation of the silicon wafer.
As an alternative embodiment, the third predetermined time is 17s to 23s, but should not be limited thereto.
Thereafter, the SOC film 402 is baked, and the wafer stops rotating during baking. Specifically, the SOC film 402 may be heated to a temperature between 235 ℃ and 255 ℃ and maintained for 55s to 75s, so that the SOC material rapidly undergoes a Cross-linking reaction (Cross Link) to harden the SOC film 402. After that, the SOC film 402 is cooled to room temperature.
Referring to fig. 10, a photoresist layer is formed on the SOC film 402 and a photolithography process is performed to form a plurality of holes 303, wherein the holes 303 extend from the surface of the dielectric layer 300 to penetrate the dielectric layer 300 and expose the gate structure 200 on the substrate 100, and the holes 303 and the holes 302 together serve as a contact hole for guiding out the gate structure 200, and the depth is about 700 a. Since the surface flatness of the SOC film 402 is improved, the depth of focus of the photolithography process can be ensured, and the uniformity and roundness of the line width of the photolithography can be improved.
In summary, in the method for manufacturing a semiconductor structure provided by the embodiment of the present invention, after an SOC film is formed on a silicon wafer, at least one heating process and a cooling process are alternately performed, where the heating process is to heat the SOC film to a first predetermined temperature and maintain the first predetermined time, the cooling process is to cool the SOC film to a second predetermined temperature and maintain the second predetermined time, the first predetermined temperature is greater than the second predetermined temperature, and both the first predetermined temperature and the second predetermined temperature are 155 ℃ to 185 ℃, and since the SOC material has a better fluidity and does not harden in 155 ℃ to 185 ℃, the heating and cooling are cyclically performed in this temperature interval, so that the filling capability of the SOC material can be improved; and then the SOC film is hardened and the subsequent photoetching process is carried out, so that the focal depth of the photoetching process can be ensured and the linewidth uniformity and the roundness of photoetching can be improved at the same time because the surface evenness of the SOC film is improved.
It should be noted that, in the present description, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different manner from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. For the system disclosed in the embodiment, the description is relatively simple because of corresponding to the method disclosed in the embodiment, and the relevant points refer to the description of the method section.
It should be further noted that although the present invention has been disclosed in the preferred embodiments, the above embodiments are not intended to limit the present invention. Many possible variations and modifications of the disclosed technology can be made by anyone skilled in the art without departing from the scope of the technology, or the technology can be modified to be equivalent. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present invention still fall within the scope of the technical solution of the present invention.
It should be further understood that the terms "first," "second," "third," and the like in this specification are used merely for distinguishing between various components, elements, steps, etc. in the specification and not for indicating a logical or sequential relationship between the various components, elements, steps, etc., unless otherwise indicated.
It should also be understood that the terminology described herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses, and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood as having the definition of a logical "or" rather than a logical "exclusive or" unless the context clearly indicates the contrary. Furthermore, implementation of the methods and/or apparatus in embodiments of the invention may include performing selected tasks manually, automatically, or in combination.
Claims (9)
1. A method of fabricating a semiconductor structure, comprising:
providing a silicon wafer, and coating an SOC material on the silicon wafer to form an SOC film;
alternately executing at least one heating process and a cooling process, wherein the heating process is to heat the SOC film to a first preset temperature and keep the first preset time, the cooling process is to cool the SOC film to a second preset temperature and keep the second preset time, the first preset temperature is greater than the second preset temperature, the first preset temperature and the second preset temperature are both 155-185 ℃, and the silicon wafer rotates at a preset rotating speed when the heating process and the cooling process are executed;
baking the SOC film to harden the SOC film; and
and forming a photoresist layer on the SOC film and performing a photolithography process.
2. The method of manufacturing a semiconductor structure according to claim 1, wherein the first predetermined temperature is 175 ℃ to 185 ℃ and the second predetermined temperature is 155 ℃ to 165 ℃.
3. The method of manufacturing a semiconductor structure according to claim 1, wherein the first predetermined time and the second predetermined time are each 17s to 23s.
4. The method of manufacturing a semiconductor structure according to claim 1, wherein the predetermined rotational speed is 90r/min to 110r/min.
5. The method of manufacturing a semiconductor structure according to claim 1, wherein the silicon wafer changes a rotation direction every third predetermined time while rotating.
6. The method of manufacturing a semiconductor structure according to claim 5, wherein the third predetermined time is 17s to 23s.
7. The method for manufacturing a semiconductor structure according to any one of claims 1 to 3, further comprising, before performing the temperature increasing process:
heating the SOC film to a third preset temperature which is less than the first preset temperature and is 155-165 ℃, and keeping for a third preset time which is 17-23 s.
8. The method of claim 1, wherein the silicon wafer has a plurality of holes and trenches extending from a surface of the silicon wafer into the silicon wafer, the SOC film covering the surface of the silicon wafer and filling at least a portion of the depth of the holes and trenches.
9. The method of manufacturing a semiconductor structure according to claim 1, wherein the step of baking the SOC film to harden the SOC film comprises:
heating the SOC film to 235-255 ℃ and maintaining for 55-75 s; the method comprises the steps of,
the SOC film was cooled to room temperature.
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| US11901189B2 (en) * | 2020-02-27 | 2024-02-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Ambient controlled two-step thermal treatment for spin-on coating layer planarization |
| US11476108B2 (en) * | 2020-08-03 | 2022-10-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Spin on carbon composition and method of manufacturing a semiconductor device |
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| CN101355034A (en) * | 2007-07-27 | 2009-01-28 | 中芯国际集成电路制造(上海)有限公司 | Method for forming photoetch pattern and method for manufacturing dual-damascene structure |
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