CN116225318A

CN116225318A - Command scheduling method, flash memory controller, flash memory device and storage medium

Info

Publication number: CN116225318A
Application number: CN202211697265.2A
Authority: CN
Inventors: 印中举; 黄运新; 杨亚飞
Original assignee: Shenzhen Dapu Microelectronics Co Ltd
Current assignee: Shenzhen Dapu Microelectronics Co Ltd
Priority date: 2022-12-28
Filing date: 2022-12-28
Publication date: 2023-06-06

Abstract

The embodiment of the application relates to the field of storage equipment application, and discloses a command scheduling method, a flash memory controller, flash memory equipment and a storage medium. Acquiring a read command and issuing the read command to a high-priority first-in first-out queue, wherein the read command comprises at least one instruction; each instruction in the high priority first-in-first-out queue is executed. By storing the write command in the low priority first-in first-out queue, issuing the acquired read command to the high priority first-in first-out queue and executing each instruction in the high priority first-in first-out queue, the method and the device can enable the read command issued later to be executed in preference to the write command issued earlier under the condition of maintaining the total bandwidth, and therefore delay of the read command is reduced.

Description

Command scheduling method, flash memory controller, flash memory device and storage medium

Technical Field

The present invention relates to the field of storage device applications, and in particular, to a command scheduling method, a flash memory controller, a flash memory device, and a storage medium.

Background

Flash memory devices, for example: a solid state disk (Solid State Drives, SSD), which is a memory device using a semiconductor Flash memory (NAND Flash) as a medium, has a main component including a Flash memory medium, a Flash memory controller, a Dynamic Random Access Memory (DRAM), and the like. An important function of the flash memory controller is to perform a storage operation as a driver of the flash memory chip, and its main operations include erase, write, and read.

As the functions of flash memory become more and more complex, it becomes more and more difficult for a solidified flash memory controller to meet the flexible control requirements of flash memory, and part of flash memory controllers begin to add coprocessors (Coprocessing Center Process Unit, S-CPUs) to optimize the flexibility of flash memory operations by combining software and hardware.

However, under the condition of considering cost and power consumption, the coprocessor used by the flash memory controller is as small as possible, so that the computational power of the coprocessor is usually relatively high, the coprocessor can fill a hardware first-in first-out queue (FIFO) as much as possible, however, when a new read command comes, the processing of the new read command can be started only after the issued command in the hardware FIFO is completed, which leads to a relatively large delay of the read command.

Disclosure of Invention

The embodiment of the application provides a command scheduling method, a flash memory controller, flash memory equipment and a storage medium, which can enable a read command issued later to be executed in preference to a write command issued earlier under the condition of maintaining the total bandwidth, thereby reducing the delay of the read command.

The embodiment of the application provides the following technical scheme:

in a first aspect, an embodiment of the present application provides a command scheduling method, applied to a flash memory controller, where the flash memory controller includes a high priority first-in first-out queue and a low priority first-in first-out queue, where the low priority first-in first-out queue is used for storing write commands;

the command scheduling method comprises the following steps:

acquiring a read command and issuing the read command to a high-priority first-in first-out queue, wherein the read command comprises at least one instruction;

each instruction in the high priority first-in-first-out queue is executed.

In some embodiments, prior to acquiring the read command, the method includes:

a high priority fifo queue and a low priority fifo queue are determined.

In some embodiments, the method further comprises:

the method comprises the steps of obtaining a write command and issuing the write command to a low priority first-in first-out queue, wherein the write command comprises at least one instruction.

In some embodiments, the flash memory controller further comprises an arbitration module for deciding to execute instructions in the first-in-first-out queue;

the method further comprises the steps of:

the control arbitration module selects one first-in first-out queue from the high priority first-in first-out queue and the low priority first-in first-out queue, and executes the instruction in the selected first-in first-out queue.

In some embodiments, controlling the arbitration module to select one of the high priority fifo and the low priority fifo and execute instructions in the selected fifo, comprises:

preferentially executing instructions in the high priority first-in first-out queue;

if the instruction in the low priority first-in first-out queue is not executed within the preset time, executing one instruction in the low priority first-in first-out queue;

instructions in the high priority fifo queue continue to execute.

In some embodiments, the method further comprises:

executing the instructions in the low priority first-in first-out queue when all instructions in the high priority first-in first-out queue are executed;

if there is a new instruction in the high priority first-in first-out queue, continuing to execute the instruction in the high priority first-in first-out queue.

In some embodiments, each instruction is an atomic instruction, each atomic instruction being executed continuously during execution.

In some embodiments, the flash memory controller includes at least one channel, each channel including a high priority first-in-first-out queue and a low priority first-in-first-out queue.

In a second aspect, an embodiment of the present application provides a flash memory controller, applying the command scheduling method of the first aspect, where the flash memory controller includes:

a high priority first-in first-out queue for storing read commands, wherein the read commands comprise at least one instruction;

a low priority first-in first-out queue for storing write commands, wherein the write commands include at least one instruction;

and the arbitration module is used for deciding to execute the instructions in the first-in first-out queue.

In a third aspect, an embodiment of the present application provides a flash memory device, including:

a flash memory controller as in the second aspect;

at least one flash memory medium is in communication with the flash memory controller.

In a fourth aspect, embodiments of the present application also provide a non-transitory computer-readable storage medium storing computer-executable instructions that, when executed by a processor, cause the processor to perform the command scheduling method of the first aspect.

The beneficial effects of the embodiment of the application are that: in comparison with the prior art, the command scheduling method provided in the embodiment of the present application is applied to a flash memory controller, where the flash memory controller includes a high priority first-in first-out queue and a low priority first-in first-out queue, and the low priority first-in first-out queue is used for storing write commands, and the command scheduling method includes: acquiring a read command and issuing the read command to a high-priority first-in first-out queue, wherein the read command comprises at least one instruction; each instruction in the high priority first-in-first-out queue is executed. By storing the write command in the low priority first-in first-out queue, issuing the acquired read command to the high priority first-in first-out queue and executing each instruction in the high priority first-in first-out queue, the method and the device can enable the read command issued later to be executed in preference to the write command issued earlier under the condition of maintaining the total bandwidth, and therefore delay of the read command is reduced.

Drawings

One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which the figures of the drawings are not to be taken in a limiting sense, unless otherwise indicated.

Fig. 1 is a schematic structural diagram of a flash memory device according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of a flash memory controller according to an embodiment of the present application;

FIG. 3 is a schematic diagram of command scheduling provided by an embodiment of the present application;

fig. 4 is a schematic flow chart of a command scheduling method according to an embodiment of the present application;

FIG. 5 is a schematic diagram of another embodiment of a flash memory controller;

FIG. 6 is a schematic diagram of an arbitration module according to an embodiment of the present application;

FIG. 7 is a flow chart of a decision to execute an instruction in a first-in-first-out queue according to an embodiment of the present application;

fig. 8 is a schematic diagram of the refinement flow of step S701;

FIG. 9 is a flow chart of another decision-making instruction in a FIFO queue according to an embodiment of the present application;

FIG. 10 is a schematic diagram of another command schedule provided by an embodiment of the present application;

fig. 11 is a schematic structural diagram of another flash memory controller according to an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.

It should be noted that, if not conflicting, the various features in the embodiments of the present application may be combined with each other, which is within the protection scope of the present application. In addition, while functional block division is performed in a device diagram and logical order is shown in a flowchart, in some cases, the steps shown or described may be performed in a different order than the block division in the device, or in the flowchart. Moreover, the words "first," "second," "third," and the like as used herein do not limit the data and order of execution, but merely distinguish between identical or similar items that have substantially the same function and effect.

The following specifically describes the technical scheme of the present application with reference to the drawings of the specification:

referring to fig. 1, fig. 1 is a schematic structural diagram of a flash memory device according to an embodiment of the present application;

as shown in fig. 1, the flash memory device 100 includes a flash memory medium 110 and a controller 120 connected to the flash memory medium 110. The flash memory device 100 is in communication connection with the host 200 through a wired or wireless manner, so as to implement data interaction.

The Flash memory medium 110, which is a storage medium of the Flash memory device 100, is also called a Flash memory, a NAND Flash, a Flash memory or Flash particles, belongs to one type of memory device, is a nonvolatile memory, and can store data for a long time even without current supply, and has storage characteristics equivalent to a hard disk, so that the Flash memory medium 110 becomes a base of storage media of various portable digital devices.

The controller 120 includes a processor 121, a buffer 122, a flash memory controller 123, and an interface 124.

The processor 121 is connected to the buffer 122, the flash memory controller 123 and the interface 124, where the processor 121 and the buffer 122, the flash memory controller 123 and the interface 124 may be connected by a bus or other manners, and the processor is configured to execute nonvolatile software programs, instructions and modules stored in the buffer 122, so as to implement any method embodiment of the present application. On this basis, through firmware development, it is also used for the core processing of the flash translation layer (Flash translation layer, FTL).

The buffer 122 is mainly used for buffering the read/write command sent by the host 200 and the read data or write data obtained from the flash memory medium 110 according to the read/write command sent by the host 200.

The flash controller 123 is connected to the flash medium 110, the processor 121 and the buffer 122, and is used for accessing the flash medium 110 at the back end and managing various parameters and data I/O of the flash medium 110.

The interface 124 is connected to the host 200 and the processor 121 and the buffer 122, and is configured to receive data sent by the host 200, or receive data sent by the processor 121, so as to implement data transmission between the host 200 and the processor 121, where the interface 124 may be a SATA-2 interface, a SATA-3 interface, a SAS interface, a MSATA interface, a PCI-E interface, a ngf interface, a CFast interface, a SFF-8639 interface, and an m.2nvme/SATA protocol.

Referring to fig. 2, fig. 2 is a schematic structural diagram of a flash memory controller according to an embodiment of the present application;

as shown in fig. 2, the flash memory controller includes a plurality of Channels (CH), for example: channel 0 (CH 0), channel 1 (CH 1), … …, and channel 15 (CH 15), each Channel (CH) includes a first-in-first-out queue (First Input First Output, FIFO), and at least one flash memory chip (Die) is mounted under each Channel (CH), for example: channel 0 (CH 0) downloads flash chip 0 (Die 0), flash chip 1 (Die 1), flash chip 2 (Die 2) and flash chip 3 (Die 3), channel 1 (CH 1) downloads flash chip 4 (Die 4), flash chip 5 (Die 5), flash chip 6 (Die 6) and flash chip 7 (Die 7), … …, channel 15 (CH 15) downloads flash chip 60 (Die 60), flash chip 61 (Die 61), flash chip 62 (Die 62) and flash chip 63 (Die 63), wherein multiple flash chips (Die) under the same channel share a set of control buses (bus).

Wherein a first-in first-out queue (FIFO) is used to buffer read and/or write commands and follow a first-in first-out rule, i.e. the first command written to the queue is also the first command fetched from the queue. A plurality of flash memory chips (Die) are packaged in one flash memory particle, and the flash memory chips (Die) are basic units for receiving and executing flash memory commands, and one flash memory chip (Die) can only independently execute one command at a time.

It will be appreciated that one important function of a flash memory controller is to perform a storage operation as a drive for a flash memory chip (Die), the main operations of which include erase, write and read. The erase operation of a flash memory medium is in units of blocks (blocks), and the write and read operations are in units of pages (pages), one Block typically containing hundreds or thousands of pages.

Specifically, after the flash memory controller issues the erase command and the address, the flash memory medium starts to perform the erase operation, which generally requires several milliseconds, and during this period, the flash memory controller cannot perform other erase or read/write operations on the flash memory medium, and needs to wait for the erase to be completed.

Specifically, after the flash memory controller issues a write command and an address and transmits write data, the flash memory medium starts to perform write operation, which generally needs to consume hundreds of microseconds to several milliseconds, and during this period, the flash memory controller cannot perform other erasing or read/write operations on the flash memory medium, and needs to wait for the write to be completed.

Specifically, after the flash memory controller issues the read command and address, the flash memory medium starts to perform the read operation, which generally needs to consume tens of microseconds, and during this period, the flash memory controller cannot perform other erasing or read/write operations on the flash memory medium, and needs to wait for the completion of the read operation. After the reading is completed, the data is temporarily stored in the buffer space of the flash memory medium, then the flash memory controller can start to transmit the read data, and the read command is ended after the transmission is completed.

Further, when the flash memory medium performs the erase, write and Read operations, the flash memory medium is in a Busy state, and at this time, the flash memory controller may send a Read Status command to confirm whether the flash memory medium completes the corresponding command, thereby confirming whether the subsequent operation instruction can be sent. Specifically, after the flash memory controller issues commands and data to one flash memory chip (Die), the flash memory chip (Die) executes the commands and is in a Busy state, the flash memory controller can issue commands and data to other flash memory chips (Die) through a control bus (bus), after issuing commands and data to other flash memory chips (Die), the flash memory controller can inquire whether the flash memory chip (Die) in the Busy state before sending an inquiry state (Read Status) command completes the corresponding commands, if so, the flash memory chip (Die) can issue subsequent commands, so that the bus bandwidth can be fully utilized, and the overall performance is improved.

However, as the performance of the flash memory becomes higher, the functions become more powerful and complex, and the solidified flash memory controller becomes more difficult to meet the flexible control requirements of the flash memory, part of the flash memory controller starts to add a coprocessor (Coprocessing Center Process Unit, S-CPU), and the flexibility of the flash memory operation is optimized by combining software and hardware. Flash memory controllers typically add several coprocessors (S-CPUs), each responsible for command processing for one or more Channels (CH), where a coprocessor (S-CPU) is a processor that is developed and applied to assist a central processor in completing processing tasks that it cannot execute or is inefficient to execute.

Referring to fig. 3, fig. 3 is a schematic diagram of command scheduling according to an embodiment of the present application;

in this embodiment of the present application, the flash memory controller includes a coprocessor (S-CPU), each Channel (CH) of the flash memory controller includes a first-in first-out queue (FIFO), after the flash memory device receives upper-layer commands sequentially issued by the host, the coprocessor (S-CPU) in the flash memory controller splits each upper-layer command into at least one instruction and issues the at least one instruction to the hardware first-in first-out queue (FIFO), and then issues the instruction and data to each flash memory chip mounted on the channel through a control bus (bus) of the channel, and each flash memory chip (Die) executes the corresponding command and is in a Busy (Busy) state.

As shown in fig. 3, the host issues four commands in sequence: the upper layer command A, the upper layer command B, the upper layer command C and the upper layer command D, wherein the coprocessor (S-CPU) splits the upper layer command and sequentially transmits corresponding instructions and data to the flash memory chip 0 (Die 0), the flash memory chip 1 (Die 1), the flash memory chip 2 (Die 2) and the flash memory chip 3 (Die 3) through a control bus (bus) of a channel, and each flash memory chip (Die) executes the corresponding command and is in a Busy state.

Specifically, after the coprocessor (S-CPU) acquires the upper command a, the upper command a is split to obtain an instruction A0, the instruction A0 is issued to a first-in first-out queue (FIFO), then the coprocessor (S-CPU) sequentially acquires the upper command B, the upper command C and the upper command D, the upper command B is split to obtain an instruction B0, the upper command C is split to obtain an instruction C0 and an instruction C2, the upper command D is split to obtain an instruction D0 and an instruction D2, and then the instruction B0, the instruction C0 and the instruction D0 are sequentially issued to the first-in first-out queue (FIFO).

Further, the coprocessor (S-CPU) issues corresponding instructions and data to each flash memory chip mounted on the channel through a control bus (bus) of the channel, for example: the upper command a is a write command of the flash memory chip 0 (Die 0), the command A0 is a write command and a data transfer command of the upper command a, and the first command in the first-in first-out queue (FIFO) is the command A0, so the command A0 is sent to the flash memory chip 0 (Die 0), where the data transfer command included in the command A0 takes a long time, and then the flash memory chip 0 (Die 0) starts to perform the write operation and is in a Busy state.

Further, the coprocessor (S-CPU) continues to send the next instruction B0 in the first-in-first-out queue (FIFO) to the flash memory chip 1 (Die 1), then sequentially sends the instruction C0 in the first-in-first-out queue (FIFO) to the flash memory chip 2 (Die 2), and sends the instruction D0 in the first-in-first-out queue (FIFO) to the flash memory chip 3 (Die 3). When each flash memory chip completes the read operation or the write operation exits the Busy (Busy) state, the coprocessor (S-CPU) continues to issue instructions C1, D1, A1 to the first-in-first-out queue (FIFO) in order to query whether the execution of instructions C0, D0, A0 is completed, and send instructions C1, D1, A1 in the first-in-first-out queue (FIFO) to flash memory chip 2 (Die 2), flash memory chip 3 (Die 3), flash memory chip 0 (Die 0), respectively.

Further, after obtaining that the instruction C0 and the instruction D0 are in the execution completion state, the coprocessor (S-CPU) continues to issue the instruction C2 and the instruction D2 to the first-in first-out queue (FIFO), and issues the instruction C2 and the instruction D2 in the first-in first-out queue (FIFO) to the flash memory chip 2 (Die 2) and the flash memory chip 3 (Die 3) respectively, so as to perform data transmission of the upper-layer command C and the upper-layer command D respectively, and then the execution of the upper-layer command C and the upper-layer command D is completed, and after the coprocessor (S-CPU) issues the instruction A1 and the instruction B1 in the first-in first-out queue (FIFO) to the flash memory chip 0 (Die 0) and the flash memory chip 1 (Die 1) respectively, the upper-layer command a and the upper-layer command B are completed.

Wherein, the upper command a is a write command of the flash memory chip 0 (Die 0), the upper command B is a write command of the flash memory chip 1 (Die 1), the upper command C is a read command of the flash memory chip 2 (Die 2), the upper command D is a read command of the flash memory chip 3 (Die 3), the command A0 is a write command and a data transmission command of the upper command a, the command B0 is a write command and a data transmission command of the upper command B, the command C0 is a read command of the upper command C, the command D0 is a read command of the upper command D, the command A1 is a query status command of the upper command a, the command B1 is a query status command of the upper command B, the command C1 is a query status command of the upper command C, the command C2 is a read data transmission command of the upper command C, and the command D2 is a read data transmission command of the upper command D.

It can be understood that the response delay of the flash memory device, such as a solid state disk, to the read/write command is an important indicator for judging the product quality, and the host side requires the response of the read/write command to be faster and better. After the data of the write command is transmitted from the host end to the inside of the solid state disk, the solid state disk returns a completion signal to the host end, so that the delay of writing the data into the flash memory medium is invisible to the host end; the read command must wait for the data to be read from the flash memory medium before being further transferred to the host side for completion, so the latency of the read command at the flash memory side is an important part of the latency of the entire read command.

However, the flash memory controller uses as few coprocessors (S-CPUs) as possible in consideration of cost and power consumption, so that the computational power of the coprocessors (S-CPUs) is generally intense. Therefore, the coprocessor (S-CPU) can fill the hardware first-in first-out queue (FIFO) as much as possible, so that bus waste caused by untimely scheduling of the coprocessor (S-CPU) is reduced as much as possible, and the bandwidth is improved. However, when a new read command comes, it is necessary to complete the issued command in the first-in-first-out queue (FIFO) before the new read command starts to be processed, which results in a larger delay of the read command, for example: in fig. 3, the coprocessor (S-CPU) issues the instruction A0 and the instruction B0 first, and when the read command C is received, although the instruction B0 has not yet started to be executed, the read command C0 is located in the first-in first-out queue (FIFO) and after the position of the read command C0 is located in the instruction B0, the instruction C0 can be executed only after waiting for the instruction B0 to be executed, which results in a larger read delay.

Based on this, the embodiment of the application provides a command scheduling method, so that under the condition of maintaining the total bandwidth, a later issued read command is executed in preference to an earlier issued write command, and thus delay of the read command is reduced.

Referring to fig. 4, fig. 4 is a flow chart of a command scheduling method according to an embodiment of the present application;

the command scheduling method is applied to a flash memory controller, wherein the flash memory controller comprises a high-priority first-in first-out queue (FIFO-H) and a low-priority first-in first-out queue (FIFO-L), and the low-priority first-in first-out queue is used for storing write commands.

Specifically, referring to fig. 5, fig. 5 is a schematic structural diagram of another flash memory controller according to an embodiment of the present application;

as shown in fig. 5, the flash memory controller includes at least one Channel (CH), such as: channel 0 (CH 0), channel 1 (CH 1), … …, and channel 15 (CH 15), each Channel (CH) includes a high priority first-in-first-out queue (FIFO-H) and a low priority first-in-first-out queue (FIFO-L), and at least one flash memory chip (Die) is mounted under each Channel (CH), for example: channel 0 (CH 0) downloads flash chip 0 (Die 0), flash chip 1 (Die 1), flash chip 2 (Die 2) and flash chip 3 (Die 3), channel 1 (CH 1) downloads flash chip 4 (Die 4), flash chip 5 (Die 5), flash chip 6 (Die 6) and flash chip 7 (Die 7), … …, channel 15 (CH 15) downloads flash chip 60 (Die 60), flash chip 61 (Die 61), flash chip 62 (Die 62) and flash chip 63 (Die 63), wherein multiple flash chips (Die) under the same channel share a set of control buses (bus).

In this embodiment of the present application, the flash memory controller further includes at least one coprocessor (S-CPU), where the coprocessor (S-CPU) is configured to split an upper layer command sent by the host into at least one instruction, and issue the instruction to a corresponding high priority first-in first-out queue (FIFO-H) and/or low priority first-in first-out queue (FIFO-L) through a control bus (bus).

As shown in fig. 4, the command scheduling method includes:

step S401: acquiring a read command and issuing the read command to a high-priority first-in first-out queue;

specifically, the read command includes at least one instruction, the flash memory controller receives the read command sent by the host, and controls the coprocessor (S-CPU) to split the read command into a read command and a read data transmission command, and then issues the read command to a high priority first-in-first-out queue (FIFO-H) through the control bus (bus).

In an embodiment of the present application, before acquiring a read command, the method includes:

a high priority fifo queue and a low priority fifo queue are determined.

Specifically, the flash memory controller determines a high priority first-in first-out queue (FIFO-H) and a priority first-in first-out queue (FIFO-L) before acquiring the read command and/or the write command, wherein the bit widths and depths of the high priority first-in first-out queue (FIFO-H) and the priority first-in first-out queue (FIFO-L) are the same.

In an embodiment of the present application, the method further includes:

the write command is acquired and issued to the low priority first-in-first-out queue.

Specifically, the write command includes at least one instruction, the flash memory controller receives the write command sent by the host, and controls the coprocessor (S-CPU) to split the write command into a write command and a data transmission command, and then issues the write command and the data transmission command to a low priority first-in-first-out queue (FIFO-L) through the control bus (bus).

In this embodiment of the present application, the flash memory controller further includes an arbitration module, where the arbitration module is configured to decide to execute the instruction in the first-in-first-out queue, and the arbitration module includes, but is not limited to, a Round-Robin (Round-Robin) arbiter, a Fixed-Priority arbiter, and the like. Preferably, a Fixed Priority arbiter (Fixed-Priority) is employed in embodiments of the present application.

Referring to fig. 6, fig. 6 is a schematic diagram of an arbitration module according to an embodiment of the present application;

as shown in fig. 6, the arbitration module is connected with a high priority first-in-first-out queue (FIFO-H), a priority first-in-first-out queue (FIFO-L), and a control bus (bus), respectively.

Specifically, the arbitration module has 2 different interfaces for interfacing with the high priority fifo queue and the priority fifo queue, respectively, so as to identify the source of each instruction.

Step S402: each instruction in the high priority first-in-first-out queue is executed.

Specifically, the flash controller controls the arbitration module to decide to execute each instruction in a high priority first-in-first-out queue (FIFO-H).

Referring to fig. 7, fig. 7 is a schematic flow chart of an instruction in a decision-making fifo queue according to an embodiment of the disclosure;

as shown in fig. 7, the decision to execute the flow of the instruction in the fifo queue includes:

step S701: the control arbitration module selects one first-in first-out queue from a high priority first-in first-out queue (FIFO-H) and a low priority first-in first-out queue (FIFO-L), and executes instructions in the selected first-in first-out queue.

Specifically, referring to fig. 8, fig. 8 is a schematic diagram of a refinement flow of step S701;

as shown in fig. 8, step S701: the control arbitration module selects one first-in first-out queue from the high priority first-in first-out queue and the low priority first-in first-out queue, and executes the instruction in the selected first-in first-out queue, comprising:

step S7011: preferentially executing instructions in the high priority first-in first-out queue;

specifically, the arbitration module preferentially executes the instruction in the high-priority first-in-first-out queue (FIFO-H), issues the instruction to the corresponding flash memory chip (Die) through the control bus (bus), and executes the instruction by the flash memory chip (Die).

Step S7012: judging whether the instruction in the low priority first-in first-out queue is executed in a preset time;

specifically, the preset time is configured by a register, and is determined according to the number of cycles of the hardware driving clock, for example, the clock is 600MHz, and is configured to be 600×1024, and then the preset time is 1ms.

Further, if the instruction in the low priority first-in-first-out queue (FIFO-L) is not executed within the preset time, the step S7013 is entered: executing an instruction in the low priority first-in-first-out queue; if the instruction in the low priority first-in-first-out queue (FIFO-L) is executed within the preset time, the process returns to step S7011: instructions in the high priority first-in-first-out queue are preferentially executed.

Step S7013: executing an instruction in the low priority first-in-first-out queue;

specifically, if the instruction in the low priority first-in-first-out queue (FIFO-L) is not executed within the preset time, the arbitration module issues an instruction in the low priority first-in-first-out queue (FIFO-L) to the corresponding flash memory chip (Die) through the control bus (bus), and the flash memory chip (Die) executes the instruction.

Step S7014: instructions in the high priority fifo queue continue to execute.

Specifically, after the arbitration module executes an instruction in the low priority first-in first-out queue (FIFO-L), if an instruction still exists in the high priority first-in first-out queue (FIFO-H), the arbitration module continues to issue each instruction in the high priority first-in first-out queue (FIFO-H) to a corresponding flash memory chip (Die) through the control bus (bus), and the flash memory chip (Die) executes the instruction.

In the embodiment of the application, by judging whether the instruction in the low priority first-in first-out queue is executed in the preset time, the write command can be ensured to be executed in time while the delay of the read command is reduced.

In the embodiment of the present application, each instruction in the high priority first-in-first-out queue (FIFO-H) and the low priority first-in-first-out queue (FIFO-L) is an atomic instruction, and each atomic instruction is continuously executed during the execution process, for example: the write command A0 comprises write commands A0-Cmd, write addresses A0-Addr and write Data A0-Data, is an atomic operation, cannot be interrupted and needs to be continuously executed, and the issuing sequence is as follows: start→A0-cmd→A0-addr→A0-data→end, or the issuing sequence of the atomic instruction of the read command is: the instruction between Start, 0x00, address, 0x30, end needs to be continuously executed and cannot be interrupted.

It will be appreciated that since the flash operation needs to follow a certain rule and cannot be randomly out of order, all atomic instructions begin with Start instructions and End instructions End with instructions between Start-End needing to be executed continuously and cannot be interrupted.

In the embodiment of the application, through the continuous execution of each atomic instruction in the execution process, the application can ensure that the atomic instruction is not interrupted, and is suitable for the rule of operating the atomicity of the flash memory type.

Referring to fig. 9, fig. 9 is a schematic flow chart of another decision-making execution of instructions in a fifo queue according to an embodiment of the disclosure;

as shown in fig. 9, the decision to execute the instruction in the fifo queue includes:

step S901: executing the instructions in the low priority first-in first-out queue when all instructions in the high priority first-in first-out queue are executed;

specifically, when all instructions in the high priority first-in first-out queue (FIFO-H) are executed, the arbitration module issues the instructions in the low priority first-in first-out queue (FIFO-L) to the corresponding flash memory chip (Die) through the control bus (bus), and the flash memory chip (Die) executes the instructions.

Step S902: judging whether a new instruction exists in the high-priority first-in first-out queue;

specifically, if there is a new instruction in the high priority first-in-first-out queue (FIFO-H), step S903 is performed: continuing to execute the instructions in the high priority first-in first-out queue; if there is no new instruction in the high priority first-in-first-out queue (FIFO-H), the process returns to step S901, and the instruction in the low priority first-in-first-out queue is continuously executed.

Step S903: instructions in the high priority fifo queue continue to execute.

Specifically, if there is a new instruction in the high priority first-in first-out queue (FIFO-H), the arbitration module issues each instruction in the high priority first-in first-out queue to the corresponding flash memory chip (Die) through the control bus (bus), and the flash memory chip (Die) executes the instruction until the next time the instruction in the low priority first-in first-out queue (FIFO-L) or the instruction in the high priority first-in first-out queue is not executed when the instruction in the low priority first-in first-out queue (FIFO-L) is executed.

Referring to fig. 10, fig. 10 is a schematic flow chart of another command scheduling according to the embodiment of the present application;

in this embodiment of the present application, after the flash memory device receives the upper-layer commands sequentially issued by the host, a coprocessor (S-CPU) in the flash memory controller splits each upper-layer command into at least one instruction, issues a corresponding instruction of a write command into a low priority first-in first-out queue (FIFO-L), issues a corresponding instruction of a read command into a high priority first-in first-out queue (FIFO-H), and then issues instructions and data to each flash memory chip mounted on a channel through a control bus (bus) of the channel by an arbitration module in the flash memory controller, where each flash memory chip (Die) executes the corresponding command and is in a Busy state.

As shown in fig. 10, the host sequentially issues four commands: the upper-layer command A, the upper-layer command B, the upper-layer command C and the upper-layer command D, wherein the coprocessor (S-CPU) splits the upper-layer command into at least one instruction, the at least one instruction is issued to a corresponding high-priority first-in first-out queue (FIFO-H) or a corresponding low-priority first-in first-out queue (FIFO-L), then an arbitration module decides which instruction in the first-in first-out queue is executed and sequentially issues corresponding instructions and data to the flash memory chip 0 (Die 0), the flash memory chip 1 (Die 1), the flash memory chip 2 (Die 2) and the flash memory chip 3 (Die 3) through a control bus (bus) of a channel, and each flash memory chip (Die) executes the corresponding instruction and is in a Busy state.

Specifically, after the coprocessor (S-CPU) acquires the upper command a, the upper command a is split to obtain an instruction A0, and issues the instruction A0 into a low priority first-in first-out queue (FIFO-L), then the coprocessor (S-CPU) sequentially acquires the upper command B, the upper command C and the upper command D, and splits the upper command B to obtain an instruction B0, splits the upper command C to obtain an instruction C0 and an instruction C2, splits the upper command D to obtain an instruction D0 and an instruction D2, and sequentially issues the instruction B0 into a low priority first-in first-out queue (FIFO-L), the instruction C0, and the instruction D0 into a high priority first-in first-out queue (FIFO-H).

It will be appreciated that the upper level command issues all require time, so the time for issuing instructions A0, B0, C0, D0 is sequentially incremented and not issued in parallel instantaneously. Since the instruction A0 is issued first, there is no instruction in the high priority first-in-first-out queue (FIFO-H), and there is only the instruction A0 in the low priority first-in-first-out queue (FIFO-L), the arbitration module will send the instruction A0 to the flash memory chip 0 (Die 0), and the flash memory chip 0 (Die 0) starts to perform the write operation and is in the Busy state.

Since instruction A0 also takes a period of time to execute, which is often much longer than the time that software issues a single instruction, when instruction A0 is executed, instructions C0, D0 are already in a high priority first-in-first-out queue (FIFO-H), so instructions C0, D0 may then execute preferentially. After the execution of the instruction C0 and the instruction D0 is completed, there is no instruction in the high priority first-in first-out queue (FIFO-H), so the arbitration module may then send the instruction B0 in the low priority first-in first-out queue (FIFO-L) to the flash memory chip 1 (Die 1), and the coprocessor (S-CPU) may continue to issue the instruction C1 and the instruction D1 to the high priority first-in first-out queue (FIFO-H) during the period when the flash memory chip 1 (Die 1) executes the instruction B0, and the arbitration module sends the instruction C1 and the instruction D1 to the flash memory chip 3 (Die 3) and the flash memory chip 0 (Die 0) respectively to query whether the execution of the instruction C0 and the instruction D0 is completed.

Further, after obtaining that the instruction C0 and the instruction D0 are in the execution completion state, the instruction C2 and the instruction D2 are already in a high priority first-in first-out queue (FIFO-H), the arbitration module continues to issue the instruction C2 and the instruction D2 to the flash memory chip 2 (Die 2) and the flash memory chip 3 (Die 3) respectively, so as to perform data transmission of the upper-layer command C and the upper-layer command D respectively, then the execution of the upper-layer command C and the upper-layer command D is completed, and after the arbitration module issues the instruction A1 and the instruction B1 in the low priority first-in first-out queue (FIFO-L) to the flash memory chip 0 (Die 0) and the flash memory chip 1 respectively, the execution of the upper-layer command a and the upper-layer command B is completed.

In an embodiment of the present application, a command scheduling method is provided and applied to a flash memory controller, where the flash memory controller includes a high priority fifo queue and a low priority fifo queue, and the low priority fifo queue is used for storing write commands, and the command scheduling method includes: acquiring a read command and issuing the read command to a high-priority first-in first-out queue, wherein the read command comprises at least one instruction; each instruction in the high priority first-in-first-out queue is executed. By storing the write command in the low priority first-in first-out queue, issuing the acquired read command to the high priority first-in first-out queue and executing each instruction in the high priority first-in first-out queue, the method and the device can enable the read command issued later to be executed in preference to the write command issued earlier under the condition of maintaining the total bandwidth, and therefore delay of the read command is reduced.

Referring to fig. 11 again, fig. 11 is a schematic structural diagram of another flash memory controller according to an embodiment of the present application;

as shown in fig. 11, the flash controller 111 includes at least one high priority fifo queue 1111, at least one low priority fifo queue 1112, and at least one arbitration module 1113. In fig. 11, a high priority fifo 1111, a low priority fifo 1112, and an arbitration module 1113 are taken as examples.

Specifically, the flash memory controller 111 includes at least one Channel (CH), each Channel (CH) includes a high priority fifo (first in first out) queue 1111, a low priority fifo (first in first out) queue 1112, and an arbitration module 1113, wherein the arbitration module 1113 is communicatively connected to the high priority fifo (first in first out) queue 1111 and the low priority fifo (first in first out) queue 1112 through 2 ports, respectively.

The flash memory controller 111 is configured to perform the command scheduling method in any of the above embodiments, for example: acquiring a read command and issuing the read command to a high-priority first-in first-out queue, wherein the read command comprises at least one instruction; each instruction in the high priority first-in-first-out queue is executed.

The high priority first-in first-out queue 1111 is configured to store a read command, where the read command includes at least one instruction.

A low priority first-in first-out queue 1112 for holding write commands, wherein the write commands include at least one instruction.

The arbitration module 1113 is configured to determine to execute the instruction in the fifo queue, for example: preferentially executing instructions in the high priority first-in first-out queue 111; if the instruction in the low priority first-in first-out queue 1112 is not executed within the preset time, executing an instruction in the low priority first-in first-out queue 1112; the execution of instructions in the high priority first-in-first-out queue 1111 continues. Or, when all instructions in the high priority fifo 1111 have been executed, executing instructions in the low priority fifo 1112; if there is a new instruction in the high priority first-in-first-out queue 1111, execution of the instruction in the high priority first-in-first-out queue 1111 continues.

The present application also provides a non-volatile computer storage medium storing computer-executable instructions for execution by one or more processors, e.g., to perform the command scheduling method of any of the method embodiments described above, e.g., to perform the steps described above.

The apparatus or device embodiments described above are merely illustrative, in which the unit modules illustrated as separate components may or may not be physically separate, and the components shown as unit modules may or may not be physical units, may be located in one place, or may be distributed over multiple network module units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

From the above description of embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus a general purpose hardware platform, or may be implemented by hardware. Based on such understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the related art in the form of a software product, which may be stored in a computer readable storage medium, such as ROM/RAM, a magnetic disk, an optical disk, etc., and include several instructions for up to a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method of each embodiment or some parts of the embodiments.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and are not limiting thereof; the technical features of the above embodiments or in the different embodiments may also be combined under the idea of the present application, the steps may be implemented in any order, and there are many other variations of the different aspects of the present application as above, which are not provided in details for the sake of brevity; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. The command scheduling method is characterized by being applied to a flash memory controller, wherein the flash memory controller comprises a high-priority first-in first-out queue and a low-priority first-in first-out queue, and the low-priority first-in first-out queue is used for storing write commands;

the method comprises the following steps:

acquiring a read command and issuing the read command to the high-priority first-in first-out queue, wherein the read command comprises at least one instruction;

each of the instructions in the high priority first-in-first-out queue is executed.

2. The method of claim 1, wherein prior to the acquiring the read command, the method comprises:

determining the high priority first-in first-out queue and the low priority first-in first-out queue;

the method further comprises the steps of:

and acquiring a write command and issuing the write command to the low-priority first-in-first-out queue, wherein the write command comprises at least one instruction.

3. The method of claim 1 or 2, wherein the flash memory controller further comprises an arbitration module for deciding to execute instructions in a first-in-first-out queue;

the method further comprises the steps of:

and controlling the arbitration module to select one first-in first-out queue from the high-priority first-in first-out queue and the low-priority first-in first-out queue, and executing the instruction in the selected first-in first-out queue.

4. The method of claim 3, wherein the controlling the arbitration module to select one of the high priority fifo queue and the low priority fifo queue and execute instructions in the selected fifo queue comprises:

preferentially executing the instructions in the high-priority first-in first-out queue;

and continuing to execute the instruction in the high-priority first-in first-out queue.

5. The method according to claim 4, wherein the method further comprises:

and if the high-priority first-in first-out queue has a new instruction, continuing to execute the instruction in the high-priority first-in first-out queue.

6. The method of any of claims 1-2 or 4-5, wherein each of the instructions is an atomic instruction, each of the atomic instructions being executed continuously during execution.

7. The method of any of claims 1-2 or 4-5, wherein the flash memory controller comprises at least one channel, each channel comprising one of the high priority first-in-first-out queues and one of the low priority first-in-first-out queues.

8. A flash memory controller, wherein the method of any one of claims 1-7 is applied, the flash memory controller comprising:

9. A flash memory device, comprising:

the flash memory controller of claim 8;

and the at least one flash memory medium is in communication connection with the flash memory controller.

10. A non-transitory computer readable storage medium storing computer executable instructions which, when executed by a processor, cause the processor to perform the command scheduling method of any one of claims 1-7.